projects / soc.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
capture CR 3 and 5 bit sv encodings
[soc.git] / src /
2020-11-04 Luke Kenneth Casso... move back to 3.3v on X3 VERSA ECP5 connector tree | commitdiff
2020-11-04 Tobias PlatenMMU: begin test case for 'dcbz' tree | commitdiff
2020-11-03 Tobias Platenfix broken unittest after installing power-instruction... tree | commitdiff
2020-11-03 Luke Kenneth Casso... swap jtag pinorder to match ulx3s tree | commitdiff
2020-11-03 Luke Kenneth Casso... change LVCMOS level on versa ecp5 jtag to 2.5v tree | commitdiff
2020-11-01 Cesar StraussAdd a check for liveness. tree | commitdiff
2020-10-31 Cole Poirierversa_ecp5.py add 4 arbitrarily assigned gpio pins... tree | commitdiff
2020-10-31 Cesar StraussCheck that the read and write counters differ at most... tree | commitdiff
2020-10-31 Cesar StraussRemove stray comment tree | commitdiff
2020-10-30 Luke Kenneth Casso... add JTAG extension to versa_ecp5 then we can use it tree | commitdiff
2020-10-28 Cesar StraussImplement an operand producer that talks the rel_o... tree | commitdiff
2020-10-24 Cesar StraussCreate a GTKWave document for the test ALU unit tests tree | commitdiff
2020-10-22 Luke Kenneth Casso... add query about cross-domain on the JTAG enable of WB tree | commitdiff
2020-10-22 Luke Kenneth Casso... add detection and disable of Instruction Wishbone based... tree | commitdiff
2020-10-22 Luke Kenneth Casso... add detection and disable of LoadStore Wishbone based... tree | commitdiff
2020-10-22 Luke Kenneth Casso... add JTAG enable/disable of wishbone to TestIssuer tree | commitdiff
2020-10-22 Luke Kenneth Casso... add means to JTAG interface to enable/disable "stuff... tree | commitdiff
2020-10-21 Cole Poirierversa_ecp5 adds ability to build and load for ulx3s85f... tree | commitdiff
2020-10-21 Luke Kenneth Casso... fix up asserts (check correct pads/cores) tree | commitdiff
2020-10-20 Tobias Platens/alu/fsm/g tree | commitdiff
2020-10-20 Tobias Platentest case for FSMMMUStage tree | commitdiff
2020-10-18 Cole Poirieruse random.seed to generate repro cases of the two... tree | commitdiff
2020-10-16 Luke Kenneth Casso... experiment swapping dummy trap stage over to input tree | commitdiff
2020-10-16 Luke Kenneth Casso... re-enable tests tree | commitdiff
2020-10-16 Luke Kenneth Casso... manually run coresync clock for test issuer tree | commitdiff
2020-10-16 Luke Kenneth Casso... set defaults in pspec tree | commitdiff
2020-10-16 Luke Kenneth Casso... add extra (test dummy stage in trap to see if combinato... tree | commitdiff
2020-10-16 Luke Kenneth Casso... add LGPLv3+ notice and add copyright holders tree | commitdiff
2020-10-15 Luke Kenneth Casso... add commented-out connection to JTAG in ECP5 litex tree | commitdiff
2020-10-15 Luke Kenneth Casso... wrong pspec variable in selecting pll clock tree | commitdiff
2020-10-15 Luke Kenneth Casso... sorting out missing clock somewhere tree | commitdiff
2020-10-15 Luke Kenneth Casso... use "enable" and set default actions in getopt tree | commitdiff
2020-10-15 Luke Kenneth Casso... add extra variant to litex core tree | commitdiff
2020-10-15 Luke Kenneth Casso... syntax error tree | commitdiff
2020-10-15 Luke Kenneth Casso... disable gpio in litex core tree | commitdiff
2020-10-15 Luke Kenneth Casso... enable/disable litex irqs based on variant name tree | commitdiff
2020-10-14 Cole Poirierissuer_verilog.py update to use commandline args using... tree | commitdiff
2020-10-12 Cole Poirierlitex/florent/versa_ecp5.py add arg --fpga [versa_ecp5... tree | commitdiff
2020-10-12 Cole Poirierfix ModuleNotFound/Import errors found when running... tree | commitdiff
2020-10-12 Cole Poirieradd tested working fpga compile/build/load file for... tree | commitdiff
2020-10-11 Luke Kenneth Casso... add way to bypass PLL for ECP5 and sim tree | commitdiff
2020-10-11 Luke Kenneth Casso... comment out XICS/GPIO interrupt test, causes ECP5 litex... tree | commitdiff
2020-10-11 Luke Kenneth Casso... record commands for building ECP5 tree | commitdiff
2020-10-11 Luke Kenneth Casso... litex sim.py operational tree | commitdiff
2020-10-10 Cole Poirierflorent/versa_ecp5.py remove uneccessary imports, speci... tree | commitdiff
2020-10-10 Luke Kenneth Casso... add debug start/stop to firmware_upload script tree | commitdiff
2020-10-10 Luke Kenneth Casso... add DMI status / reset to firmware upload script tree | commitdiff
2020-10-10 Luke Kenneth Casso... add first version of firmware uploader tree | commitdiff
2020-10-09 Luke Kenneth Casso... use libresoc version of c4m-jtag repo tree | commitdiff
2020-10-09 Luke Kenneth Casso... drop in "undefined" function into ISAcaller namespace tree | commitdiff
2020-10-09 Luke Kenneth Casso... rename undef to undefined (preserving the fact that... tree | commitdiff
2020-10-09 Luke Kenneth Casso... missing yields in JTAG pads test to allow settling tree | commitdiff
2020-10-09 Jacob Lifshayfinish converting mul tests to use common code tree | commitdiff
2020-10-09 Jacob Lifshayworking on splitting out common mul pipe test code tree | commitdiff
2020-10-09 Jacob Lifshayadd carry handling to pia_res_to_output tree | commitdiff
2020-10-09 Jacob Lifshaymove pia_res_to_output to common test helpers tree | commitdiff
2020-10-09 Jacob Lifshaymove mul pipe ilang test to separate file tree | commitdiff
2020-10-09 Jacob Lifshayadd undef() tree | commitdiff
2020-10-08 Luke Kenneth Casso... missing yields in JTAG pads test to allow settling tree | commitdiff
2020-10-08 Luke Kenneth Casso... minor icache cleanup tree | commitdiff
2020-10-08 Cole Poiriersecond attempt at https://bugs.libre-soc.org/show_bug... tree | commitdiff
2020-10-08 Cole Poirierremove singleton dict per https://bugs.libre-soc.org... tree | commitdiff
2020-10-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-10-08 Tobias Platenadd WIP test_pipe_caller.py for mmu tree | commitdiff
2020-10-08 Luke Kenneth Casso... add incoming PortInterface to be connected to LoadStore... tree | commitdiff
2020-10-08 Luke Kenneth Casso... JTAG boundary scan test 1st attempt tree | commitdiff
2020-10-08 Luke Kenneth Casso... rework jtag test to use JTAG class not DMITAP tree | commitdiff
2020-10-08 Luke Kenneth Casso... split out jtag util functions to separate module tree | commitdiff
2020-10-08 Cole Poirierfirst attempt at 3) of tree | commitdiff
2020-10-08 Cole Poiriermodify wb_get per 1) of https://bugs.libre-soc.org... tree | commitdiff
2020-10-07 Tobias Platenconnect mmu_done, ldst_error, cache_paradox tree | commitdiff
2020-10-07 Luke Kenneth Casso... missing invert_in field from shiftrot input record tree | commitdiff
2020-10-07 Luke Kenneth Casso... reorder / reorganise reset signals slightly tree | commitdiff
2020-10-07 Jacob Lifshayfix div tests tree | commitdiff
2020-10-07 Jacob LifshayFix forgotten test_pipe_caller changes from e0b4334c7d8... tree | commitdiff
2020-10-06 Tobias Platenremove redunant signals tree | commitdiff
2020-10-06 Luke Kenneth Casso... update comments on pimem.py tree | commitdiff
2020-10-06 Tobias Platentest_mmu_dcache_pi.py tree | commitdiff
2020-10-06 Luke Kenneth Casso... comments tree | commitdiff
2020-10-06 Luke Kenneth Casso... add ports function to DummyPLL tree | commitdiff
2020-10-06 Luke Kenneth Casso... use pdecode2.do not pdecode2.e in test_pipe_caller... tree | commitdiff
2020-10-06 Luke Kenneth Casso... skip Decode2ToOperand from PowerDecodeSubset tree | commitdiff
2020-10-06 Luke Kenneth Casso... comment SRR1 mem.exception tree | commitdiff
2020-10-06 Luke Kenneth Casso... add SRR1 setting for LDST memory exception trap tree | commitdiff
2020-10-06 Luke Kenneth Casso... passing LDSTException over to Trap Pipeline tree | commitdiff
2020-10-06 Luke Kenneth Casso... add LDSTException decode/handling in PowerDecoder2 tree | commitdiff
2020-10-06 Luke Kenneth Casso... make LDSTException fields added from list of fieldnames tree | commitdiff
2020-10-06 Luke Kenneth Casso... move LDSTException to mem_types tree | commitdiff
2020-10-06 Luke Kenneth Casso... add LDSTException to PortInterface tree | commitdiff
2020-10-06 Luke Kenneth Casso... add sdr bypass routing via JTAG boundary scan tree | commitdiff
2020-10-06 Jacob Lifshayadd divde regression test tree | commitdiff
2020-10-06 Jacob Lifshayadd moduw regression test tree | commitdiff
2020-10-06 Jacob Lifshayadd workaround for nmigen bug #502 tree | commitdiff
2020-10-06 Jacob Lifshayadd modsw regression tree | commitdiff
2020-10-06 Jacob Lifshayadd test case for divweu regression tree | commitdiff
2020-10-06 Jacob Lifshayprint regs in hex tree | commitdiff
2020-10-05 Luke Kenneth Casso... add debug / investigation print statements tree | commitdiff
2020-10-05 Jacob Lifshay`deepcopy` from cache instead of recreating parsers... tree | commitdiff
2020-10-05 Jacob Lifshayformat code tree | commitdiff
2020-10-05 Cole Poiriericache.py fix ispow2() util fn per https://bugs.libre... tree | commitdiff
next