2020-06-06 |
Luke Kenneth Casso... | noticed the regular pattern in all pipe_data.py (regspecs). |
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2020-06-05 |
Luke Kenneth Casso... | comment out CR assertion for now |
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2020-06-05 |
colepoirier | Added skeleton fu/trap/test/test_pipe_caller using |
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2020-06-05 |
colepoirier | Add trap_input_data.py for fu/trap, cookie-cut from |
tree | commitdiff |
2020-06-05 |
Tobias Platen | fix proof_datamerger (see 216#c56) |
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2020-06-05 |
Luke Kenneth Casso... | update comments |
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2020-06-05 |
Luke Kenneth Casso... | add comments and start of elaborate |
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2020-06-05 |
Luke Kenneth Casso... | more comments |
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2020-06-05 |
Luke Kenneth Casso... | more comments |
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2020-06-05 |
Luke Kenneth Casso... | a_i not b_in |
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2020-06-05 |
Luke Kenneth Casso... | add comments |
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2020-06-05 |
Luke Kenneth Casso... | experimenting with CR, not quite right |
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2020-06-05 |
colepoirier | Made small changes to fu/trap/main_stage to bring nmige... |
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2020-06-05 |
Tobias Platen | implement init function of DualPortSplitter |
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2020-06-05 |
Tobias Platen | uncomment rtlil.convert in test_l0_cache that causes... |
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2020-06-05 |
Luke Kenneth Casso... | whoops returning cr2 for cr3 regspec map |
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2020-06-05 |
Luke Kenneth Casso... | name regfile ports by name not numerical position |
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2020-06-05 |
Luke Kenneth Casso... | whoops connecting up CR in wrong order. fixing with... |
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2020-06-05 |
Luke Kenneth Casso... | fix syntax errors and use correct FastRegs (SRR0/1... |
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2020-06-05 |
Luke Kenneth Casso... | add TODO for MFSPR/MTSPR |
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2020-06-05 |
Luke Kenneth Casso... | refer to srr0/1 not a/b |
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2020-06-05 |
Luke Kenneth Casso... | add msr_copy function and use it in OP_TRAP, OP_RFID... |
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2020-06-05 |
Luke Kenneth Casso... | set SRR0 in OP_SC |
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2020-06-05 |
Luke Kenneth Casso... | add OP_RFID SRR0/SRR1 in PowerDecode2 |
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2020-06-04 |
colepoirier | Use a_i and b_i convenience variables instead of a... |
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2020-06-04 |
Luke Kenneth Casso... | testing CRs after writing: not in the right bit-order |
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2020-06-04 |
Luke Kenneth Casso... | remove unneeded code |
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2020-06-04 |
Luke Kenneth Casso... | use common TestCase class in logical |
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2020-06-04 |
Luke Kenneth Casso... | add branch test case to core |
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2020-06-04 |
Luke Kenneth Casso... | no global variables in test suites |
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2020-06-04 |
Luke Kenneth Casso... | sigh. because POWER. CR index inversion |
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2020-06-04 |
Luke Kenneth Casso... | sigh. weirdness involving bit-inversion, inconsistency... |
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2020-06-04 |
Luke Kenneth Casso... | no global variables in test suites |
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2020-06-04 |
Luke Kenneth Casso... | add ShiftRot test case (works only because CRs are... |
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2020-06-04 |
Luke Kenneth Casso... | add both logical and ALU test core |
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2020-06-04 |
Luke Kenneth Casso... | no global variables in test suites |
tree | commitdiff |
2020-06-04 |
Luke Kenneth Casso... | no global variables in test suites |
tree | commitdiff |
2020-06-04 |
Luke Kenneth Casso... | no global variables in test suites |
tree | commitdiff |
2020-06-04 |
Luke Kenneth Casso... | whoops, docstring indentation |
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2020-06-04 |
Luke Kenneth Casso... | add docstrings for read/write port connection |
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2020-06-04 |
Luke Kenneth Casso... | move core code into separate functions, for clarity |
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2020-06-04 |
Luke Kenneth Casso... | reduce amount of code in SelectableInt |
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2020-06-04 |
Luke Kenneth Casso... | oops forgot to switch write-enable off |
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2020-06-04 |
Luke Kenneth Casso... | comment clarify on core |
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2020-06-04 |
Luke Kenneth Casso... | initialise XER from simulation |
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2020-06-04 |
Luke Kenneth Casso... | messing with valid/busy signals in core test |
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2020-06-04 |
Luke Kenneth Casso... | add extra argument (not used) to regfile.py |
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2020-06-04 |
Luke Kenneth Casso... | hmmm sync-delay wport write and wen |
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2020-06-04 |
Luke Kenneth Casso... | whitespace |
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2020-06-04 |
Luke Kenneth Casso... | test actual reg values being produced in core test |
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2020-06-04 |
Luke Kenneth Casso... | use common TestCase in branch |
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2020-06-04 |
Luke Kenneth Casso... | use common TestCase in shift_rot |
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2020-06-04 |
Luke Kenneth Casso... | use common TestCase in alu |
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2020-06-04 |
Luke Kenneth Casso... | move TestCase to common location |
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2020-06-04 |
Luke Kenneth Casso... | move reg setup to earlier in test |
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2020-06-04 |
Luke Kenneth Casso... | comment out wrflag as it should already be in the fu... |
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2020-06-04 |
Luke Kenneth Casso... | test against Logical (hard-coded change) |
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2020-06-04 |
Luke Kenneth Casso... | add first cut at test core |
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2020-06-04 |
Luke Kenneth Casso... | sync onto fu.go_wr_i otherwise a loop occurs |
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2020-06-04 |
Luke Kenneth Casso... | add rdmask and issue/busy setting |
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2020-06-04 |
Luke Kenneth Casso... | remove unneeded imports |
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2020-06-04 |
Luke Kenneth Casso... | use copy of FHDLTestCase |
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2020-06-04 |
Luke Kenneth Casso... | connect up write-ports from Regfiles to FUs |
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2020-06-04 |
Luke Kenneth Casso... | docstring for AllFunctionUnits |
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2020-06-04 |
Luke Kenneth Casso... | missing a fastregs write-port |
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2020-06-04 |
Luke Kenneth Casso... | update docstring on simple/core.py |
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2020-06-04 |
Luke Kenneth Casso... | move regfile/spec organiser to separate function |
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2020-06-04 |
Luke Kenneth Casso... | mention convenience variables |
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2020-06-04 |
Luke Kenneth Casso... | rename trap to use convenience variables |
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2020-06-04 |
colepoirier | Undo damage done by deleting VHDL microwatt comments, |
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2020-06-04 |
Luke Kenneth Casso... | collate fu-enable signals |
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2020-06-04 |
Luke Kenneth Casso... | connect up Function Unit operand subsets |
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2020-06-03 |
Luke Kenneth Casso... | forgot to add in rdflag enable |
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2020-06-03 |
Luke Kenneth Casso... | whoops, regfiles are uppercase |
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2020-06-03 |
Luke Kenneth Casso... | whoops needed a bit of a reorg of the data structure... |
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2020-06-03 |
Luke Kenneth Casso... | hmmm got naming wrong in regfile-fu connectivity |
tree | commitdiff |
2020-06-03 |
Luke Kenneth Casso... | whoops names of regfiles are lower-case |
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2020-06-03 |
Luke Kenneth Casso... | munge/redirect the regfile port based on the naming |
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2020-06-03 |
Luke Kenneth Casso... | connect read-enable and src_i to regfile ports |
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2020-06-03 |
Luke Kenneth Casso... | link up PriorityPickers on read channels |
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2020-06-03 |
Luke Kenneth Casso... | put rdspecs into a different dictionary |
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2020-06-03 |
Luke Kenneth Casso... | start putting a non-production core together, |
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2020-06-03 |
Luke Kenneth Casso... | add a simple core, not intended for production use |
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2020-06-03 |
Luke Kenneth Casso... | correct comments on regspec decode map |
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2020-06-03 |
Luke Kenneth Casso... | only select xer_xo if OE enabled |
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2020-06-03 |
Luke Kenneth Casso... | decide to elaborate Refiles *into* another class, rathe... |
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2020-06-03 |
Luke Kenneth Casso... | turn RegFiles into module, add all regfiles to it |
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2020-06-03 |
Luke Kenneth Casso... | add a simple class containing all FunctionUnits |
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2020-06-03 |
Tobias Platen | more work on proof_datamerger.py |
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2020-06-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-06-03 |
Luke Kenneth Casso... | add class containing all regfiles |
tree | commitdiff |
2020-06-03 |
Luke Kenneth Casso... | whitespace |
tree | commitdiff |
2020-06-03 |
Luke Kenneth Casso... | use common get_cu_inputs for CR unit tests |
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2020-06-03 |
Luke Kenneth Casso... | convert shift_rot tests to use common get_cu_inputs... |
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2020-06-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-06-03 |
Tobias Platen | whitespace fix for proof_datamerger.py |
tree | commitdiff |
2020-06-03 |
Luke Kenneth Casso... | reorganise ALU tests, move get_cu_inputs function to... |
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2020-06-03 |
Luke Kenneth Casso... | worked out how to dynamically enable carry-in to ALU... |
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2020-06-03 |
Luke Kenneth Casso... | correct overflow-enable flags for rdmask specs in ALU |
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2020-06-03 |
Luke Kenneth Casso... | attempt to make carry-in and overflow-enable optional... |
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