Skip vector test case, and add a scalar case
[soc.git] / src /
2021-02-13 Cesar StraussSkip vector test case, and add a scalar case
2021-02-13 Cesar StraussFix imports and whitespace
2021-02-13 Luke Kenneth Casso... update svp64 unit test comments
2021-02-13 Tobias Platenforward microwatt mmu specific SPR: PID and PRTBL
2021-02-13 Luke Kenneth Casso... add SVP64 TestIssuer separate unit test
2021-02-13 Luke Kenneth Casso... split out TestRunner into separate module
2021-02-13 Cesar StraussFix SVP64 translator to yield the unaltered instruction
2021-02-12 Luke Kenneth Casso... add one SVP64 ALU test case to get started
2021-02-12 Luke Kenneth Casso... add SVSTATE to TestCase infrastructure for use in TestI...
2021-02-12 Luke Kenneth Casso... add skip of instruction if SVSTATE.VL=0 in ISACaller
2021-02-12 Luke Kenneth Casso... validate all registers to make sure no damage occurs...
2021-02-12 Luke Kenneth Casso... add srcstep and correct PC-advancing during Sub-PC...
2021-02-12 Luke Kenneth Casso... comments
2021-02-12 Luke Kenneth Casso... add in SVSTATE.srcstep update, loop from 0 to VL-1
2021-02-12 Luke Kenneth Casso... allow PC to update by 8 in SVP64 mode
2021-02-12 Luke Kenneth Casso... fix setting of SVSTATE.VL and MVL
2021-02-12 Luke Kenneth Casso... add in SVSTATE to ISACaller, not used, just passed in
2021-02-11 Luke Kenneth Casso... comments in TestIssuer for SVP64PrefixDecoder
2021-02-10 Luke Kenneth Casso... add svp64 reg decode detection to ISACaller output
2021-02-10 Luke Kenneth Casso... starting to add SVP64 register EXTRA-read and isvec...
2021-02-10 Luke Kenneth Casso... comment update
2021-02-09 colepoirieradd missing newline at end of experiment/formal/.gitignore
2021-02-09 colepoirierfix erroneous removal of proof* from experiment/formal...
2021-02-07 colepoirieradd skeleton implementation of experiment/formal/proof_...
2021-02-07 colepoiriericache.py fix formatting
2021-02-07 colepoirierModify experiment/formal/.gitignore because was prevent...
2021-02-06 Cesar StraussFix whitespace
2021-02-06 Cesar StraussExtract the fetch FSM out from the main FSM
2021-02-05 Tobias Platenfix hanging simulation
2021-02-04 Tobias Platensrc/soc/fu/mmu/fsm.py: add debug outputs for gtkwave
2021-02-04 Tobias Platenupdate test_issuer_mmu_data_path.py to handle SPRs
2021-02-04 Tobias Platenpass SPR MicroOp to MMU function unit
2021-02-03 Luke Kenneth Casso... nope - need it to be zero if not identified as svp64
2021-02-03 Luke Kenneth Casso... actually no need to mux in the svp64_rm, just the id...
2021-02-03 Luke Kenneth Casso... add SVP64PowerDecoder, extracts svp64 remap if correctl...
2021-02-01 Luke Kenneth Casso... ISACaller, in svp64 mode, read the next 32 bits when...
2021-02-01 Tobias Platenextending the GTKWave document in test_issuer when...
2021-02-01 Luke Kenneth Casso... sort out SelectableInt bit-ordering for identifying...
2021-02-01 Luke Kenneth Casso... construct the assembly-code prefix and base v3.0B in...
2021-02-01 Cesar StraussAdd GTKWave document to test_issuer
2021-01-31 Cesar StraussFix loop test and enable it
2021-01-31 Luke Kenneth Casso... start an ISACaller SVP64 unit test
2021-01-31 Luke Kenneth Casso... test SVP64 major opcode, start checking if it is EXT001...
2021-01-31 Luke Kenneth Casso... adjusting ISACaller unit test to use ISACaller.setup_one()
2021-01-31 Luke Kenneth Casso... fix ISACaller unit test
2021-01-31 Tobias Platenfix two syntax errors in src/soc/decoder/isa/caller.py
2021-01-31 Luke Kenneth Casso... SVP64 Remap Fields structures for ISACaller
2021-01-31 Luke Kenneth Casso... remove sv_rm from PowerDecoder register decoders
2021-01-31 Luke Kenneth Casso... add SVSTATE SPR sub-field accessor class to ISACaller
2021-01-31 Luke Kenneth Casso... move SVP64 Extra reg decoding into main PowerDecoder...
2021-01-31 Luke Kenneth Casso... update submodule
2021-01-30 Luke Kenneth Casso... move CR in/out SVP64 EXTRA decoders into PowerDecoder
2021-01-30 Luke Kenneth Casso... add SVP64 CR out extending to 7-bit in PowerDecoder2
2021-01-30 Luke Kenneth Casso... add SVP64 CR EXTRA field-extension, from 3-bit to 7...
2021-01-30 Luke Kenneth Casso... extend CR registers in Decode2ToExecute1Type to 7 bit
2021-01-30 Luke Kenneth Casso... add SVP64CRExtra class to PowerDecoder2, turns 3-bit...
2021-01-30 Luke Kenneth Casso... split out SVEXTRA field selection/decoding into separat...
2021-01-30 Luke Kenneth Casso... whoops update PowerDecoder2 svp64 comments, reg sizes...
2021-01-30 Luke Kenneth Casso... add SVP64 EXTRA decoding to RB, RC and RT (out) in...
2021-01-30 Luke Kenneth Casso... add first SVP64 7-bit register context decoder to Power...
2021-01-29 Luke Kenneth Casso... add SVP64RM record to PowerDecoder2
2021-01-29 Luke Kenneth Casso... increase register number sizes from 5 to 7
2021-01-29 Luke Kenneth Casso... syntax corrections, also size of maxvl was wrong
2021-01-29 Luke Kenneth Casso... add SVP64 RM (Remap) Record
2021-01-29 Luke Kenneth Casso... adjust SVP64RM class to output more PowerDecoder-friend...
2021-01-29 Luke Kenneth Casso... adjust how register copy/setup is done in PowerDecoder2
2021-01-29 Luke Kenneth Casso... add SV etype/ptype to power decoder
2021-01-29 Luke Kenneth Casso... whoops syntax error. submodule update
2021-01-29 Luke Kenneth Casso... start adding svp64 enums
2021-01-29 Luke Kenneth Casso... use new svp64-augmented csv reader in PowerDecoder
2021-01-29 Luke Kenneth Casso... whoops missed out "+" on explicit license listing
2021-01-28 Luke Kenneth Casso... add SVSTATE to StateRegs
2021-01-28 Luke Kenneth Casso... add SVState SPR Record, SVSTATERec
2021-01-28 Luke Kenneth Casso... add svp64 CR field identification for EXTRA2/3 decoding
2021-01-28 Luke Kenneth Casso... move svp64 reg-decode function to more appropriate...
2021-01-28 Luke Kenneth Casso... provide "merger" of SVP64 RM info into v3.0B CSV files
2021-01-27 Tobias Platenuse SPR constants
2021-01-27 Luke Kenneth Casso... move SVP64RM CSV class to new module
2021-01-27 Luke Kenneth Casso... whitespace and shortening of SPR MMU redirection in...
2021-01-27 Luke Kenneth Casso... also read LDST RM files
2021-01-26 Tobias Platen[Bug 580] update comment above changed block
2021-01-26 Tobias Platen[Bug 580] redirect MMU SPRs to the MMU
2021-01-25 Luke Kenneth Casso... extra comments in svp64
2021-01-24 Luke Kenneth Casso... changing svp64 asm syntax to use / instead of . as... 24jan2021_ls180
2021-01-23 Luke Kenneth Casso... move sanity-checks, add mode into svp64_rm
2021-01-23 Luke Kenneth Casso... cleanup on aisle 3 - simplify sv_mode svp64
2021-01-23 Luke Kenneth Casso... check src/dest mask exist if zeroing, svp64
2021-01-23 Luke Kenneth Casso... add predicate-result svp64 decoding
2021-01-23 Luke Kenneth Casso... add svp64 saturation decoding
2021-01-23 Luke Kenneth Casso... start decoding modes in svp64
2021-01-23 Luke Kenneth Casso... and now for something completely different...
2021-01-23 Luke Kenneth Casso... add elwidth encoding svp64, add more debug-print
2021-01-23 Luke Kenneth Casso... add svp64 subvl encoding
2021-01-23 Luke Kenneth Casso... add in svp64 predicate mask encoding
2021-01-23 Luke Kenneth Casso... capture CR 3 and 5 bit sv encodings
2021-01-23 Luke Kenneth Casso... start decoding EXTRA2/3
2021-01-23 Luke Kenneth Casso... start decoding sv EXTRAs and identifying them
2021-01-23 Luke Kenneth Casso... start to read RM CSV files
2021-01-23 Luke Kenneth Casso... add beginnings of svp64 assembly translator
2021-01-22 Luke Kenneth Casso... add example on how to access regs list for cmp
next