get fu compunit test to use ISACaller instruction-memory
[soc.git] / src /
2020-06-17 Luke Kenneth Casso... get fu compunit test to use ISACaller instruction-memory
2020-06-17 Luke Kenneth Casso... got fed up of adding arguments to ISACaller / ISA,...
2020-06-17 Luke Kenneth Casso... split execute and setup of ISACaller instruction execution
2020-06-17 Luke Kenneth Casso... comment ISACaller setup
2020-06-17 Luke Kenneth Casso... start to add in independent execution into ISACaller
2020-06-17 Luke Kenneth Casso... add a fake program counter to ISACaller
2020-06-17 Luke Kenneth Casso... use an independent power decoder in ISACaller
2020-06-17 Luke Kenneth Casso... add "respect_pc" boolean to ISACaller
2020-06-17 Luke Kenneth Casso... add optional instruction memory
2020-06-17 Luke Kenneth Casso... split out TestIssuer into separate module
2020-06-17 Luke Kenneth Casso... remove unneeded yield
2020-06-17 Luke Kenneth Casso... enable all tests again in test_core.py and test_issuer.py
2020-06-17 Luke Kenneth Casso... got test_issuer FSM operating. bit of a hack
2020-06-17 Luke Kenneth Casso... debugging test_issuer, getting FSM working
2020-06-17 Luke Kenneth Casso... output to issuer_simulator.vcd
2020-06-16 Luke Kenneth Casso... add first version unit test for TestIssuer
2020-06-16 Luke Kenneth Casso... reduce instruction depth to 6 bits in TestIssuer
2020-06-16 Luke Kenneth Casso... move debug statements to check function
2020-06-16 Luke Kenneth Casso... hack LD/ST ad/st together, allow PC to be set externally
2020-06-16 Luke Kenneth Casso... move check regs in simple core to separate function
2020-06-16 Luke Kenneth Casso... move test core reg set up into separate function
2020-06-16 Luke Kenneth Casso... set up a TestIssuer class with a FSM for doing instruct...
2020-06-16 Luke Kenneth Casso... add ports to TestMemory
2020-06-16 Luke Kenneth Casso... add beginnings of TestIssuer class, to issue instructio...
2020-06-16 Luke Kenneth Casso... weird: adding TestMemory with no port causes nmigen...
2020-06-16 Luke Kenneth Casso... refer to signals directly in Test Core
2020-06-16 Luke Kenneth Casso... add test instruction memory SRAM
2020-06-16 Luke Kenneth Casso... update popcount docstring
2020-06-15 Luke Kenneth Casso... start trying to fill in some comments in Minerva L1...
2020-06-15 Luke Kenneth Casso... whitespace cleanup
2020-06-15 Luke Kenneth Casso... imports and syntax errors fixed (found test_cache.py)
2020-06-15 Luke Kenneth Casso... more whitespace
2020-06-15 Luke Kenneth Casso... more whitespace on minerva (no unit tests, so cannot...
2020-06-15 Luke Kenneth Casso... whitespace cleanup, remove minerva DataSelector class
2020-06-15 Luke Kenneth Casso... have to set up addr/st rel-go link before setting up...
2020-06-15 Luke Kenneth Casso... add in memory setup/check but disable LDST Unit Tests...
2020-06-15 Luke Kenneth Casso... move setup/check memory into helper functions for use...
2020-06-15 Luke Kenneth Casso... whoops LDSTCompUnit was identified as a Function.ALU...
2020-06-15 Luke Kenneth Casso... add in TstL0CacheBuffer but disable temporarily
2020-06-14 Luke Kenneth Casso... add optional LDSTFunctionUnit to compunits
2020-06-14 Luke Kenneth Casso... unit tests showing byte-reverse works
2020-06-14 Luke Kenneth Casso... add sim-qemu test for byte-reversed LD/ST
2020-06-14 Luke Kenneth Casso... add in byte-reverse from op PowerDecode2 field
2020-06-14 Luke Kenneth Casso... error in address width (truncated) in setting up L0Cach...
2020-06-14 Luke Kenneth Casso... error in naming that ended up in gtkwave from a proxy
2020-06-14 Luke Kenneth Casso... add another LD/ST example to qemu-sim test,
2020-06-14 Luke Kenneth Casso... add byte-reversal on LD and ST in L0CacheBuffer
2020-06-14 Luke Kenneth Casso... reasonably certain that the careful and slow use of...
2020-06-13 Cesar StraussWait for all active rel signals to be high, and only...
2020-06-12 Luke Kenneth Casso... first cut at qemu memory dump and compare
2020-06-12 Luke Kenneth Casso... note possible BE/LE mode needed for memory reads/writes
2020-06-12 Luke Kenneth Casso... update ld/st test to see what is going on
2020-06-12 Luke Kenneth Casso... tracking down what looks like an error in the Simulator...
2020-06-12 Luke Kenneth Casso... debug printout of sim and hardware memory, shows mismat...
2020-06-12 Luke Kenneth Casso... use ALUHelpers in LDSTCompUnit test
2020-06-11 Luke Kenneth Casso... some ugly hacks that get LD/ST immediate working
2020-06-11 Luke Kenneth Casso... even more complexity in CompALUMulti, to deal with...
2020-06-11 Luke Kenneth Casso... must distinguish between rd/write xer_ca sim helpers
2020-06-11 Luke Kenneth Casso... fixing get_rd_sim_xer_ca, has to only read carry if...
2020-06-11 Luke Kenneth Casso... yield needed for unit tests to work (has to go)
2020-06-11 Luke Kenneth Casso... read and write version of get_sim_xer_ca are different
2020-06-11 Luke Kenneth Casso... use ALUHelpers in shift_rot
2020-06-11 Luke Kenneth Casso... add fast spr1/2 sim ALUHelpers
2020-06-11 Luke Kenneth Casso... rename get_sim_cr_a to get_wr_sim_cr_a for now
2020-06-10 Luke Kenneth Casso... move Decode2ToExecute1Type to separate module
2020-06-10 Luke Kenneth Casso... whitespace
2020-06-10 Michael Nolanmodify qemu.py to set qemu's cr to 0
2020-06-10 Luke Kenneth Casso... link ST.go directly to ST.rel
2020-06-10 Luke Kenneth Casso... rename unit test function in ld/st compalu_multi
2020-06-10 Luke Kenneth Casso... hmmm very confused about LD/ST CompUnit unit test
2020-06-10 Luke Kenneth Casso... wrong data structure being imported, duplicate CompLDST...
2020-06-10 Luke Kenneth Casso... remove old code
2020-06-10 Luke Kenneth Casso... set data_len in compldst_multi unit test
2020-06-10 Luke Kenneth Casso... yield ports from data_o and addr_o
2020-06-10 Luke Kenneth Casso... expand LenExpand to 4 bits in order to cover 1/2/4...
2020-06-10 Luke Kenneth Casso... got L0CacheBuffer shift/mask working on a preliminary...
2020-06-10 Luke Kenneth Casso... whitespace
2020-06-10 Luke Kenneth Casso... add use of classes in L0Cache unit tests
2020-06-10 Luke Kenneth Casso... start using unittest suite in l0_cache.py
2020-06-10 Luke Kenneth Casso... creates an import error and stops unit tests from running
2020-06-10 Luke Kenneth Casso... add in LenExpander to L0CacheBuffer, not used yet
2020-06-10 Tobias Platenmake resetless for all signals in DataMergerRecord
2020-06-10 Tobias PlatenPortInterface refactoring
2020-06-10 Tobias Platenexception if rolls in addr_split.py
2020-06-10 Luke Kenneth Casso... add link to bug 361 in FU test
2020-06-10 Luke Kenneth Casso... TODO on RA immediate-zero mode
2020-06-10 Luke Kenneth Casso... re-do cookie-cut of alu test_pipe_caller.py over to...
2020-06-10 Luke Kenneth Casso... use ALUHelpers in output stage of test_pipe_caller
2020-06-10 Luke Kenneth Casso... use sim-get helpers in ALU input fetch
2020-06-10 Luke Kenneth Casso... use ALUHelpers in output phase of test_alu_compunit.py
2020-06-10 Luke Kenneth Casso... continue ALUHelpers check alu outputs code-morph
2020-06-10 Luke Kenneth Casso... code-morph ALU output test check phase
2020-06-10 Luke Kenneth Casso... code-morph regspecmap functions, split into separate...
2020-06-10 Luke Kenneth Casso... starting on alu output check
2020-06-10 Luke Kenneth Casso... ilang file output change from alu_pipeline.il to div_pi...
2020-06-10 Luke Kenneth Casso... cookie-cut alu test_pipe_caller.py over
2020-06-10 Luke Kenneth Casso... move to common ALUHelpers for ShiftRot test_pipe_caller.py
2020-06-10 Luke Kenneth Casso... move to common ALUHelpers for Logical test_pipe_caller.py
2020-06-10 Luke Kenneth Casso... move to common ALUHelpers for CR test_pipe_caller.py
2020-06-10 Luke Kenneth Casso... move to common ALUHelpers for branch test_pipe_caller.py
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