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also read LDST RM files
[soc.git] / src /
2021-01-27 Luke Kenneth Casso... also read LDST RM files tree | commitdiff
2021-01-26 Tobias Platen[Bug 580] update comment above changed block tree | commitdiff
2021-01-26 Tobias Platen[Bug 580] redirect MMU SPRs to the MMU tree | commitdiff
2021-01-25 Luke Kenneth Casso... extra comments in svp64 tree | commitdiff
2021-01-24 Luke Kenneth Casso... changing svp64 asm syntax to use / instead of . as... 24jan2021_ls180 tree | commitdiff
2021-01-23 Luke Kenneth Casso... move sanity-checks, add mode into svp64_rm tree | commitdiff
2021-01-23 Luke Kenneth Casso... cleanup on aisle 3 - simplify sv_mode svp64 tree | commitdiff
2021-01-23 Luke Kenneth Casso... check src/dest mask exist if zeroing, svp64 tree | commitdiff
2021-01-23 Luke Kenneth Casso... add predicate-result svp64 decoding tree | commitdiff
2021-01-23 Luke Kenneth Casso... add svp64 saturation decoding tree | commitdiff
2021-01-23 Luke Kenneth Casso... start decoding modes in svp64 tree | commitdiff
2021-01-23 Luke Kenneth Casso... and now for something completely different... tree | commitdiff
2021-01-23 Luke Kenneth Casso... add elwidth encoding svp64, add more debug-print tree | commitdiff
2021-01-23 Luke Kenneth Casso... add svp64 subvl encoding tree | commitdiff
2021-01-23 Luke Kenneth Casso... add in svp64 predicate mask encoding tree | commitdiff
2021-01-23 Luke Kenneth Casso... capture CR 3 and 5 bit sv encodings tree | commitdiff
2021-01-23 Luke Kenneth Casso... start decoding EXTRA2/3 tree | commitdiff
2021-01-23 Luke Kenneth Casso... start decoding sv EXTRAs and identifying them tree | commitdiff
2021-01-23 Luke Kenneth Casso... start to read RM CSV files tree | commitdiff
2021-01-23 Luke Kenneth Casso... add beginnings of svp64 assembly translator tree | commitdiff
2021-01-22 Luke Kenneth Casso... add example on how to access regs list for cmp tree | commitdiff
2021-01-19 Tobias Platentest_issuer_mmu_data_path.py: test both ld and st instr... tree | commitdiff
2021-01-19 Tobias Platenconnect LDSTException to MMU and DCache tree | commitdiff
2021-01-19 Tobias Platenconnect wishbone bus to test memory tree | commitdiff
2021-01-18 Tobias Platenuncomment #FIXME in unit_test tree | commitdiff
2021-01-18 Tobias Platenfu/mmu/fsm.py: connect valid and load signals tree | commitdiff
2021-01-17 Tobias Platenadd test memory for simulation tree | commitdiff
2021-01-17 Tobias Platencleanup test_issuer_mmu_data_path.py tree | commitdiff
2021-01-16 Tobias Platenclean up test case for tlbie and dcbz tree | commitdiff
2021-01-16 Tobias Platenmove microwatt_mmu bool variable to pspec tree | commitdiff
2021-01-16 Tobias Platenadd new unittest: test_issuer_mmu_data_path.py tree | commitdiff
2021-01-15 Tobias Platencleanup test_non_production_core.py tree | commitdiff
2021-01-15 Tobias Platenadd microwatt_mmu boolean variable to core and compunits tree | commitdiff
2021-01-15 Tobias Platentest_non_production_core.py: fix hanging test tree | commitdiff
2021-01-15 Tobias Platentest_non_production_core.py: wire instruction decoder... tree | commitdiff
2021-01-14 Tobias Platenadd test case for mmu+NonProductionCore tree | commitdiff
2021-01-10 Tobias Platenadd microwatt mmu config option to compunits.py tree | commitdiff
2021-01-08 Tobias Platenfix broken testcase for simple core tree | commitdiff
2021-01-07 Tobias Platenset initial_sprs, cleanup mfspr testprog tree | commitdiff
2021-01-07 Tobias Platenmfspr is RT, SPR tree | commitdiff
2021-01-06 Tobias Platenfirst testcase for mmu: case_mfspr_after_invalid_load tree | commitdiff
2021-01-06 Tobias Platenfu/mmu/fsm.py: mfspr!=mtspr tree | commitdiff
2021-01-04 Tobias Platentest_countzero.py: rename output files tree | commitdiff
2021-01-01 Cesar StraussAdd zero CR test case and fix comments tree | commitdiff
2021-01-01 Cesar StraussAdd test cases with rc=1 tree | commitdiff
2021-01-01 Cesar StraussMake all ports the same size, on the test ALU tree | commitdiff
2021-01-01 Cesar StraussAdd CR output port to test cases tree | commitdiff
2021-01-01 Cesar StraussAdd CR to the output data port tree | commitdiff
2021-01-01 Cesar StraussMake output write enables independent of valid_o tree | commitdiff
2021-01-01 Cesar StraussMove NOP test case earlier tree | commitdiff
2021-01-01 Cesar StraussDisable data value output on NOP tree | commitdiff
2021-01-01 Cesar StraussAdd condition register (CR) output tree | commitdiff
2020-12-31 Cesar StraussImplement and test NOP in the test ALU tree | commitdiff
2020-12-31 Cesar StraussDon't use OP_NOP for zero-delay subtraction tree | commitdiff
2020-12-31 Cesar StraussTest first input port being masked out tree | commitdiff
2020-12-31 Cesar StraussSign extend the second input port tree | commitdiff
2020-12-31 Cesar StraussTest masked-out second input port tree | commitdiff
2020-12-31 Cesar StraussAdd sign extend to the Test ALU tree | commitdiff
2020-12-31 Cesar StraussShow rdmaskn and wrmask in GTKWave tree | commitdiff
2020-12-31 Cesar StraussUse the increment operator tree | commitdiff
2020-12-31 Cesar StraussAdd support for masked write operations tree | commitdiff
2020-12-31 Cesar StraussClarify reason for holding rdmaskn valid during the... tree | commitdiff
2020-12-31 Cesar StraussRemove previous version of the CompUnit parallel unit... tree | commitdiff
2020-12-31 Cesar StraussOnly hold the decoder signals for one cycle, along... tree | commitdiff
2020-12-30 Cesar StraussTest the rdmaskn control signal tree | commitdiff
2020-12-29 Cesar StraussRemove left-over comments. tree | commitdiff
2020-12-28 Luke Kenneth Casso... add CR1 to power_enums tree | commitdiff
2020-12-20 Cesar StraussAdd support for CXXSim simulation tree | commitdiff
2020-12-13 Cesar StraussIgnore formal verification output in the source directory tree | commitdiff
2020-12-13 Cesar StraussAllow more test cases to be run with CXXSim tree | commitdiff
2020-12-12 Luke Kenneth Casso... skip madd, not implemented tree | commitdiff
2020-12-07 Cesar StraussDisplay the instruction type as a vector on cxxsim tree | commitdiff
2020-12-06 Luke Kenneth Casso... attempt to split into two separate GPIO banks due to... tree | commitdiff
2020-12-06 Cesar StraussWhitespace tree | commitdiff
2020-12-06 Cesar StraussUpdate GTKWave documents to work with latest cxxsim tree | commitdiff
2020-12-05 Cesar StraussWrite a GTKWave document to investigate why the proof... tree | commitdiff
2020-12-05 Cesar StraussUse the DummyALU regspec and its corresponding OpSubset tree | commitdiff
2020-12-03 Luke Kenneth Casso... put ls180 litex bus width back to 32 bit temporarily tree | commitdiff
2020-12-03 Luke Kenneth Casso... argh issue with yosys ABC tree | commitdiff
2020-12-03 Luke Kenneth Casso... add 3 more 4k SRAMs, change WB bus width to 64 in ls180... tree | commitdiff
2020-11-28 Cesar StraussFix signal names: go/rel -> go_i/rel_o tree | commitdiff
2020-11-24 Cesar StraussFix some typos and whitespace tree | commitdiff
2020-11-24 Cesar StraussPort the DummyALU test case to the new parallel issuer tree | commitdiff
2020-11-23 Cesar StraussResults are now a list, so "expected" should follow... tree | commitdiff
2020-11-23 Cesar StraussParameterize the issuer on the number of operands and... tree | commitdiff
2020-11-22 Cesar StraussRefactor the ALU operation issuer into a class tree | commitdiff
2020-11-22 Cesar StraussPort the ALU test case to the new parallel test style tree | commitdiff
2020-11-22 Cesar StraussAdd a GTKWave document to the ALU test case tree | commitdiff
2020-11-22 Luke Kenneth Casso... simplify litex-core wishbone interfaces tree | commitdiff
2020-11-19 Cesar StraussSeparate input and output ports by color tree | commitdiff
2020-11-19 Cesar StraussExplain the test cases tree | commitdiff
2020-11-18 Cesar StraussSeparate individual traces for each rel_o/go_i port tree | commitdiff
2020-11-17 Tobias Platentestcase for dcbz tree | commitdiff
2020-11-16 Cesar StraussAdd a transaction counter to producers and consumers tree | commitdiff
2020-11-16 Tobias Platenadd class LoadStore1(PortInterfaceBase) tree | commitdiff
2020-11-15 Cesar StraussImplement ResultConsumer and port the Shifter unit... tree | commitdiff
2020-11-14 Cesar StraussMove the DUT driver to within the test case process tree | commitdiff
2020-11-14 Cesar StraussFix and enable the regspec test for the Shifter tree | commitdiff
2020-11-14 Luke Kenneth Casso... sigh, direction wrong in IOtypes litex core tree | commitdiff
2020-11-13 Luke Kenneth Casso... reduce number of nc in ls180 to 24 tree | commitdiff
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