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Show rdmaskn and wrmask in GTKWave
[soc.git] / src /
2020-12-31 Cesar StraussShow rdmaskn and wrmask in GTKWave tree | commitdiff
2020-12-31 Cesar StraussUse the increment operator tree | commitdiff
2020-12-31 Cesar StraussAdd support for masked write operations tree | commitdiff
2020-12-31 Cesar StraussClarify reason for holding rdmaskn valid during the... tree | commitdiff
2020-12-31 Cesar StraussRemove previous version of the CompUnit parallel unit... tree | commitdiff
2020-12-31 Cesar StraussOnly hold the decoder signals for one cycle, along... tree | commitdiff
2020-12-30 Cesar StraussTest the rdmaskn control signal tree | commitdiff
2020-12-29 Cesar StraussRemove left-over comments. tree | commitdiff
2020-12-28 Luke Kenneth Casso... add CR1 to power_enums tree | commitdiff
2020-12-20 Cesar StraussAdd support for CXXSim simulation tree | commitdiff
2020-12-13 Cesar StraussIgnore formal verification output in the source directory tree | commitdiff
2020-12-13 Cesar StraussAllow more test cases to be run with CXXSim tree | commitdiff
2020-12-12 Luke Kenneth Casso... skip madd, not implemented tree | commitdiff
2020-12-07 Cesar StraussDisplay the instruction type as a vector on cxxsim tree | commitdiff
2020-12-06 Luke Kenneth Casso... attempt to split into two separate GPIO banks due to... tree | commitdiff
2020-12-06 Cesar StraussWhitespace tree | commitdiff
2020-12-06 Cesar StraussUpdate GTKWave documents to work with latest cxxsim tree | commitdiff
2020-12-05 Cesar StraussWrite a GTKWave document to investigate why the proof... tree | commitdiff
2020-12-05 Cesar StraussUse the DummyALU regspec and its corresponding OpSubset tree | commitdiff
2020-12-03 Luke Kenneth Casso... put ls180 litex bus width back to 32 bit temporarily tree | commitdiff
2020-12-03 Luke Kenneth Casso... argh issue with yosys ABC tree | commitdiff
2020-12-03 Luke Kenneth Casso... add 3 more 4k SRAMs, change WB bus width to 64 in ls180... tree | commitdiff
2020-11-28 Cesar StraussFix signal names: go/rel -> go_i/rel_o tree | commitdiff
2020-11-24 Cesar StraussFix some typos and whitespace tree | commitdiff
2020-11-24 Cesar StraussPort the DummyALU test case to the new parallel issuer tree | commitdiff
2020-11-23 Cesar StraussResults are now a list, so "expected" should follow... tree | commitdiff
2020-11-23 Cesar StraussParameterize the issuer on the number of operands and... tree | commitdiff
2020-11-22 Cesar StraussRefactor the ALU operation issuer into a class tree | commitdiff
2020-11-22 Cesar StraussPort the ALU test case to the new parallel test style tree | commitdiff
2020-11-22 Cesar StraussAdd a GTKWave document to the ALU test case tree | commitdiff
2020-11-22 Luke Kenneth Casso... simplify litex-core wishbone interfaces tree | commitdiff
2020-11-19 Cesar StraussSeparate input and output ports by color tree | commitdiff
2020-11-19 Cesar StraussExplain the test cases tree | commitdiff
2020-11-18 Cesar StraussSeparate individual traces for each rel_o/go_i port tree | commitdiff
2020-11-17 Tobias Platentestcase for dcbz tree | commitdiff
2020-11-16 Cesar StraussAdd a transaction counter to producers and consumers tree | commitdiff
2020-11-16 Tobias Platenadd class LoadStore1(PortInterfaceBase) tree | commitdiff
2020-11-15 Cesar StraussImplement ResultConsumer and port the Shifter unit... tree | commitdiff
2020-11-14 Cesar StraussMove the DUT driver to within the test case process tree | commitdiff
2020-11-14 Cesar StraussFix and enable the regspec test for the Shifter tree | commitdiff
2020-11-14 Luke Kenneth Casso... sigh, direction wrong in IOtypes litex core tree | commitdiff
2020-11-13 Luke Kenneth Casso... reduce number of nc in ls180 to 24 tree | commitdiff
2020-11-13 Luke Kenneth Casso... reduce clkcsel ls180 width (2 pins), rename pll_18... tree | commitdiff
2020-11-13 Luke Kenneth Casso... rename and add pll lock signal to ls180 tree | commitdiff
2020-11-13 Luke Kenneth Casso... rename ls180 litex pll_48 output to pll_18 tree | commitdiff
2020-11-13 Luke Kenneth Casso... add enable/disable arguments (not ideal but it works... tree | commitdiff
2020-11-13 Luke Kenneth Casso... remove io_in/out now it is not needed for niolib tree | commitdiff
2020-11-11 Tobias Platendcbz and tlbie first test, still incomplete tree | commitdiff
2020-11-11 Tobias Platenfu/mmu/test/test_pipe_caller.py test case for mfspr tree | commitdiff
2020-11-10 Luke Kenneth Casso... add build commands to Makefile for versa ecp5 tree | commitdiff
2020-11-10 Luke Kenneth Casso... remove ClockSelect module, use DummyPLL tree | commitdiff
2020-11-10 Luke Kenneth Casso... add separate DummyPLL module, according to API discussed at tree | commitdiff
2020-11-08 Tobias Platenmmu fsm testcase: add check_fsm_outputs based on functi... tree | commitdiff
2020-11-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-11-08 Tobias Platenmmu/fsm: test case for mtspr tree | commitdiff
2020-11-07 Tobias Platenfixed a bug in src/soc/fu/mmu/fsm.py tree | commitdiff
2020-11-06 Luke Kenneth Casso... sigh sorting out litex pin-connections to sdram tree | commitdiff
2020-11-04 Luke Kenneth Casso... move back to 3.3v on X3 VERSA ECP5 connector tree | commitdiff
2020-11-04 Tobias PlatenMMU: begin test case for 'dcbz' tree | commitdiff
2020-11-03 Tobias Platenfix broken unittest after installing power-instruction... tree | commitdiff
2020-11-03 Luke Kenneth Casso... swap jtag pinorder to match ulx3s tree | commitdiff
2020-11-03 Luke Kenneth Casso... change LVCMOS level on versa ecp5 jtag to 2.5v tree | commitdiff
2020-11-01 Cesar StraussAdd a check for liveness. tree | commitdiff
2020-10-31 Cole Poirierversa_ecp5.py add 4 arbitrarily assigned gpio pins... tree | commitdiff
2020-10-31 Cesar StraussCheck that the read and write counters differ at most... tree | commitdiff
2020-10-31 Cesar StraussRemove stray comment tree | commitdiff
2020-10-30 Luke Kenneth Casso... add JTAG extension to versa_ecp5 then we can use it tree | commitdiff
2020-10-28 Cesar StraussImplement an operand producer that talks the rel_o... tree | commitdiff
2020-10-24 Cesar StraussCreate a GTKWave document for the test ALU unit tests tree | commitdiff
2020-10-22 Luke Kenneth Casso... add query about cross-domain on the JTAG enable of WB tree | commitdiff
2020-10-22 Luke Kenneth Casso... add detection and disable of Instruction Wishbone based... tree | commitdiff
2020-10-22 Luke Kenneth Casso... add detection and disable of LoadStore Wishbone based... tree | commitdiff
2020-10-22 Luke Kenneth Casso... add JTAG enable/disable of wishbone to TestIssuer tree | commitdiff
2020-10-22 Luke Kenneth Casso... add means to JTAG interface to enable/disable "stuff... tree | commitdiff
2020-10-21 Cole Poirierversa_ecp5 adds ability to build and load for ulx3s85f... tree | commitdiff
2020-10-21 Luke Kenneth Casso... fix up asserts (check correct pads/cores) tree | commitdiff
2020-10-20 Tobias Platens/alu/fsm/g tree | commitdiff
2020-10-20 Tobias Platentest case for FSMMMUStage tree | commitdiff
2020-10-18 Cole Poirieruse random.seed to generate repro cases of the two... tree | commitdiff
2020-10-16 Luke Kenneth Casso... experiment swapping dummy trap stage over to input tree | commitdiff
2020-10-16 Luke Kenneth Casso... re-enable tests tree | commitdiff
2020-10-16 Luke Kenneth Casso... manually run coresync clock for test issuer tree | commitdiff
2020-10-16 Luke Kenneth Casso... set defaults in pspec tree | commitdiff
2020-10-16 Luke Kenneth Casso... add extra (test dummy stage in trap to see if combinato... tree | commitdiff
2020-10-16 Luke Kenneth Casso... add LGPLv3+ notice and add copyright holders tree | commitdiff
2020-10-15 Luke Kenneth Casso... add commented-out connection to JTAG in ECP5 litex tree | commitdiff
2020-10-15 Luke Kenneth Casso... wrong pspec variable in selecting pll clock tree | commitdiff
2020-10-15 Luke Kenneth Casso... sorting out missing clock somewhere tree | commitdiff
2020-10-15 Luke Kenneth Casso... use "enable" and set default actions in getopt tree | commitdiff
2020-10-15 Luke Kenneth Casso... add extra variant to litex core tree | commitdiff
2020-10-15 Luke Kenneth Casso... syntax error tree | commitdiff
2020-10-15 Luke Kenneth Casso... disable gpio in litex core tree | commitdiff
2020-10-15 Luke Kenneth Casso... enable/disable litex irqs based on variant name tree | commitdiff
2020-10-14 Cole Poirierissuer_verilog.py update to use commandline args using... tree | commitdiff
2020-10-12 Cole Poirierlitex/florent/versa_ecp5.py add arg --fpga [versa_ecp5... tree | commitdiff
2020-10-12 Cole Poirierfix ModuleNotFound/Import errors found when running... tree | commitdiff
2020-10-12 Cole Poirieradd tested working fpga compile/build/load file for... tree | commitdiff
2020-10-11 Luke Kenneth Casso... add way to bypass PLL for ECP5 and sim tree | commitdiff
2020-10-11 Luke Kenneth Casso... comment out XICS/GPIO interrupt test, causes ECP5 litex... tree | commitdiff
2020-10-11 Luke Kenneth Casso... record commands for building ECP5 tree | commitdiff
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