whitespace
[soc.git] / src /
2021-03-04 Luke Kenneth Casso... whitespace
2021-03-04 Tobias Platenupdate test_caller_radix.py
2021-03-04 Tobias PlatenISACaller: add option mmu
2021-03-04 Luke Kenneth Casso... whoops microwatt already allocates SPR 720
2021-03-04 Luke Kenneth Casso... add comments from gem5-experimental mmu
2021-03-04 Luke Kenneth Casso... add cached pgtbl0/3
2021-03-04 Luke Kenneth Casso... add two functions for checking permissions, to be based...
2021-03-03 Tobias Platenadd RADIX skeleton and unit test
2021-03-03 Luke Kenneth Casso... add debug strings
2021-03-03 Luke Kenneth Casso... remove singleton pattern
2021-03-03 Luke Kenneth Casso... cur_state is a global, does not have to be passed as...
2021-03-03 Luke Kenneth Casso... set SVSTATE in TestRunner using new TestIssuer.svstate_i
2021-03-03 Luke Kenneth Casso... add svstate_i to TestIssuer which mirrors pc_i
2021-03-02 Luke Kenneth Casso... comment out changing SPR 720 because 720 is not support...
2021-03-02 Luke Kenneth Casso... sort out SPR setting in MMU
2021-03-02 Luke Kenneth Casso... operating correctly, not directing MMU SPRs to SPR...
2021-03-02 Luke Kenneth Casso... must always set ok for writing out data otherwise it...
2021-03-01 Luke Kenneth Casso... Revert "fix Bug 607 - unnecessary code added related...
2021-03-01 Luke Kenneth Casso... move SVP64 RM decoder to separate module
2021-02-28 Luke Kenneth Casso... add additional SVP64 RM decode fields
2021-02-28 Luke Kenneth Casso... start on SVP64 RM Mode decoder
2021-02-28 Luke Kenneth Casso... more SVP64 enums
2021-02-28 Luke Kenneth Casso... add SVP64 RM sub-field enums
2021-02-28 Luke Kenneth Casso... move SVP64 Extra decoders to separate module
2021-02-28 Luke Kenneth Casso... fix syntax error
2021-02-28 Luke Kenneth Casso... move SVP64PrefixDecoder to separate module
2021-02-28 Luke Kenneth Casso... add PowerDecoder.no_in_vec
2021-02-28 Luke Kenneth Casso... add svp64_instrs to power_svp64
2021-02-28 Tobias Platenfix Bug 607 - unnecessary code added related to MMU...
2021-02-28 Tobias Platenfix Bug 603 - use SPR names/numbers from sprs.csv
2021-02-27 Luke Kenneth Casso... use PowerDecoder2.no_out_vec instead of manual vector...
2021-02-27 Luke Kenneth Casso... add corresponding VL=0 unit test as from 161b7d67b...
2021-02-27 Cesar StraussAdd traces for the new FSM
2021-02-26 Cesar StraussAdd a vector case with VL == 0
2021-02-26 Luke Kenneth Casso... comment on CoreState
2021-02-26 Luke Kenneth Casso... remove sv_changed input to fetch_fsm, add it to issue_f...
2021-02-26 Luke Kenneth Casso... moving new_svstate and update_svstate into issue FSM...
2021-02-26 Luke Kenneth Casso... move fetch_insn_o into issue_fsm TestIssuer
2021-02-26 Luke Kenneth Casso... add comments, missing that VL loop ends after execution...
2021-02-26 Cesar StraussImplement a decode/issue FSM between fetch and execute
2021-02-24 Tobias Platenwb_get: write outputs to seperate logfile too
2021-02-24 Tobias Platenupdate mmu testcase
2021-02-24 Tobias Platentest_runner.py: add needed imports
2021-02-24 Luke Kenneth Casso... add comments explaining split
2021-02-24 Luke Kenneth Casso... move DecodeCROut/In (at last) out of PowerDecoderSubset...
2021-02-24 Luke Kenneth Casso... start making write_cr0 independent of DecodeCROut
2021-02-23 Tobias Platendeduplicate
2021-02-23 Luke Kenneth Casso... add note that SVSTATE has changed, this will allow...
2021-02-22 Cesar StraussFix typo when calculating PowerDecoder2.no_out_vec
2021-02-22 Luke Kenneth Casso... move setting of NIA into fetch FSM in TestIssuer
2021-02-22 Luke Kenneth Casso... whoops
2021-02-22 Luke Kenneth Casso... moving PC-setting (NIA) out of execute_fsm in TestIssuer
2021-02-22 Luke Kenneth Casso... rename inter-FSM handshake signals in TestIssuer
2021-02-21 Luke Kenneth Casso... err trying to put in some FSM handshake signals, gettin...
2021-02-21 Luke Kenneth Casso... comment for where SVSTATE FSM should go
2021-02-21 Luke Kenneth Casso... add CR out vector detection to PowerDecoder2 no_out_vec
2021-02-21 Cesar StraussThe field selection function was moved to nmutil.util
2021-02-21 Cesar StraussHide the register augmentation traces by default
2021-02-21 Luke Kenneth Casso... move execute_fsm to separate function in TestIssuer
2021-02-21 Luke Kenneth Casso... move fetch_fsm to separate function in TestIssuer
2021-02-21 Luke Kenneth Casso... add JTAG enable/disable of 4k SRAMs
2021-02-21 Cesar StraussThe new version of "sel" is smart enough to find a...
2021-02-21 Luke Kenneth Casso... add comments for Mode field in SVP64Asm
2021-02-21 Luke Kenneth Casso... comments in SVP64RMFields
2021-02-21 Cesar StraussUse the new selection field function from nmutil
2021-02-21 Cesar StraussUse symbolic values as field sizes
2021-02-21 Cesar StraussReplace all hardcoded shifts into RM by usage of SVP64R...
2021-02-21 Luke Kenneth Casso... create SVP64CROffs consts for when SVP64 Vector-of...
2021-02-20 Luke Kenneth Casso... comments on sv.add. Rc=1 unit test
2021-02-20 Luke Kenneth Casso... add in Vectorised CRs when Rc=1 into ISACaller
2021-02-20 Luke Kenneth Casso... add CR1 to DecodeCRIn/Out
2021-02-20 Luke Kenneth Casso... add some debug checking to get_pdecode_cr_out
2021-02-20 Luke Kenneth Casso... add crossreference to bug #603
2021-02-20 Luke Kenneth Casso... add more debug output to get_pdecode_cr_out
2021-02-20 Cesar StraussActually forward the field width to field_slice()
2021-02-20 Cesar StraussAssemble the SV64 prefix from its subfields using SVP64...
2021-02-20 Luke Kenneth Casso... start on CRs in SVP64 mode
2021-02-20 Luke Kenneth Casso... fix SVP64Asm Rc=1 assembly
2021-02-20 Luke Kenneth Casso... add black-box attribute to 4k SRAM cell
2021-02-20 Cesar StraussFix more MSB0 issues in comments
2021-02-20 Cesar StraussReplace more hardcoded constants with symbolic field...
2021-02-20 Luke Kenneth Casso... increment CRs based on srcstep, see what happens
2021-02-20 Luke Kenneth Casso... add litex wishbone interconnect to 4x 4k SRAMs
2021-02-20 Luke Kenneth Casso... add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer...
2021-02-20 Luke Kenneth Casso... add option for QTY 4x 4k SRAM blocks (not added yet...
2021-02-20 Luke Kenneth Casso... add Wishbone-wrapped SPBlock_512W64B8W
2021-02-20 Luke Kenneth Casso... whoops set ROM to none by mistake
2021-02-20 Luke Kenneth Casso... whoops spelling error
2021-02-20 Luke Kenneth Casso... add (unused) code for writing out SVSTATE in TestIssuer
2021-02-20 Luke Kenneth Casso... correct arguments, set microwatt_mmu=True, pass in...
2021-02-20 Luke Kenneth Casso... minor whitespace cleanup
2021-02-20 Luke Kenneth Casso... remove massive code-duplication, move simple "self...
2021-02-20 Tobias Platenmmu testcase: set MMU SPRs
2021-02-20 Tobias Platenadd rom debugger
2021-02-20 Tobias Platenadd mmu rom testcase
2021-02-18 Tobias Platenmmu: remove TestMemory
2021-02-17 Luke Kenneth Casso... declare blank classes SPEC and EXTRA2 to add MSB-to...
2021-02-17 Cesar StraussUse subfield bit selection to extract the RM SVP64...
2021-02-17 Cesar StraussReplace MSB-i by symbolic subfield indices and selectors
2021-02-17 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
next