move CR in/out SVP64 EXTRA decoders into PowerDecoder
[soc.git] / src /
2021-01-30 Luke Kenneth Casso... move CR in/out SVP64 EXTRA decoders into PowerDecoder
2021-01-30 Luke Kenneth Casso... add SVP64 CR out extending to 7-bit in PowerDecoder2
2021-01-30 Luke Kenneth Casso... add SVP64 CR EXTRA field-extension, from 3-bit to 7...
2021-01-30 Luke Kenneth Casso... extend CR registers in Decode2ToExecute1Type to 7 bit
2021-01-30 Luke Kenneth Casso... add SVP64CRExtra class to PowerDecoder2, turns 3-bit...
2021-01-30 Luke Kenneth Casso... split out SVEXTRA field selection/decoding into separat...
2021-01-30 Luke Kenneth Casso... whoops update PowerDecoder2 svp64 comments, reg sizes...
2021-01-30 Luke Kenneth Casso... add SVP64 EXTRA decoding to RB, RC and RT (out) in...
2021-01-30 Luke Kenneth Casso... add first SVP64 7-bit register context decoder to Power...
2021-01-29 Luke Kenneth Casso... add SVP64RM record to PowerDecoder2
2021-01-29 Luke Kenneth Casso... increase register number sizes from 5 to 7
2021-01-29 Luke Kenneth Casso... syntax corrections, also size of maxvl was wrong
2021-01-29 Luke Kenneth Casso... add SVP64 RM (Remap) Record
2021-01-29 Luke Kenneth Casso... adjust SVP64RM class to output more PowerDecoder-friend...
2021-01-29 Luke Kenneth Casso... adjust how register copy/setup is done in PowerDecoder2
2021-01-29 Luke Kenneth Casso... add SV etype/ptype to power decoder
2021-01-29 Luke Kenneth Casso... whoops syntax error. submodule update
2021-01-29 Luke Kenneth Casso... start adding svp64 enums
2021-01-29 Luke Kenneth Casso... use new svp64-augmented csv reader in PowerDecoder
2021-01-29 Luke Kenneth Casso... whoops missed out "+" on explicit license listing
2021-01-28 Luke Kenneth Casso... add SVSTATE to StateRegs
2021-01-28 Luke Kenneth Casso... add SVState SPR Record, SVSTATERec
2021-01-28 Luke Kenneth Casso... add svp64 CR field identification for EXTRA2/3 decoding
2021-01-28 Luke Kenneth Casso... move svp64 reg-decode function to more appropriate...
2021-01-28 Luke Kenneth Casso... provide "merger" of SVP64 RM info into v3.0B CSV files
2021-01-27 Tobias Platenuse SPR constants
2021-01-27 Luke Kenneth Casso... move SVP64RM CSV class to new module
2021-01-27 Luke Kenneth Casso... whitespace and shortening of SPR MMU redirection in...
2021-01-27 Luke Kenneth Casso... also read LDST RM files
2021-01-26 Tobias Platen[Bug 580] update comment above changed block
2021-01-26 Tobias Platen[Bug 580] redirect MMU SPRs to the MMU
2021-01-25 Luke Kenneth Casso... extra comments in svp64
2021-01-24 Luke Kenneth Casso... changing svp64 asm syntax to use / instead of . as... 24jan2021_ls180
2021-01-23 Luke Kenneth Casso... move sanity-checks, add mode into svp64_rm
2021-01-23 Luke Kenneth Casso... cleanup on aisle 3 - simplify sv_mode svp64
2021-01-23 Luke Kenneth Casso... check src/dest mask exist if zeroing, svp64
2021-01-23 Luke Kenneth Casso... add predicate-result svp64 decoding
2021-01-23 Luke Kenneth Casso... add svp64 saturation decoding
2021-01-23 Luke Kenneth Casso... start decoding modes in svp64
2021-01-23 Luke Kenneth Casso... and now for something completely different...
2021-01-23 Luke Kenneth Casso... add elwidth encoding svp64, add more debug-print
2021-01-23 Luke Kenneth Casso... add svp64 subvl encoding
2021-01-23 Luke Kenneth Casso... add in svp64 predicate mask encoding
2021-01-23 Luke Kenneth Casso... capture CR 3 and 5 bit sv encodings
2021-01-23 Luke Kenneth Casso... start decoding EXTRA2/3
2021-01-23 Luke Kenneth Casso... start decoding sv EXTRAs and identifying them
2021-01-23 Luke Kenneth Casso... start to read RM CSV files
2021-01-23 Luke Kenneth Casso... add beginnings of svp64 assembly translator
2021-01-22 Luke Kenneth Casso... add example on how to access regs list for cmp
2021-01-19 Tobias Platentest_issuer_mmu_data_path.py: test both ld and st instr...
2021-01-19 Tobias Platenconnect LDSTException to MMU and DCache
2021-01-19 Tobias Platenconnect wishbone bus to test memory
2021-01-18 Tobias Platenuncomment #FIXME in unit_test
2021-01-18 Tobias Platenfu/mmu/fsm.py: connect valid and load signals
2021-01-17 Tobias Platenadd test memory for simulation
2021-01-17 Tobias Platencleanup test_issuer_mmu_data_path.py
2021-01-16 Tobias Platenclean up test case for tlbie and dcbz
2021-01-16 Tobias Platenmove microwatt_mmu bool variable to pspec
2021-01-16 Tobias Platenadd new unittest: test_issuer_mmu_data_path.py
2021-01-15 Tobias Platencleanup test_non_production_core.py
2021-01-15 Tobias Platenadd microwatt_mmu boolean variable to core and compunits
2021-01-15 Tobias Platentest_non_production_core.py: fix hanging test
2021-01-15 Tobias Platentest_non_production_core.py: wire instruction decoder...
2021-01-14 Tobias Platenadd test case for mmu+NonProductionCore
2021-01-10 Tobias Platenadd microwatt mmu config option to compunits.py
2021-01-08 Tobias Platenfix broken testcase for simple core
2021-01-07 Tobias Platenset initial_sprs, cleanup mfspr testprog
2021-01-07 Tobias Platenmfspr is RT, SPR
2021-01-06 Tobias Platenfirst testcase for mmu: case_mfspr_after_invalid_load
2021-01-06 Tobias Platenfu/mmu/fsm.py: mfspr!=mtspr
2021-01-04 Tobias Platentest_countzero.py: rename output files
2021-01-01 Cesar StraussAdd zero CR test case and fix comments
2021-01-01 Cesar StraussAdd test cases with rc=1
2021-01-01 Cesar StraussMake all ports the same size, on the test ALU
2021-01-01 Cesar StraussAdd CR output port to test cases
2021-01-01 Cesar StraussAdd CR to the output data port
2021-01-01 Cesar StraussMake output write enables independent of valid_o
2021-01-01 Cesar StraussMove NOP test case earlier
2021-01-01 Cesar StraussDisable data value output on NOP
2021-01-01 Cesar StraussAdd condition register (CR) output
2020-12-31 Cesar StraussImplement and test NOP in the test ALU
2020-12-31 Cesar StraussDon't use OP_NOP for zero-delay subtraction
2020-12-31 Cesar StraussTest first input port being masked out
2020-12-31 Cesar StraussSign extend the second input port
2020-12-31 Cesar StraussTest masked-out second input port
2020-12-31 Cesar StraussAdd sign extend to the Test ALU
2020-12-31 Cesar StraussShow rdmaskn and wrmask in GTKWave
2020-12-31 Cesar StraussUse the increment operator
2020-12-31 Cesar StraussAdd support for masked write operations
2020-12-31 Cesar StraussClarify reason for holding rdmaskn valid during the...
2020-12-31 Cesar StraussRemove previous version of the CompUnit parallel unit...
2020-12-31 Cesar StraussOnly hold the decoder signals for one cycle, along...
2020-12-30 Cesar StraussTest the rdmaskn control signal
2020-12-29 Cesar StraussRemove left-over comments.
2020-12-28 Luke Kenneth Casso... add CR1 to power_enums
2020-12-20 Cesar StraussAdd support for CXXSim simulation
2020-12-13 Cesar StraussIgnore formal verification output in the source directory
2020-12-13 Cesar StraussAllow more test cases to be run with CXXSim
2020-12-12 Luke Kenneth Casso... skip madd, not implemented
2020-12-07 Cesar StraussDisplay the instruction type as a vector on cxxsim
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