revert bug in icache wishbone ack
[soc.git] / src /
2020-10-01 Luke Kenneth Casso... revert bug in icache wishbone ack
2020-10-01 Luke Kenneth Casso... add clksel, pll to ls180
2020-10-01 Luke Kenneth Casso... create dummy PLL block, connect up to core and clock...
2020-10-01 Cesar StraussAdd GTKWave document to test_compunit_fsm
2020-09-30 Luke Kenneth Casso... add I2C into ls180
2020-09-30 Luke Kenneth Casso... add ASIC version of I2C Master
2020-09-30 Luke Kenneth Casso... clean up row store and wb adr in icache
2020-09-30 Luke Kenneth Casso... hmm only set wishbone address if ack is actually received
2020-09-30 Luke Kenneth Casso... add more debug prints in icache
2020-09-30 Luke Kenneth Casso... remove more reviewed comments
2020-09-30 Luke Kenneth Casso... remove reviewed comments
2020-09-30 Luke Kenneth Casso... comb on wr_index not sync
2020-09-30 Luke Kenneth Casso... start removing reviewed comments
2020-09-30 Luke Kenneth Casso... use same constant name (confusing otherwise)
2020-09-30 Luke Kenneth Casso... need asserts
2020-09-30 Luke Kenneth Casso... halve the number of icache lines for now
2020-09-30 Luke Kenneth Casso... use Repl rather than for-loop to copy bit
2020-09-30 Luke Kenneth Casso... move loop invariant test out of loop
2020-09-30 Luke Kenneth Casso... reduce size of ilang file by a factor of FIVE
2020-09-30 Luke Kenneth Casso... store tag in temp signal
2020-09-30 Luke Kenneth Casso... reduce gate usage by getting cache row only not entire...
2020-09-30 Luke Kenneth Casso... fix read_tag to use word_select correctly
2020-09-30 Luke Kenneth Casso... forgot to add PLRUs as submodules
2020-09-29 Cole Poiriericache.py fix combinatorial loop with by testing temp...
2020-09-29 Cole Poiriericache.py fix is_last_row_addr, get_next_row_addr
2020-09-29 Cole Poiriericache.py trying to sort out test failure, added r...
2020-09-29 Cole Poiriericache.py fix test stbs_done signal, not stbs_zero...
2020-09-29 Cole Poiriericache.py fix rarange
2020-09-29 Cole Poiriericache.py fixed numerous bugs as specified by lkcl...
2020-09-28 Cole Poiriericache.py use d_out as input to assignment instead...
2020-09-28 Luke Kenneth Casso... reduce not-connected IO pins
2020-09-28 Luke Kenneth Casso... missing pspec
2020-09-28 Luke Kenneth Casso... connect SDRAM dqm to wrdata_mask
2020-09-28 Luke Kenneth Casso... lots of sorting out iopads
2020-09-28 Luke Kenneth Casso... add "nocore" option to build verilog
2020-09-28 Luke Kenneth Casso... switch off internal gpio (testing)
2020-09-28 Luke Kenneth Casso... rewrite ilang file after litex ls180 build
2020-09-28 Luke Kenneth Casso... had to over-ride the wishbone functions on C4M TAP
2020-09-27 Cole Poiriericache.py fix translation mistake
2020-09-27 Cesar StraussConvert yet another few tests to be able to use latest...
2020-09-27 Luke Kenneth Casso... add Makefile for creating ls180.il
2020-09-27 Luke Kenneth Casso... rename sys_clk_i to clk_24_i
2020-09-27 Luke Kenneth Casso... add clock selection mechanism
2020-09-26 Luke Kenneth Casso... DMI-to-JTAG needed to be "sync" to get ack/resp right
2020-09-26 Luke Kenneth Casso... do not use simdec2 in test_pipe_caller
2020-09-26 Luke Kenneth Casso... fix annoying alu test_pipe_caller bug, missing asmcode
2020-09-26 Luke Kenneth Casso... add alternative PowerDecode2 to branch test_pipe_caller
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-09-26 Luke Kenneth Casso... try svf test of DMI MSR
2020-09-26 Luke Kenneth Casso... make check of LDSTMode.update conditional in PowerDecoder2
2020-09-26 Luke Kenneth Casso... add ls180io.py
2020-09-26 Luke Kenneth Casso... add openocd script to fire off svf test
2020-09-26 Luke Kenneth Casso... get openocd svf test running, replicating jtag test
2020-09-26 Luke Kenneth Casso... put test into "server" mode for connecting with openocd
2020-09-26 Luke Kenneth Casso... create client-server version of jtag debug unit test
2020-09-26 Luke Kenneth Casso... create client-server version of jtag debug unit test
2020-09-26 Luke Kenneth Casso... class-ify jtagremote
2020-09-26 Luke Kenneth Casso... send/receive jtagremote protocol
2020-09-26 Luke Kenneth Casso... basic client/server socket example
2020-09-26 Luke Kenneth Casso... add openocd configs
2020-09-26 Luke Kenneth Casso... reduce sdram pins to smaller address and only 1 cs_n
2020-09-26 Luke Kenneth Casso... only enable pads connections for ls180 for now
2020-09-25 Cole Poiriericache.py fix several subtle bugs that were lines that...
2020-09-25 Cole Poirierwb_types.py add reset value of 0b11111111 for WBSelType...
2020-09-24 Cesar StraussUse nmutil simulator module to simplify choosing among...
2020-09-24 Luke Kenneth Casso... do not have to use uart_litex gpio_litex names
2020-09-24 Luke Kenneth Casso... add comments
2020-09-24 Luke Kenneth Casso... enable GPIO pads through C4M JTAG
2020-09-24 Luke Kenneth Casso... c4m iopad integration working
2020-09-24 Cole Poiriericache.py add some missing lines from icache.vhdl,...
2020-09-24 Cole Poiriermem_types.py wb_types.py add name constructor to all...
2020-09-24 Cole Poiriericache.py fixed all errors that raised python exception...
2020-09-24 Cesar StraussFix whitespace, remove unused imports
2020-09-24 Luke Kenneth Casso... brackets round imports looks cleaner?
2020-09-24 Luke Kenneth Casso... add jtag c4m pins which gives us a way to connect IO...
2020-09-24 Cesar StraussUse nmutil simulator module to simplify choosing among...
2020-09-23 Luke Kenneth Casso... cs_n and cke in sdram need to match in length
2020-09-23 Luke Kenneth Casso... change litex sdram pinouts to ASIC type
2020-09-23 Luke Kenneth Casso... redo litex SDCard to send out data/cmd o/i/en pins
2020-09-23 Luke Kenneth Casso... sort out GPIO with i/o/oe in ls180
2020-09-23 Luke Kenneth Casso... add ls180 pinmap text file
2020-09-23 Luke Kenneth Casso... attempt GPIO bi-directional
2020-09-23 Luke Kenneth Casso... add I2C master to ls180
2020-09-22 Luke Kenneth Casso... add 2 PWMs (quick, easy to do)
2020-09-22 Luke Kenneth Casso... move dmi_sim to separate module
2020-09-22 Jacob LifshayRevert "disable pia in div tests"
2020-09-22 Luke Kenneth Casso... add openocd.cfg experiment
2020-09-22 Luke Kenneth Casso... create a JTAG platform and connect it up. jtagremote...
2020-09-22 Luke Kenneth Casso... add jtagremote to litex sim, add new "variant" to core...
2020-09-22 Luke Kenneth Casso... link litex ls180soc JTAG pads
2020-09-22 Luke Kenneth Casso... add jtag wishbone and jtag ports to libresoc litex...
2020-09-22 Luke Kenneth Casso... add jtag interface to issuer_verilog
2020-09-22 Luke Kenneth Casso... add sys_rst to Clock Reset Generator
2020-09-22 Luke Kenneth Casso... add JTAG IOpads and rename rst to sys_rst
2020-09-22 Luke Kenneth Casso... add similar platforms to ls180.py
2020-09-22 Luke Kenneth Casso... add JTAG bus module
2020-09-22 Luke Kenneth Casso... split out dmi2jtag into own unit test
2020-09-22 Cesar StraussPort soc.experiment.alu_fsm to the new way of invoking...
2020-09-22 Luke Kenneth Casso... disable pia in div tests
2020-09-22 Luke Kenneth Casso... add MMU (commented out)
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