soc.git
26 min agoupdate test_caller_radix.py master
Tobias Platen [Thu, 4 Mar 2021 19:16:50 +0000 (20:16 +0100)]
update test_caller_radix.py

37 min agoISACaller: add option mmu
Tobias Platen [Thu, 4 Mar 2021 19:05:44 +0000 (20:05 +0100)]
ISACaller: add option mmu

87 min agowhoops microwatt already allocates SPR 720
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 18:15:40 +0000 (18:15 +0000)]
whoops microwatt already allocates SPR 720

96 min agoadd comments from gem5-experimental mmu
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 18:06:57 +0000 (18:06 +0000)]
add comments from gem5-experimental mmu

115 min agoadd cached pgtbl0/3
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 17:47:21 +0000 (17:47 +0000)]
add cached pgtbl0/3

2 hours agoadd two functions for checking permissions, to be based on microwatt
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 17:39:53 +0000 (17:39 +0000)]
add two functions for checking permissions, to be based on microwatt

25 hours agoadd RADIX skeleton and unit test
Tobias Platen [Wed, 3 Mar 2021 18:23:01 +0000 (19:23 +0100)]
add RADIX skeleton and unit test

25 hours agoadd debug strings
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 17:45:55 +0000 (17:45 +0000)]
add debug strings

26 hours agoremove singleton pattern
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 17:07:00 +0000 (17:07 +0000)]
remove singleton pattern

27 hours agoadd pywriter Makefile entry
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 16:13:43 +0000 (16:13 +0000)]
add pywriter Makefile entry

29 hours agocur_state is a global, does not have to be passed as a parameter in TestIssuer
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 14:28:53 +0000 (14:28 +0000)]
cur_state is a global, does not have to be passed as a parameter in TestIssuer

29 hours agoset SVSTATE in TestRunner using new TestIssuer.svstate_i
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 14:18:46 +0000 (14:18 +0000)]
set SVSTATE in TestRunner using new TestIssuer.svstate_i

29 hours agoadd svstate_i to TestIssuer which mirrors pc_i
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 14:15:18 +0000 (14:15 +0000)]
add svstate_i to TestIssuer which mirrors pc_i

2 days agocomment out changing SPR 720 because 720 is not supported by the MMU pipe
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 16:32:20 +0000 (16:32 +0000)]
comment out changing SPR 720 because 720 is not supported by the MMU pipe

2 days agosort out SPR setting in MMU
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 16:24:50 +0000 (16:24 +0000)]
sort out SPR setting in MMU

2 days agooperating correctly, not directing MMU SPRs to SPR Pipeline,
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 13:55:17 +0000 (13:55 +0000)]
operating correctly, not directing MMU SPRs to SPR Pipeline,
failure with PC likely due to ISACaller not supporting SPR 720

2 days agomust always set ok for writing out data otherwise it never hits regfile
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 12:49:18 +0000 (12:49 +0000)]
must always set ok for writing out data otherwise it never hits regfile
(and causes compunit to fail)

3 days agoRevert "fix Bug 607 - unnecessary code added related to MMU in PowerDecoder2"
Luke Kenneth Casson Leighton [Mon, 1 Mar 2021 19:35:31 +0000 (19:35 +0000)]
Revert "fix Bug 607 - unnecessary code added related to MMU in PowerDecoder2"

This reverts commit 0b31706069567c4124ebac487f238342cc540d79.

3 days agomove SVP64 RM decoder to separate module
Luke Kenneth Casson Leighton [Mon, 1 Mar 2021 15:40:31 +0000 (15:40 +0000)]
move SVP64 RM decoder to separate module

4 days agoadd additional SVP64 RM decode fields
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 18:36:22 +0000 (18:36 +0000)]
add additional SVP64 RM decode fields

4 days agostart on SVP64 RM Mode decoder
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 17:19:18 +0000 (17:19 +0000)]
start on SVP64 RM Mode decoder

4 days agomore SVP64 enums
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 16:29:54 +0000 (16:29 +0000)]
more SVP64 enums

4 days agoadd SVP64 RM sub-field enums
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 16:21:42 +0000 (16:21 +0000)]
add SVP64 RM sub-field enums

4 days agomove SVP64 Extra decoders to separate module
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:47:25 +0000 (14:47 +0000)]
move SVP64 Extra decoders to separate module

4 days agofix syntax error
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:43:09 +0000 (14:43 +0000)]
fix syntax error

4 days agomove SVP64PrefixDecoder to separate module
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:42:35 +0000 (14:42 +0000)]
move SVP64PrefixDecoder to separate module

4 days agoadd PowerDecoder.no_in_vec
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:42:12 +0000 (14:42 +0000)]
add PowerDecoder.no_in_vec

4 days agoadd svp64_instrs to power_svp64
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 12:19:52 +0000 (12:19 +0000)]
add svp64_instrs to power_svp64

4 days agofix Bug 607 - unnecessary code added related to MMU in PowerDecoder2
Tobias Platen [Sun, 28 Feb 2021 11:25:51 +0000 (12:25 +0100)]
fix Bug 607 - unnecessary code added related to MMU in PowerDecoder2

4 days agofix Bug 603 - use SPR names/numbers from sprs.csv
Tobias Platen [Sun, 28 Feb 2021 11:14:31 +0000 (12:14 +0100)]
fix Bug 603 - use SPR names/numbers from sprs.csv

5 days agouse PowerDecoder2.no_out_vec instead of manual vector detection in ISACaller
Luke Kenneth Casson Leighton [Sat, 27 Feb 2021 12:43:35 +0000 (12:43 +0000)]
use PowerDecoder2.no_out_vec instead of manual vector detection in ISACaller

5 days agoadd corresponding VL=0 unit test as from 161b7d67b in svp64_cases.py
Luke Kenneth Casson Leighton [Sat, 27 Feb 2021 12:38:15 +0000 (12:38 +0000)]
add corresponding VL=0 unit test as from 161b7d67b in svp64_cases.py

5 days agoAdd traces for the new FSM
Cesar Strauss [Sat, 27 Feb 2021 09:25:47 +0000 (06:25 -0300)]
Add traces for the new FSM

5 days agoAdd a vector case with VL == 0
Cesar Strauss [Fri, 26 Feb 2021 21:45:18 +0000 (18:45 -0300)]
Add a vector case with VL == 0

This will be useful for testing the fetch <-> issue loop.

6 days agocomment on CoreState
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:50:04 +0000 (13:50 +0000)]
comment on CoreState

6 days agoremove sv_changed input to fetch_fsm, add it to issue_fsm TestIssuer
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:46:22 +0000 (13:46 +0000)]
remove sv_changed input to fetch_fsm, add it to issue_fsm TestIssuer

6 days agomoving new_svstate and update_svstate into issue FSM TestIssuer
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:40:22 +0000 (13:40 +0000)]
moving new_svstate and update_svstate into issue FSM TestIssuer

6 days agomove fetch_insn_o into issue_fsm TestIssuer
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:34:59 +0000 (13:34 +0000)]
move fetch_insn_o into issue_fsm TestIssuer

6 days agoadd comments, missing that VL loop ends after execution if no_out_vec set
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:21:31 +0000 (13:21 +0000)]
add comments, missing that VL loop ends after execution if no_out_vec set
SVP64 TestIssuer

6 days agoImplement a decode/issue FSM between fetch and execute
Cesar Strauss [Fri, 26 Feb 2021 10:47:03 +0000 (07:47 -0300)]
Implement a decode/issue FSM between fetch and execute

The idea is for it to:
* keep looping "fetch" while VL==0 on a vector instruction.
* keep looping "execute" while SRCSTEP != VL-1.
* unless PC/SVSTATE was modified by "execute", in that case do go back
to "fetch".
* update PC and SRCSTEP accordingly.

8 days agowb_get: write outputs to seperate logfile too
Tobias Platen [Wed, 24 Feb 2021 18:43:23 +0000 (19:43 +0100)]
wb_get: write outputs to seperate logfile too

8 days agoupdate mmu testcase
Tobias Platen [Wed, 24 Feb 2021 18:40:53 +0000 (19:40 +0100)]
update mmu testcase

8 days agotest_runner.py: add needed imports
Tobias Platen [Wed, 24 Feb 2021 18:39:59 +0000 (19:39 +0100)]
test_runner.py: add needed imports

8 days agoadd comments explaining split
Luke Kenneth Casson Leighton [Wed, 24 Feb 2021 15:22:20 +0000 (15:22 +0000)]
add comments explaining split
https://bugs.libre-soc.org/show_bug.cgi?id=606

8 days agomove DecodeCROut/In (at last) out of PowerDecoderSubset and into PowerDecoder2
Luke Kenneth Casson Leighton [Wed, 24 Feb 2021 15:19:16 +0000 (15:19 +0000)]
move DecodeCROut/In (at last) out of PowerDecoderSubset and into PowerDecoder2
https://bugs.libre-soc.org/show_bug.cgi?id=606

8 days agostart making write_cr0 independent of DecodeCROut
Luke Kenneth Casson Leighton [Wed, 24 Feb 2021 15:08:32 +0000 (15:08 +0000)]
start making write_cr0 independent of DecodeCROut
https://bugs.libre-soc.org/show_bug.cgi?id=606

9 days agodeduplicate
Tobias Platen [Tue, 23 Feb 2021 18:20:15 +0000 (19:20 +0100)]
deduplicate

9 days agoadd note that SVSTATE has changed, this will allow picking up that
Luke Kenneth Casson Leighton [Tue, 23 Feb 2021 13:43:35 +0000 (13:43 +0000)]
add note that SVSTATE has changed, this will allow picking up that
Trap pipeline has altered SVSTATE

9 days agoFix typo when calculating PowerDecoder2.no_out_vec
Cesar Strauss [Mon, 22 Feb 2021 21:29:11 +0000 (18:29 -0300)]
Fix typo when calculating PowerDecoder2.no_out_vec

10 days agomove setting of NIA into fetch FSM in TestIssuer
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 16:21:26 +0000 (16:21 +0000)]
move setting of NIA into fetch FSM in TestIssuer

10 days agowhoops
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 16:00:24 +0000 (16:00 +0000)]
whoops

10 days agomoving PC-setting (NIA) out of execute_fsm in TestIssuer
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 15:59:33 +0000 (15:59 +0000)]
moving PC-setting (NIA) out of execute_fsm in TestIssuer

10 days agorename inter-FSM handshake signals in TestIssuer
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 14:48:46 +0000 (14:48 +0000)]
rename inter-FSM handshake signals in TestIssuer

11 days agoerr trying to put in some FSM handshake signals, getting confused
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 19:27:06 +0000 (19:27 +0000)]
err trying to put in some FSM handshake signals, getting confused

11 days agocomment for where SVSTATE FSM should go
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 19:20:38 +0000 (19:20 +0000)]
comment for where SVSTATE FSM should go

11 days agoadd CR out vector detection to PowerDecoder2 no_out_vec
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 19:20:17 +0000 (19:20 +0000)]
add CR out vector detection to PowerDecoder2 no_out_vec

11 days agoThe field selection function was moved to nmutil.util
Cesar Strauss [Sun, 21 Feb 2021 17:21:54 +0000 (14:21 -0300)]
The field selection function was moved to nmutil.util

All previous users were updated.

11 days agoHide the register augmentation traces by default
Cesar Strauss [Sun, 21 Feb 2021 17:18:15 +0000 (14:18 -0300)]
Hide the register augmentation traces by default

This saves some vertical space if you are not interested in seeing this
level of detail, but it is still there if you need it.
Needs the latest nmutil version for it to work.

11 days agomove execute_fsm to separate function in TestIssuer
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 15:50:31 +0000 (15:50 +0000)]
move execute_fsm to separate function in TestIssuer

11 days agomove fetch_fsm to separate function in TestIssuer
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 15:41:08 +0000 (15:41 +0000)]
move fetch_fsm to separate function in TestIssuer

11 days agoadd JTAG enable/disable of 4k SRAMs
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 15:22:28 +0000 (15:22 +0000)]
add JTAG enable/disable of 4k SRAMs

11 days agoThe new version of "sel" is smart enough to find a suitable Signal name
Cesar Strauss [Sun, 21 Feb 2021 14:50:21 +0000 (11:50 -0300)]
The new version of "sel" is smart enough to find a suitable Signal name

An up-to-date version of nmutil is required for this.

11 days agoadd comments for Mode field in SVP64Asm
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 13:08:32 +0000 (13:08 +0000)]
add comments for Mode field in SVP64Asm

11 days agocomments in SVP64RMFields
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 12:58:19 +0000 (12:58 +0000)]
comments in SVP64RMFields

11 days agoUse the new selection field function from nmutil
Cesar Strauss [Sun, 21 Feb 2021 12:54:20 +0000 (09:54 -0300)]
Use the new selection field function from nmutil

Note that the new function accepts a Module on which it to generate its
wires, and returns a Signal of the appropriate size.

Be sure to update nmutil to get the new function.

11 days agoUse symbolic values as field sizes
Cesar Strauss [Sun, 21 Feb 2021 09:58:54 +0000 (06:58 -0300)]
Use symbolic values as field sizes

11 days agoReplace all hardcoded shifts into RM by usage of SVP64RMFields
Cesar Strauss [Sat, 20 Feb 2021 23:00:02 +0000 (20:00 -0300)]
Replace all hardcoded shifts into RM by usage of SVP64RMFields

11 days agocreate SVP64CROffs consts for when SVP64 Vector-of-CRs is active (Rc=1)
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 01:04:50 +0000 (01:04 +0000)]
create SVP64CROffs consts for when SVP64 Vector-of-CRs is active (Rc=1)

11 days agocomments on sv.add. Rc=1 unit test
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 23:38:17 +0000 (23:38 +0000)]
comments on sv.add. Rc=1 unit test

11 days agoadd in Vectorised CRs when Rc=1 into ISACaller
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 23:32:50 +0000 (23:32 +0000)]
add in Vectorised CRs when Rc=1 into ISACaller

11 days agoadd CR1 to DecodeCRIn/Out
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 23:15:06 +0000 (23:15 +0000)]
add CR1 to DecodeCRIn/Out

11 days agoadd some debug checking to get_pdecode_cr_out
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 22:13:20 +0000 (22:13 +0000)]
add some debug checking to get_pdecode_cr_out

11 days agoadd crossreference to bug #603
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 21:55:57 +0000 (21:55 +0000)]
add crossreference to bug #603

11 days agoadd more debug output to get_pdecode_cr_out
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 21:44:48 +0000 (21:44 +0000)]
add more debug output to get_pdecode_cr_out

11 days agoActually forward the field width to field_slice()
Cesar Strauss [Sat, 20 Feb 2021 21:12:03 +0000 (18:12 -0300)]
Actually forward the field width to field_slice()

This means that field extraction of multi-bit subfields, for field sizes
other than 64 bits, was buggy up to now.

Fortunately, there were no users of non-default field sizes so far.

11 days agoAssemble the SV64 prefix from its subfields using SVP64PrefixFields
Cesar Strauss [Sat, 20 Feb 2021 20:09:42 +0000 (17:09 -0300)]
Assemble the SV64 prefix from its subfields using SVP64PrefixFields

11 days agostart on CRs in SVP64 mode
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 20:49:26 +0000 (20:49 +0000)]
start on CRs in SVP64 mode

11 days agofix SVP64Asm Rc=1 assembly
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 20:49:00 +0000 (20:49 +0000)]
fix SVP64Asm Rc=1 assembly

11 days agoadd black-box attribute to 4k SRAM cell
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 20:47:48 +0000 (20:47 +0000)]
add black-box attribute to 4k SRAM cell

12 days agoFix more MSB0 issues in comments
Cesar Strauss [Sat, 20 Feb 2021 18:39:41 +0000 (15:39 -0300)]
Fix more MSB0 issues in comments

12 days agoReplace more hardcoded constants with symbolic field numbers
Cesar Strauss [Sat, 20 Feb 2021 18:31:55 +0000 (15:31 -0300)]
Replace more hardcoded constants with symbolic field numbers

12 days agoincrement CRs based on srcstep, see what happens
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 16:40:41 +0000 (16:40 +0000)]
increment CRs based on srcstep, see what happens

12 days agoadd litex wishbone interconnect to 4x 4k SRAMs
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 15:22:18 +0000 (15:22 +0000)]
add litex wishbone interconnect to 4x 4k SRAMs
also had to add one more of the massive DFF 512 byte SRAMs in order to cover
all the exception areas (0x900) without going into 4k SRAM area,
which litex demands to be on an aligned boundary

12 days agoadd QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer if enabled
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 14:58:58 +0000 (14:58 +0000)]
add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer if enabled

12 days agoadd option for QTY 4x 4k SRAM blocks (not added yet) to issuer_verilog
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 14:39:14 +0000 (14:39 +0000)]
add option for QTY 4x 4k SRAM blocks (not added yet) to issuer_verilog

12 days agoadd Wishbone-wrapped SPBlock_512W64B8W
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 14:30:07 +0000 (14:30 +0000)]
add Wishbone-wrapped SPBlock_512W64B8W

12 days agowhoops set ROM to none by mistake
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 13:55:47 +0000 (13:55 +0000)]
whoops set ROM to none by mistake

12 days agowhoops spelling error
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 12:26:32 +0000 (12:26 +0000)]
whoops spelling error

12 days agoadd (unused) code for writing out SVSTATE in TestIssuer
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 12:23:04 +0000 (12:23 +0000)]
add (unused) code for writing out SVSTATE in TestIssuer

12 days agocorrect arguments, set microwatt_mmu=True, pass in ROM correctly
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 12:12:14 +0000 (12:12 +0000)]
correct arguments, set microwatt_mmu=True, pass in ROM correctly

12 days agominor whitespace cleanup
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 12:10:11 +0000 (12:10 +0000)]
minor whitespace cleanup

12 days agoremove massive code-duplication, move simple "self.rom" to test_runner.py
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 12:03:35 +0000 (12:03 +0000)]
remove massive code-duplication, move simple "self.rom" to test_runner.py
the fu rom mmu unit test does seem to still work

12 days agommu testcase: set MMU SPRs
Tobias Platen [Sat, 20 Feb 2021 11:53:41 +0000 (12:53 +0100)]
mmu testcase: set MMU SPRs

12 days agoadd rom debugger
Tobias Platen [Sat, 20 Feb 2021 10:37:20 +0000 (11:37 +0100)]
add rom debugger

12 days agoadd mmu rom testcase
Tobias Platen [Sat, 20 Feb 2021 09:20:10 +0000 (10:20 +0100)]
add mmu rom testcase

13 days agommu: remove TestMemory
Tobias Platen [Thu, 18 Feb 2021 19:45:48 +0000 (20:45 +0100)]
mmu: remove TestMemory

2 weeks agodeclare blank classes SPEC and EXTRA2 to add MSB-to-LSB conversion
Luke Kenneth Casson Leighton [Wed, 17 Feb 2021 23:06:00 +0000 (23:06 +0000)]
declare blank classes SPEC and EXTRA2 to add MSB-to-LSB conversion

2 weeks agoUse subfield bit selection to extract the RM SVP64 subfield
Cesar Strauss [Wed, 17 Feb 2021 22:53:01 +0000 (19:53 -0300)]
Use subfield bit selection to extract the RM SVP64 subfield

2 weeks agoReplace MSB-i by symbolic subfield indices and selectors
Cesar Strauss [Wed, 17 Feb 2021 22:30:29 +0000 (19:30 -0300)]
Replace MSB-i by symbolic subfield indices and selectors

2 weeks agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Wed, 17 Feb 2021 17:30:54 +0000 (18:30 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc