soc.git
2 days agomove unused directory out of src, to indicate "ignore completely" master
Luke Kenneth Casson Leighton [Sun, 1 Aug 2021 17:46:55 +0000 (18:46 +0100)]
move unused directory out of src, to indicate "ignore completely"

2 days agoimport setup_i_memory from soc.simple.test.test_runner
Jonathan Neuschäfer [Sat, 31 Jul 2021 22:25:34 +0000 (00:25 +0200)]
import setup_i_memory from soc.simple.test.test_runner

This function was moved in commit 8482a3ed
("split out TestRunner into separate module").

2 days agosoc.simple.test: Rename setup_test_memory to avoid nosetest calling it
Jonathan Neuschäfer [Sun, 1 Aug 2021 17:08:50 +0000 (19:08 +0200)]
soc.simple.test: Rename setup_test_memory to avoid nosetest calling it

2 days agoRename test_dcache, which can't be invoked by test runners
Jonathan Neuschäfer [Sat, 31 Jul 2021 22:43:26 +0000 (00:43 +0200)]
Rename test_dcache, which can't be invoked by test runners

Functions named *test_* are invoked by test runners, such as nosetests,
but test_dcache was not written with this behavior in mind. Rename it to
avoid invocation.

Maybe the main block at the end of a file should now be converted into a
test that *is* invoked by test runners.

2 days agosimulator/test_sim.py should not have been added
Luke Kenneth Casson Leighton [Sun, 1 Aug 2021 17:39:27 +0000 (18:39 +0100)]
simulator/test_sim.py should not have been added

3 days agopartial fix for src/soc/experiment/compldst_multi.py
Tobias Platen [Sat, 31 Jul 2021 16:49:45 +0000 (18:49 +0200)]
partial fix for src/soc/experiment/compldst_multi.py

4 days agopartially fix unit test in compldst_multi.py
Tobias Platen [Fri, 30 Jul 2021 18:59:24 +0000 (20:59 +0200)]
partially fix unit test in compldst_multi.py

8 days agocompldst_multi: add debug output for dcbz
Tobias Platen [Mon, 26 Jul 2021 18:42:21 +0000 (20:42 +0200)]
compldst_multi: add debug output for dcbz

10 days agoadd test_issuer_dcache.py
Tobias Platen [Sat, 24 Jul 2021 11:25:49 +0000 (13:25 +0200)]
add test_issuer_dcache.py

11 days agoldst: cleanup debug outputs
Tobias Platen [Fri, 23 Jul 2021 18:49:52 +0000 (20:49 +0200)]
ldst: cleanup debug outputs

11 days agotest_dcbz_pi.py: dcbz now working
Tobias Platen [Fri, 23 Jul 2021 18:48:37 +0000 (20:48 +0200)]
test_dcbz_pi.py: dcbz now working

13 days agorevert accidential delete in test_pi2ls.py causing tests to break
Tobias Platen [Wed, 21 Jul 2021 19:04:24 +0000 (21:04 +0200)]
revert accidential delete in test_pi2ls.py causing tests to break

13 days agotest_dcbz_pi.py: do not use problem state
Tobias Platen [Wed, 21 Jul 2021 18:02:48 +0000 (20:02 +0200)]
test_dcbz_pi.py: do not use problem state

13 days agoupdate pi_dcbz function
Tobias Platen [Wed, 21 Jul 2021 17:57:55 +0000 (19:57 +0200)]
update pi_dcbz function

2 weeks agosrc/soc/config/test/test_pi2ls.py: add more debug outputs
Tobias Platen [Mon, 19 Jul 2021 19:01:38 +0000 (21:01 +0200)]
src/soc/config/test/test_pi2ls.py: add more debug outputs

2 weeks agotest_dcbz_pi.py: more work on unit test
Tobias Platen [Mon, 19 Jul 2021 18:38:05 +0000 (20:38 +0200)]
test_dcbz_pi.py: more work on unit test

2 weeks agoupdate TestRunner, SVSTATE is now a class that inherits from SelectableInt
Luke Kenneth Casson Leighton [Thu, 15 Jul 2021 12:51:49 +0000 (13:51 +0100)]
update TestRunner, SVSTATE is now a class that inherits from SelectableInt
rather than *contains* a SelectableInt

2 weeks agoupdate SVSTATE to 64 bit length (fortunately very easy)
Luke Kenneth Casson Leighton [Wed, 14 Jul 2021 19:07:02 +0000 (20:07 +0100)]
update SVSTATE to 64 bit length (fortunately very easy)

2 weeks agoadd more debug outputs, pass dcbz to loadstore/dcache
Tobias Platen [Wed, 14 Jul 2021 18:38:11 +0000 (20:38 +0200)]
add more debug outputs, pass dcbz to loadstore/dcache

2 weeks agodcache: improve debug output
Tobias Platen [Wed, 14 Jul 2021 18:28:31 +0000 (20:28 +0200)]
dcache: improve debug output

3 weeks agouse standard create_pdecode in TestRunner
Luke Kenneth Casson Leighton [Sat, 26 Jun 2021 12:38:03 +0000 (13:38 +0100)]
use standard create_pdecode in TestRunner

3 weeks agouse default decoder, do not pass one in.
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 21:11:07 +0000 (22:11 +0100)]
use default decoder, do not pass one in.
inside PowerDecoder2, create default decoder with new "conditions"

3 weeks agomore work on test_dcbz_pi.py
Tobias Platen [Sun, 11 Jul 2021 16:57:10 +0000 (18:57 +0200)]
more work on test_dcbz_pi.py

3 weeks agopass self.pi.is_dcbz to request
Tobias Platen [Sun, 11 Jul 2021 16:18:13 +0000 (18:18 +0200)]
pass self.pi.is_dcbz to request

3 weeks agoimplement pi_dcbz
Tobias Platen [Sun, 11 Jul 2021 15:50:25 +0000 (17:50 +0200)]
implement pi_dcbz

3 weeks agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Sun, 11 Jul 2021 15:38:04 +0000 (17:38 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

3 weeks agoadd test_dcbz_pi.py (skeleton only)
Tobias Platen [Sun, 11 Jul 2021 15:37:22 +0000 (17:37 +0200)]
add test_dcbz_pi.py (skeleton only)

3 weeks agoShow some usage of PortInterface in action
Cesar Strauss [Sat, 10 Jul 2021 21:53:22 +0000 (18:53 -0300)]
Show some usage of PortInterface in action

3 weeks agoAdd new traces to the GTKWave document
Cesar Strauss [Sat, 10 Jul 2021 17:25:16 +0000 (14:25 -0300)]
Add new traces to the GTKWave document

The new traces are related to the state latches, operand fetch and ALU
address generation.

3 weeks agoAdd operand producers to the parallel LDST Compunit test case
Cesar Strauss [Sat, 10 Jul 2021 17:17:17 +0000 (14:17 -0300)]
Add operand producers to the parallel LDST Compunit test case

Code from the parallel ALU Compunit test case was successfully reused.
Result consumers are to be added later.
The simulation now runs through the operand fetch phase and the address
ALU phase.

3 weeks agoDetect unexpected operand fetches and produced results
Cesar Strauss [Sat, 10 Jul 2021 16:47:19 +0000 (13:47 -0300)]
Detect unexpected operand fetches and produced results

When some operands are not used (zero_a and/or imm_ok), raise an error as
soon as rel_o is asserted. Likewise, for results (when not in RA update
mode).

3 weeks agoStart of a GTKWave document for the LDST CompUnit parallel unit test
Cesar Strauss [Wed, 7 Jul 2021 09:36:50 +0000 (06:36 -0300)]
Start of a GTKWave document for the LDST CompUnit parallel unit test

4 weeks agoBeginning of a class to make a parallel test case for LDSTCompUnit
Cesar Strauss [Sun, 4 Jul 2021 21:00:27 +0000 (18:00 -0300)]
Beginning of a class to make a parallel test case for LDSTCompUnit

For now it just issues an operation. Later it will setup producers and
consumers for input/output operands and the port interface.

4 weeks agocut down on time by uncommenting data not needed, adding documentation
Tobias Platen [Wed, 30 Jun 2021 17:41:01 +0000 (19:41 +0200)]
cut down on time by uncommenting data not needed, adding documentation

5 weeks agoupdate ldst test case by adding precise timing
Tobias Platen [Mon, 28 Jun 2021 17:44:36 +0000 (19:44 +0200)]
update ldst test case by adding precise timing

5 weeks agopropagate new use_svp64_ldst_dec mode through TestCore and TestIssuer
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 14:52:25 +0000 (15:52 +0100)]
propagate new use_svp64_ldst_dec mode through TestCore and TestIssuer

5 weeks agoadd an explicit PowerDecoder.is_svp64_mode flag to help with detection
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 12:26:19 +0000 (13:26 +0100)]
add an explicit PowerDecoder.is_svp64_mode flag to help with detection

6 weeks agodcache: add debug output
Tobias Platen [Sun, 20 Jun 2021 17:31:34 +0000 (19:31 +0200)]
dcache: add debug output

6 weeks agoupdate test_ldst_pi.py
Tobias Platen [Sun, 20 Jun 2021 16:00:22 +0000 (18:00 +0200)]
update test_ldst_pi.py

6 weeks agouncomment test_dcache_random
Tobias Platen [Fri, 18 Jun 2021 18:09:54 +0000 (20:09 +0200)]
uncomment test_dcache_random

6 weeks agosrc/soc/fu/ldst/loadstore.py: keep data for the whole cycle
Tobias Platen [Fri, 18 Jun 2021 17:40:05 +0000 (19:40 +0200)]
src/soc/fu/ldst/loadstore.py: keep data for the whole cycle

7 weeks agoupdate testcase for ldst
Tobias Platen [Mon, 14 Jun 2021 18:02:49 +0000 (20:02 +0200)]
update testcase for ldst

7 weeks agowhoops Popcount datalen too big (wasted bits). reduce
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 19:10:16 +0000 (20:10 +0100)]
whoops Popcount datalen too big (wasted bits). reduce

7 weeks agogit submodule update
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:51:14 +0000 (16:51 +0100)]
git submodule update

7 weeks agodisconnect pll clock, connected in peripheral interconnect
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:08:25 +0000 (16:08 +0100)]
disconnect pll clock, connected in peripheral interconnect

7 weeks agoadd in/out of ref_clk and pllclk_clk when PLL enabled
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 13:32:26 +0000 (14:32 +0100)]
add in/out of ref_clk and pllclk_clk when PLL enabled

8 weeks agoStart a new self-contained test suite for LDSTCompUnit
Cesar Strauss [Sun, 6 Jun 2021 22:00:46 +0000 (19:00 -0300)]
Start a new self-contained test suite for LDSTCompUnit

The idea is to use parallel processes, like on the new ALU CompUnit tests.
In this case, it will include PortInterface emulation as well.
The current goal is to ensure that exception support is properly
implemented.

2 months agocomment out domains that have already been created
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 15:36:40 +0000 (16:36 +0100)]
comment out domains that have already been created

2 months agono, do not assign clock to clock!
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 14:48:14 +0000 (15:48 +0100)]
no, do not assign clock to clock!

2 months agorename ref to ref_v in PLL due to ref being a verilog keyword
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 14:42:32 +0000 (15:42 +0100)]
rename ref to ref_v in PLL due to ref being a verilog keyword

2 months agosort out PLL domains but bypass PLL due to lack of time
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 14:41:33 +0000 (15:41 +0100)]
sort out PLL domains but bypass PLL due to lack of time

2 months agouse DomainRenamer on all sub-components of TestIssuer
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 12:48:32 +0000 (13:48 +0100)]
use DomainRenamer on all sub-components of TestIssuer
except for JTAG and DMI

2 months agomake core_rst a member of TestIssuerInternal
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 12:02:59 +0000 (13:02 +0100)]
make core_rst a member of TestIssuerInternal

2 months agotest_ldst_pi.py: add new test case
Tobias Platen [Tue, 1 Jun 2021 18:23:37 +0000 (20:23 +0200)]
test_ldst_pi.py: add new test case

2 months agotest_ldst_pi.py: first version of test_dcache_random()
Tobias Platen [Sat, 29 May 2021 18:46:18 +0000 (20:46 +0200)]
test_ldst_pi.py: first version of test_dcache_random()

2 months agotest_ldst_pi.py: more test_dcache_regression()
Tobias Platen [Sat, 29 May 2021 18:10:15 +0000 (20:10 +0200)]
test_ldst_pi.py: more test_dcache_regression()

2 months agoadjust PLL connections looking for coriolis2 issue
Luke Kenneth Casson Leighton [Thu, 27 May 2021 17:21:16 +0000 (18:21 +0100)]
adjust PLL connections looking for coriolis2 issue

2 months agocorrections on spblock ack
Luke Kenneth Casson Leighton [Thu, 27 May 2021 12:04:10 +0000 (13:04 +0100)]
corrections on spblock ack

2 months agoclassic wishbone mode: must not do ack if already acked
Luke Kenneth Casson Leighton [Thu, 27 May 2021 12:01:42 +0000 (13:01 +0100)]
classic wishbone mode: must not do ack if already acked

2 months agoarse. PLL test_issuer clk_sel_i accidentally only 1 bit not 2
Luke Kenneth Casson Leighton [Wed, 26 May 2021 15:10:30 +0000 (16:10 +0100)]
arse. PLL test_issuer clk_sel_i accidentally only 1 bit not 2

2 months agoremove err feature from sram4k wb
Luke Kenneth Casson Leighton [Wed, 26 May 2021 15:09:58 +0000 (16:09 +0100)]
remove err feature from sram4k wb

2 months agoadd ldst PortInterface misalign unit test (underway)
Luke Kenneth Casson Leighton [Wed, 26 May 2021 13:22:45 +0000 (14:22 +0100)]
add ldst PortInterface misalign unit test (underway)

2 months agorename PLL signals
Luke Kenneth Casson Leighton [Tue, 25 May 2021 11:31:31 +0000 (12:31 +0100)]
rename PLL signals

2 months agotest_ldst_pi.py: fix race condition causing early stop
Tobias Platen [Tue, 25 May 2021 19:00:41 +0000 (21:00 +0200)]
test_ldst_pi.py: fix race condition causing early stop

2 months agowait_ldok: add debug output count
Tobias Platen [Tue, 25 May 2021 17:22:46 +0000 (19:22 +0200)]
wait_ldok: add debug output count

2 months agowhoops sort out name of SPBlock RAM
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:21:00 +0000 (18:21 +0100)]
whoops sort out name of SPBlock RAM

2 months agochange name of submodule to real_pll
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:05:10 +0000 (18:05 +0100)]
change name of submodule to real_pll

2 months agomatch up PLL names
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:55:09 +0000 (12:55 +0100)]
match up PLL names

2 months agoRemove redundant build step
Cesar Strauss [Sat, 22 May 2021 21:12:48 +0000 (18:12 -0300)]
Remove redundant build step

The pywriter script has already ran, as part of the openpower-isa install.

2 months agoInclude missing step in automated build
Cesar Strauss [Sat, 22 May 2021 21:10:02 +0000 (18:10 -0300)]
Include missing step in automated build

The newly added pyfnwriter script needs to run just before pywriter.

2 months agoMove the reset code outside of the sub-test
Cesar Strauss [Sat, 22 May 2021 20:31:00 +0000 (17:31 -0300)]
Move the reset code outside of the sub-test

Even if a sub-test fails, the core still needs to be reset.
This code does not check any assertions, so it's safe to move it outside.

2 months agoupdate submodule
Luke Kenneth Casson Leighton [Sat, 22 May 2021 10:50:32 +0000 (11:50 +0100)]
update submodule

2 months agoupdate PLL to use Instance
Luke Kenneth Casson Leighton [Sat, 22 May 2021 10:50:25 +0000 (11:50 +0100)]
update PLL to use Instance

2 months agotest_ldst_pi.py: add dcache regression and random test from test_dcache.py
Tobias Platen [Sat, 15 May 2021 17:10:33 +0000 (19:10 +0200)]
test_ldst_pi.py: add dcache regression and random test from test_dcache.py

2 months agoadd radix MMU "miss" test
Luke Kenneth Casson Leighton [Fri, 14 May 2021 19:47:38 +0000 (20:47 +0100)]
add radix MMU "miss" test

2 months agoclear out request data on return to idle
Luke Kenneth Casson Leighton [Fri, 14 May 2021 12:04:17 +0000 (13:04 +0100)]
clear out request data on return to idle

2 months agosort out LoadStore1 misalignment FSM, also required test function pi_ld
Luke Kenneth Casson Leighton [Fri, 14 May 2021 11:09:55 +0000 (12:09 +0100)]
sort out LoadStore1 misalignment FSM, also required test function pi_ld
to be modified to understand exceptions.  pi_st TODO

2 months agoremove minerva units previously missed in cleanout
Luke Kenneth Casson Leighton [Fri, 14 May 2021 10:36:19 +0000 (11:36 +0100)]
remove minerva units previously missed in cleanout

2 months agoadd misaligned load through MMU (which is incorrectly succeeding without error)
Luke Kenneth Casson Leighton [Fri, 14 May 2021 10:30:53 +0000 (11:30 +0100)]
add misaligned load through MMU (which is incorrectly succeeding without error)

2 months agominor rework of wb_get, make generic
Luke Kenneth Casson Leighton [Thu, 13 May 2021 21:12:33 +0000 (22:12 +0100)]
minor rework of wb_get, make generic

2 months agoadded STORE test in test_ldst_pi.py, and it worked straight off
Luke Kenneth Casson Leighton [Thu, 13 May 2021 21:02:32 +0000 (22:02 +0100)]
added STORE test in test_ldst_pi.py, and it worked straight off

2 months agoupdate comments in issuer.py regarding a 4th FSM
Luke Kenneth Casson Leighton [Thu, 13 May 2021 21:01:54 +0000 (22:01 +0100)]
update comments in issuer.py regarding a 4th FSM

2 months agoyet more debug log stuff for DCache, this time on CacheRam, to discern
Luke Kenneth Casson Leighton [Thu, 13 May 2021 19:02:00 +0000 (20:02 +0100)]
yet more debug log stuff for DCache, this time on CacheRam, to discern
which SRAM the read/write request went to

2 months agofix wb_get error where data was being corrupted
Luke Kenneth Casson Leighton [Thu, 13 May 2021 19:01:20 +0000 (20:01 +0100)]
fix wb_get error where data was being corrupted
(not WB classic compliant)

2 months agoadd read at different locations in test_ldst_pi.py
Luke Kenneth Casson Leighton [Thu, 13 May 2021 17:05:01 +0000 (18:05 +0100)]
add read at different locations in test_ldst_pi.py

2 months agoadd some data for MMU to actually look up
Luke Kenneth Casson Leighton [Thu, 13 May 2021 16:46:07 +0000 (17:46 +0100)]
add some data for MMU to actually look up

2 months agoha, hilarious: swapped TLBUpdate output sizes db_out and pb_out.
Luke Kenneth Casson Leighton [Thu, 13 May 2021 16:35:07 +0000 (17:35 +0100)]
ha, hilarious: swapped TLBUpdate output sizes db_out and pb_out.

2 months agowhoops TLBIE must *clear* the valid bit not set it. TLBUpdate
Luke Kenneth Casson Leighton [Thu, 13 May 2021 15:39:33 +0000 (16:39 +0100)]
whoops TLBIE must *clear* the valid bit not set it.  TLBUpdate

2 months agomore debug Display in dcache.py
Luke Kenneth Casson Leighton [Thu, 13 May 2021 15:38:18 +0000 (16:38 +0100)]
more debug Display in dcache.py

2 months agoputting in a lot more debug print statements in DCache, investigation
Luke Kenneth Casson Leighton [Thu, 13 May 2021 13:14:43 +0000 (14:14 +0100)]
putting in a lot more debug print statements in DCache, investigation

2 months agoadd dcache tlb / pte test
Luke Kenneth Casson Leighton [Wed, 12 May 2021 19:15:35 +0000 (20:15 +0100)]
add dcache tlb / pte test

2 months agoset m_out.load from ldst_r(egister) in LoadStore1
Luke Kenneth Casson Leighton [Wed, 12 May 2021 19:04:12 +0000 (20:04 +0100)]
set m_out.load from ldst_r(egister) in LoadStore1

2 months agomove dcache unit test to separate test_dcache.py
Luke Kenneth Casson Leighton [Wed, 12 May 2021 18:48:23 +0000 (19:48 +0100)]
move dcache unit test to separate test_dcache.py

2 months agoexperimentation with MMU-enabled LoadStore1 through PortInterface
Luke Kenneth Casson Leighton [Wed, 12 May 2021 18:35:35 +0000 (19:35 +0100)]
experimentation with MMU-enabled LoadStore1 through PortInterface
added was a way to capture a snapshot of the incoming LD/ST request,
so that it can be re-presented after an MMU lookup.

2 months agoadd debug info, update comments, disable dcache in test
Luke Kenneth Casson Leighton [Wed, 12 May 2021 14:33:04 +0000 (15:33 +0100)]
add debug info, update comments, disable dcache in test
all tracking down bugs in test_ldst_pi.py

2 months agostart doing virtual memory queries via PortInterface on LoadStore1
Luke Kenneth Casson Leighton [Wed, 12 May 2021 14:07:09 +0000 (15:07 +0100)]
start doing virtual memory queries via PortInterface on LoadStore1

2 months agowhoops missing default zero (no idea how)
Luke Kenneth Casson Leighton [Wed, 12 May 2021 13:35:55 +0000 (14:35 +0100)]
whoops missing default zero (no idea how)

2 months agoaddcomments for MMU PortInterface test (how it, um, doesnt actually use PortInterface? :)
Luke Kenneth Casson Leighton [Wed, 12 May 2021 12:17:33 +0000 (13:17 +0100)]
addcomments for MMU PortInterface test (how it, um, doesnt actually use PortInterface? :)

2 months agobit of a hack to get test_mmu_dcache_pi.py operational.
Luke Kenneth Casson Leighton [Wed, 12 May 2021 12:15:05 +0000 (13:15 +0100)]
bit of a hack to get test_mmu_dcache_pi.py operational.
if missing data from the mem dictionary in wb_get, return zero

2 months agowhitespace
Luke Kenneth Casson Leighton [Wed, 12 May 2021 12:04:51 +0000 (13:04 +0100)]
whitespace