soc.git
71 min agopriv_mode/virt_mode are set in the request, which is passed through master
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 19:35:41 +0000 (19:35 +0000)]
priv_mode/virt_mode are set in the request, which is passed through
to the MMU, via the PortInterface "pr" parameter.

MMU should not itself be attempting to set d_in.priv_mode/virt_mode

this fixes case_5_ldst_exception

87 min agoin loadstore.py set align_intr from request which comes from PortInterface
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 19:19:36 +0000 (19:19 +0000)]
in loadstore.py set align_intr from request which comes from PortInterface
misalign, set it globally rather than from latched copy ldst_r

90 min agodriver conflict on priv_mode and virt_mode, do not understand right now,
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 19:17:11 +0000 (19:17 +0000)]
driver conflict on priv_mode and virt_mode, do not understand right now,
commenting them out in loadstore.py

3 hours agofix up test_loadstore1.py
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 17:41:33 +0000 (17:41 +0000)]
fix up test_loadstore1.py

numerous things:
1) pi_ld and pi_st now return the exception information (full status)
   because pi_ld and pi_st both reset the PortInterface: once that
   happens the exception information is DESTROYED... therefore the
   exception information MUST be obtained INSIDE pi_ld and pi_st

2) cleanup of whitespace

3) added some (probably unnecessary) yields in between LD/ST in the
   exceptions test, to make the gtkwave output clearer

4) fixed the exceptions test and enabled it by default, now

3 hours agoin loadstore.py, when an exception is done or if the FSM
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 17:38:26 +0000 (17:38 +0000)]
in loadstore.py, when an exception is done or if the FSM
is done, reset back to idle and indicate "not busy"

3 hours agofix PortInterfaceBase
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 17:37:26 +0000 (17:37 +0000)]
fix PortInterfaceBase

* setting busy latch LOW on exception is not ok: this creates a
  combinatorial loop
* setting st_done permanently was a bug, it left st_done permanently HI
* setting st_done when an exception is raised was also a bug

3 hours agofix up LDST test functions pi_ld and pi_st to respect timing
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 17:35:16 +0000 (17:35 +0000)]
fix up LDST test functions pi_ld and pi_st to respect timing
(combinatorial setting followed by test followed by immediate unsetting
is *not* ok.  it has to be set WAIT (yield one clock) and *then* clear)

added a simulation function get_exception_info() which returns a
LDSTExceptionTuple containing the yield()ed exception information
reason: at the time that the exception was raised, THAT is when
the exception information must be obtained.  by the time that
the LDST port is_ld_i/is_st_i is lowered, that is far too late

4 hours agowhitespace
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 15:51:04 +0000 (15:51 +0000)]
whitespace

5 hours agoadd misaligned ld/st to trigger an exception
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 15:22:10 +0000 (15:22 +0000)]
add misaligned ld/st to trigger an exception

5 hours agocomment out dsisr and dar in mmu FSM for now
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 15:09:22 +0000 (15:09 +0000)]
comment out dsisr and dar in mmu FSM for now

25 hours agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Thu, 2 Dec 2021 19:01:56 +0000 (20:01 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

25 hours agocleanup test_compldst_multi_mmu.py
Tobias Platen [Thu, 2 Dec 2021 18:57:43 +0000 (19:57 +0100)]
cleanup test_compldst_multi_mmu.py

27 hours agoadd a bitvector remap function, the plan is to use it to reduce the size of
Luke Kenneth Casson Leighton [Thu, 2 Dec 2021 16:56:58 +0000 (16:56 +0000)]
add a bitvector remap function, the plan is to use it to reduce the size of
regfile bitvector hazards

28 hours agofix test_random in test_loadstore1
Tobias Platen [Thu, 2 Dec 2021 16:25:12 +0000 (17:25 +0100)]
fix test_random in test_loadstore1

29 hours agouse new namedtuple in core when calling regspec_decode()
Luke Kenneth Casson Leighton [Thu, 2 Dec 2021 15:07:38 +0000 (15:07 +0000)]
use new namedtuple in core when calling regspec_decode()

29 hours agoadd module parameter to regspec_decode and therefore to get_byregfiles
Luke Kenneth Casson Leighton [Thu, 2 Dec 2021 14:56:50 +0000 (14:56 +0000)]
add module parameter to regspec_decode and therefore to get_byregfiles
as well

41 hours agoremove bitmanip fu cuz ternlogi (the only instruction implemented so far) is in shift...
Jacob Lifshay [Thu, 2 Dec 2021 03:03:26 +0000 (19:03 -0800)]
remove bitmanip fu cuz ternlogi (the only instruction implemented so far) is in shiftrot instead

41 hours agoadd ternlogi to shiftrot
Jacob Lifshay [Thu, 2 Dec 2021 03:01:12 +0000 (19:01 -0800)]
add ternlogi to shiftrot

42 hours agoformat code
Jacob Lifshay [Thu, 2 Dec 2021 02:12:42 +0000 (18:12 -0800)]
format code

2 days agostack of changes to MultiCompUnit to speed it up
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 19:47:27 +0000 (19:47 +0000)]
stack of changes to MultiCompUnit to speed it up
a lot of comb settings were changed to sync as a hack-experiment
when TestIssuer (ls180) was being developed, to try to speed up ECP5
timing.  those need reverting to reduce latency

2 days agoexperimenting with option to shorten MultiCompUnit delays
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 16:25:10 +0000 (16:25 +0000)]
experimenting with option to shorten MultiCompUnit delays

2 days agocreate single-stage ALU pipeline, shorten latency on in-order core
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 16:24:50 +0000 (16:24 +0000)]
create single-stage ALU pipeline, shorten latency on in-order core

2 days agoallow MultiCompUnit to set read and write latches to run on sync or comb
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 15:59:27 +0000 (15:59 +0000)]
allow MultiCompUnit to set read and write latches to run on sync or comb

2 days agoFunctionUnitBaseMulti which derives from ReservationStations2
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 13:41:21 +0000 (13:41 +0000)]
FunctionUnitBaseMulti which derives from ReservationStations2
*requires* the muxid to be set for each RS.  these can be set
combinatorially no problem, to indicate to ReservationStations2 where
to route the data after it pops out the end of the "real" ALU
without these muxids being set everything is royally screwed

2 days agobetter name for read latch in core.py
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 13:01:01 +0000 (13:01 +0000)]
better name for read latch in core.py

2 days agouse m.submodules[name] instead of getattr
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 13:00:41 +0000 (13:00 +0000)]
use m.submodules[name] instead of getattr

2 days agoremove redundant / mis-named variable in core
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 12:20:23 +0000 (12:20 +0000)]
remove redundant / mis-named variable in core

2 days agocode-comments
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 12:19:33 +0000 (12:19 +0000)]
code-comments

2 days agoremove unneeded data structure in core
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 12:16:18 +0000 (12:16 +0000)]
remove unneeded data structure in core

2 days agowhoops treereduce on write-vector set/clr error
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 12:12:27 +0000 (12:12 +0000)]
whoops treereduce on write-vector set/clr error

2 days agomore code-cleanup
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 12:10:48 +0000 (12:10 +0000)]
more code-cleanup

2 days agouse new regspec_decode and fu.get_iospec functions
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 12:07:45 +0000 (12:07 +0000)]
use new regspec_decode and fu.get_iospec functions

2 days agocore tidyup
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 12:04:03 +0000 (12:04 +0000)]
core tidyup

2 days agoadd Regspecs get_io_spec function
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 11:53:27 +0000 (11:53 +0000)]
add Regspecs get_io_spec function

3 days agostart allocating more FUs (more ReservationStations)
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 18:29:41 +0000 (18:29 +0000)]
start allocating more FUs (more ReservationStations)

3 days agorandom loadstore1 test: readback written data
Tobias Platen [Tue, 30 Nov 2021 17:52:10 +0000 (18:52 +0100)]
random loadstore1 test: readback written data

3 days agoreenable dcbz test case
Tobias Platen [Tue, 30 Nov 2021 17:29:58 +0000 (18:29 +0100)]
reenable dcbz test case

3 days agoreturn correct data from microwatt
Tobias Platen [Tue, 30 Nov 2021 17:29:27 +0000 (18:29 +0100)]
return correct data from microwatt

3 days agocleanup test_loadstore1.py
Tobias Platen [Tue, 30 Nov 2021 17:22:16 +0000 (18:22 +0100)]
cleanup test_loadstore1.py

3 days agoloadstore: add done_delay
Tobias Platen [Tue, 30 Nov 2021 16:56:45 +0000 (17:56 +0100)]
loadstore: add done_delay

3 days agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Tue, 30 Nov 2021 16:52:40 +0000 (17:52 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

3 days agoadd LogicalTestCases back in to test_core.py (pass)
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 16:25:45 +0000 (16:25 +0000)]
add LogicalTestCases back in to test_core.py (pass)

3 days agolet PowerDecode2 decide which operand class to use in test_core.py
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 16:23:43 +0000 (16:23 +0000)]
let PowerDecode2 decide which operand class to use in test_core.py
this gets it to pick *all* fields

3 days agouse latched readflag (recspec_decode_read "ok") instead of global one
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 16:12:31 +0000 (16:12 +0000)]
use latched readflag (recspec_decode_read "ok") instead of global one

3 days agotidyup on read-flag latches
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 16:11:58 +0000 (16:11 +0000)]
tidyup on read-flag latches

3 days agofix read-decode information by latching not just the read reg number
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 14:05:38 +0000 (14:05 +0000)]
fix read-decode information by latching not just the read reg number
but *whether it is valid or not*.
not only the register *number* from regspec_decode_read() needs to
be captured but its ok (valid) flag as well

this error only showed up when a mul (2-operand) was followed by addi
(1-operand).  the mul had its 2nd operand dropped on the floor because
the *addi* only has one operand.

3 days agofix write-after-write hazard checking
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 13:21:29 +0000 (13:21 +0000)]
fix write-after-write hazard checking

3 days agoallow busy to settle before checking state in test_core.py
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 12:11:45 +0000 (12:11 +0000)]
allow busy to settle before checking state in test_core.py

3 days agoonly check regs right at the end in test_core.py overlap mode
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 12:03:29 +0000 (12:03 +0000)]
only check regs right at the end in test_core.py overlap mode

3 days agomove sim call before core run in test_core.py
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 11:49:33 +0000 (11:49 +0000)]
move sim call before core run in test_core.py
to give PC a chance to settle in regfile

3 days agogetting formerly unused test_core.py operational
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 11:13:24 +0000 (11:13 +0000)]
getting formerly unused test_core.py operational

4 days agowhoops missed make_hazard_vec test
Luke Kenneth Casson Leighton [Mon, 29 Nov 2021 16:41:00 +0000 (16:41 +0000)]
whoops missed make_hazard_vec test

4 days agowhoops do the set/get of the write-vector at a single access point
Luke Kenneth Casson Leighton [Mon, 29 Nov 2021 15:50:26 +0000 (15:50 +0000)]
whoops do the set/get of the write-vector at a single access point
for example: INT o, INT o2 is *two* write ports.  therefore,
previously, there was a comb += wvint bitvector for o, which was
then OVERWRITTEN by a second comb += wvint bitvector for o2

instead, return the wvset/wvclr requests to connect_wrport, which
collates by regfile name and performs an additional or-tree-reduce
on the requests to set/get

4 days agoalways set fwd_bus_mode=False on regfiles
Luke Kenneth Casson Leighton [Mon, 29 Nov 2021 13:43:36 +0000 (13:43 +0000)]
always set fwd_bus_mode=False on regfiles

4 days agoadd MMU and SPR to list of FUs that must report "busy" i.e. block
Luke Kenneth Casson Leighton [Mon, 29 Nov 2021 13:19:45 +0000 (13:19 +0000)]
add MMU and SPR to list of FUs that must report "busy" i.e. block

4 days agodisallow overlap in core on LDST, Branch, and Trap.
Luke Kenneth Casson Leighton [Mon, 29 Nov 2021 10:26:35 +0000 (10:26 +0000)]
disallow overlap in core on LDST, Branch, and Trap.
these are all the ones that could cause exceptions or mess with ordering

4 days agouse dict style not setattr on submodules
Luke Kenneth Casson Leighton [Mon, 29 Nov 2021 10:22:09 +0000 (10:22 +0000)]
use dict style not setattr on submodules

5 days agoupdate loadstore1 testcase
Tobias Platen [Sun, 28 Nov 2021 13:54:32 +0000 (14:54 +0100)]
update loadstore1 testcase

6 days agocode-comments
Luke Kenneth Casson Leighton [Sat, 27 Nov 2021 14:32:21 +0000 (14:32 +0000)]
code-comments

6 days agofix instructions of the type "read-reg-is-same-as-write"
Luke Kenneth Casson Leighton [Sat, 27 Nov 2021 14:11:23 +0000 (14:11 +0000)]
fix instructions of the type "read-reg-is-same-as-write"
this then caused write-after-write detection to go into a combinatorial
loop, which was fixed by not checking fu.issue_i but instead using
fu_enable (fu_bitdict[FU])

6 days agoloadstore testcase: read at random addresses
Tobias Platen [Sat, 27 Nov 2021 12:54:22 +0000 (13:54 +0100)]
loadstore testcase: read at random addresses

6 days agoFU-Regs matrix tidyup and comments
Luke Kenneth Casson Leighton [Sat, 27 Nov 2021 12:51:52 +0000 (12:51 +0000)]
FU-Regs matrix tidyup and comments

6 days agominor tidyup on FU-Regs Matrix
Luke Kenneth Casson Leighton [Sat, 27 Nov 2021 12:33:02 +0000 (12:33 +0000)]
minor tidyup on FU-Regs Matrix

6 days agoupdate FURegDepMatrix to multi-dest
Luke Kenneth Casson Leighton [Sat, 27 Nov 2021 12:20:33 +0000 (12:20 +0000)]
update FURegDepMatrix to multi-dest

6 days agoupdate naming on Reg_Rsv signals
Luke Kenneth Casson Leighton [Sat, 27 Nov 2021 12:19:57 +0000 (12:19 +0000)]
update naming on Reg_Rsv signals

6 days agoadd copyright and attribution notices
Luke Kenneth Casson Leighton [Sat, 27 Nov 2021 11:54:37 +0000 (11:54 +0000)]
add copyright and attribution notices
update Reg_Rsv to multi-dest

6 days agoupdate FU_RW_Pending vectors to multi-dest
Luke Kenneth Casson Leighton [Sat, 27 Nov 2021 11:44:07 +0000 (11:44 +0000)]
update FU_RW_Pending vectors to multi-dest
update Copyright and Attribution notices

6 days agoconvert DependencyRow to multiple destination latches
Luke Kenneth Casson Leighton [Sat, 27 Nov 2021 11:19:57 +0000 (11:19 +0000)]
convert DependencyRow to multiple destination latches

6 days agoadd copyright and attribution notices to dependence_cell.py
Luke Kenneth Casson Leighton [Sat, 27 Nov 2021 10:40:47 +0000 (10:40 +0000)]
add copyright and attribution notices to dependence_cell.py

6 days agoupdate license and attribution in fu_reg_matrix.py
Luke Kenneth Casson Leighton [Sat, 27 Nov 2021 10:36:30 +0000 (10:36 +0000)]
update license and attribution in fu_reg_matrix.py

7 days agoconvert score6600_multi over to using RegSpecs (in a fake way)
Luke Kenneth Casson Leighton [Fri, 26 Nov 2021 16:45:23 +0000 (16:45 +0000)]
convert score6600_multi over to using RegSpecs (in a fake way)
which by slow code-morphing the entire score6600_multi code can be
converted to be like core.py

7 days agoearly use of Array unnecessarily (all uses are static references
Luke Kenneth Casson Leighton [Fri, 26 Nov 2021 15:23:40 +0000 (15:23 +0000)]
early use of Array unnecessarily (all uses are static references
not dynamic indexing: no pmux created or needed)

7 days agoearly use of Array unnecessarily (all uses are static references
Luke Kenneth Casson Leighton [Fri, 26 Nov 2021 15:19:19 +0000 (15:19 +0000)]
early use of Array unnecessarily (all uses are static references
not dynamic indexing: no pmux created or needed)

7 days agoget score6600_multi operational again
Luke Kenneth Casson Leighton [Thu, 25 Nov 2021 21:41:04 +0000 (21:41 +0000)]
get score6600_multi operational again
main thing was a "delay" on go_read_i due to regfile read results being
one clock cycle behind.

7 days agoadd debug prints in old simulator
Luke Kenneth Casson Leighton [Thu, 25 Nov 2021 21:38:54 +0000 (21:38 +0000)]
add debug prints in old simulator

7 days agoadd debug prints in old simulator
Luke Kenneth Casson Leighton [Thu, 25 Nov 2021 21:38:42 +0000 (21:38 +0000)]
add debug prints in old simulator

8 days agoseperate invalid test case from other test cases
Tobias Platen [Thu, 25 Nov 2021 17:54:21 +0000 (18:54 +0100)]
seperate invalid test case from other test cases

8 days agommu: add debug output
Tobias Platen [Thu, 25 Nov 2021 16:53:42 +0000 (17:53 +0100)]
mmu: add debug output

8 days agoadd testcase for invalid pagetable
Tobias Platen [Thu, 25 Nov 2021 16:07:05 +0000 (17:07 +0100)]
add testcase for invalid pagetable

8 days agopimem: reset on exception
Tobias Platen [Thu, 25 Nov 2021 16:05:25 +0000 (17:05 +0100)]
pimem: reset on exception

8 days agoremove unuses dsisr signal
Tobias Platen [Thu, 25 Nov 2021 15:49:06 +0000 (16:49 +0100)]
remove unuses dsisr signal

8 days agoreset state to idle on exception
Tobias Platen [Thu, 25 Nov 2021 15:45:10 +0000 (16:45 +0100)]
reset state to idle on exception

8 days agomore sorting scoremulti
Luke Kenneth Casson Leighton [Thu, 25 Nov 2021 09:43:14 +0000 (09:43 +0000)]
more sorting scoremulti

8 days agomore sorting out scoremulti
Luke Kenneth Casson Leighton [Thu, 25 Nov 2021 09:28:35 +0000 (09:28 +0000)]
more sorting out scoremulti

8 days agoadd test pspec for scoremulti to work
Luke Kenneth Casson Leighton [Thu, 25 Nov 2021 09:16:54 +0000 (09:16 +0000)]
add test pspec for scoremulti to work

8 days agoconvert hazard bitvectors to Reset-Priority SRLatch from nmutil
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 22:46:04 +0000 (22:46 +0000)]
convert hazard bitvectors to Reset-Priority SRLatch from nmutil

the read/write port were seriously getting in the way, by way of the
operand forwarding etc. etc. need instead to get either the immediate-latched
value (combinatorial) or the sync-delayed one, depending on circumstances.

9 days agofix exception handling in pi_ld
Tobias Platen [Wed, 24 Nov 2021 18:50:05 +0000 (19:50 +0100)]
fix exception handling in pi_ld

9 days agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Wed, 24 Nov 2021 18:30:44 +0000 (19:30 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

9 days agoimprove debug output in mmu.py
Tobias Platen [Wed, 24 Nov 2021 18:30:25 +0000 (19:30 +0100)]
improve debug output in mmu.py

9 days agofix write-after-write hazard detection
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 17:48:32 +0000 (17:48 +0000)]
fix write-after-write hazard detection

9 days agowhen allow_overlap enabled do a manual wait until all FUs have
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 17:44:36 +0000 (17:44 +0000)]
when allow_overlap enabled do a manual wait until all FUs have
entirely finished befor going on to read the regfile state
this really should be done with the DMI interface, which needs updating

9 days agocode-comments
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 16:24:03 +0000 (16:24 +0000)]
code-comments

9 days agoadd write-after-write hazard detection
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 16:06:26 +0000 (16:06 +0000)]
add write-after-write hazard detection
stall if a WaW hazard is detected, continuing to assert the main decoder
so that the relevant bits of the write-vector can be read.  these
bits are read *one clock behind* which is perfectly fine

9 days agoadd 2nd hazard bitvector port for write-after-write
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 15:18:08 +0000 (15:18 +0000)]
add 2nd hazard bitvector port for write-after-write
hazard detection

9 days agowhoops merged the two write-ports for RT and RA-with-update
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 12:31:52 +0000 (12:31 +0000)]
whoops merged the two write-ports for RT and RA-with-update

9 days agodisable hazard vectors when overlap is not requested in core.py
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 11:55:14 +0000 (11:55 +0000)]
disable hazard vectors when overlap is not requested in core.py

9 days agoupdate submodules
Luke Kenneth Casson Leighton [Tue, 23 Nov 2021 22:45:03 +0000 (22:45 +0000)]
update submodules

9 days agomore comments
Luke Kenneth Casson Leighton [Tue, 23 Nov 2021 22:44:55 +0000 (22:44 +0000)]
more comments

10 days agopimem changes for st exception handling
Tobias Platen [Tue, 23 Nov 2021 18:12:10 +0000 (19:12 +0100)]
pimem changes for st exception handling

10 days agofix test_loadstore1.py
Tobias Platen [Tue, 23 Nov 2021 17:42:22 +0000 (18:42 +0100)]
fix test_loadstore1.py