soc.git
7 min agofix own copy/paste error master
Tobias Platen [Mon, 25 May 2020 14:31:15 +0000 (16:31 +0200)]
fix own copy/paste error

8 min agowhitespace fix in docstring
Tobias Platen [Mon, 25 May 2020 14:29:39 +0000 (16:29 +0200)]
whitespace fix in docstring

14 min agocorrect links in regfile docstring
Luke Kenneth Casson Leighton [Mon, 25 May 2020 14:24:31 +0000 (15:24 +0100)]
correct links in regfile docstring

25 min agodocument regfiles
Luke Kenneth Casson Leighton [Mon, 25 May 2020 14:13:16 +0000 (15:13 +0100)]
document regfiles

44 min agoargh! frickin MACos terminal expanded out to 86x30 not 80x30
Luke Kenneth Casson Leighton [Mon, 25 May 2020 13:54:06 +0000 (14:54 +0100)]
argh!  frickin MACos terminal expanded out to 86x30 not 80x30

45 min agoadd docstring
Luke Kenneth Casson Leighton [Mon, 25 May 2020 13:52:40 +0000 (14:52 +0100)]
add docstring

55 min agoadd INT, SPR and CR regfiles
Luke Kenneth Casson Leighton [Mon, 25 May 2020 13:43:15 +0000 (14:43 +0100)]
add INT, SPR and CR regfiles

56 min agorefactoring (see #216 Comment 43)
Tobias Platen [Mon, 25 May 2020 13:41:49 +0000 (15:41 +0200)]
refactoring (see #216 Comment 43)

94 min agowhitespace changes
Tobias Platen [Mon, 25 May 2020 13:03:54 +0000 (15:03 +0200)]
whitespace changes

2 hours agoquick addition of zero+immed test to LDSTCompUnit
Luke Kenneth Casson Leighton [Mon, 25 May 2020 11:44:38 +0000 (12:44 +0100)]
quick addition of zero+immed test to LDSTCompUnit

3 hours agomust not do rd-req checking when both imm and zero mode are enabled
Luke Kenneth Casson Leighton [Mon, 25 May 2020 10:43:28 +0000 (11:43 +0100)]
must not do rd-req checking when both imm and zero mode are enabled

4 hours agoimplement DataMerger interface
Tobias Platen [Mon, 25 May 2020 09:47:00 +0000 (11:47 +0200)]
implement DataMerger interface

10 hours agoadd zero immed on LDST, untested
Luke Kenneth Casson Leighton [Mon, 25 May 2020 03:43:56 +0000 (04:43 +0100)]
add zero immed on LDST, untested

12 hours agocomment out invalid test
Luke Kenneth Casson Leighton [Mon, 25 May 2020 02:26:46 +0000 (03:26 +0100)]
comment out invalid test

12 hours agolots of greater than 80 chars
Luke Kenneth Casson Leighton [Mon, 25 May 2020 02:23:10 +0000 (03:23 +0100)]
lots of greater than 80 chars

12 hours agoswitch out req rel if immediate enabled
Luke Kenneth Casson Leighton [Mon, 25 May 2020 02:19:20 +0000 (03:19 +0100)]
switch out req rel if immediate enabled

13 hours agoShow oper_r and oper_i in the signal list, in simulation
Cesar Strauss [Mon, 25 May 2020 00:40:52 +0000 (21:40 -0300)]
Show oper_r and oper_i in the signal list, in simulation

14 hours agomention zeroing
Luke Kenneth Casson Leighton [Mon, 25 May 2020 00:11:49 +0000 (01:11 +0100)]
mention zeroing

14 hours agoadd links to pseudocode
Luke Kenneth Casson Leighton [Mon, 25 May 2020 00:09:54 +0000 (01:09 +0100)]
add links to pseudocode

14 hours agospelling
Luke Kenneth Casson Leighton [Sun, 24 May 2020 23:58:19 +0000 (00:58 +0100)]
spelling

14 hours agospelling
Luke Kenneth Casson Leighton [Sun, 24 May 2020 23:55:52 +0000 (00:55 +0100)]
spelling

16 hours agoadd comments for SPR pipe_data
Luke Kenneth Casson Leighton [Sun, 24 May 2020 22:00:59 +0000 (23:00 +0100)]
add comments for SPR pipe_data

16 hours agoadd SPR pipe_data.py
Luke Kenneth Casson Leighton [Sun, 24 May 2020 21:43:27 +0000 (22:43 +0100)]
add SPR pipe_data.py

17 hours agoover 80 char limit
Luke Kenneth Casson Leighton [Sun, 24 May 2020 20:57:32 +0000 (21:57 +0100)]
over 80 char limit

17 hours agoadd test of reg output, for MFCRF and ISEL
Luke Kenneth Casson Leighton [Sun, 24 May 2020 20:46:56 +0000 (21:46 +0100)]
add test of reg output, for MFCRF and ISEL

18 hours agoAvoid overwriting the first vcd file with the second one
Cesar Strauss [Sun, 24 May 2020 19:48:46 +0000 (16:48 -0300)]
Avoid overwriting the first vcd file with the second one

18 hours agoRename the internal DFF of latchregisters to avoid conflict
Cesar Strauss [Sun, 24 May 2020 19:44:12 +0000 (16:44 -0300)]
Rename the internal DFF of latchregisters to avoid conflict

18 hours agoadd gitignore for branch fu formal
Luke Kenneth Casson Leighton [Sun, 24 May 2020 19:47:53 +0000 (20:47 +0100)]
add gitignore for branch fu formal

19 hours agoadd OP_CMPB formal proof
Luke Kenneth Casson Leighton [Sun, 24 May 2020 19:23:54 +0000 (20:23 +0100)]
add OP_CMPB formal proof

19 hours agoAssert that ctr is only written when needed
Michael Nolan [Sun, 24 May 2020 19:16:28 +0000 (15:16 -0400)]
Assert that ctr is only written when needed

19 hours agosplit out Popcount into separate module: visually it interferes with readability...
Luke Kenneth Casson Leighton [Sun, 24 May 2020 19:17:36 +0000 (20:17 +0100)]
split out Popcount into separate module: visually it interferes with readability of the fu logical main stage graphviz

19 hours agocopy code for MTMSR from microwatt into comments
Luke Kenneth Casson Leighton [Sun, 24 May 2020 19:05:55 +0000 (20:05 +0100)]
copy code for MTMSR from microwatt into comments

19 hours agoadd links for trap main stage
Luke Kenneth Casson Leighton [Sun, 24 May 2020 19:01:56 +0000 (20:01 +0100)]
add links for trap main stage

19 hours agoadd untested OP_MTMSR and OP_MFMSR
Luke Kenneth Casson Leighton [Sun, 24 May 2020 19:00:07 +0000 (20:00 +0100)]
add untested OP_MTMSR and OP_MFMSR

19 hours agoupdate to new CSV files in submodule
Luke Kenneth Casson Leighton [Sun, 24 May 2020 18:53:38 +0000 (19:53 +0100)]
update to new CSV files in submodule

19 hours agoadd MFMSR and MTMSRD enums to Function
Luke Kenneth Casson Leighton [Sun, 24 May 2020 18:49:30 +0000 (19:49 +0100)]
add MFMSR and MTMSRD enums to Function

20 hours agocomment and add links to branch formal proof
Luke Kenneth Casson Leighton [Sun, 24 May 2020 18:30:56 +0000 (19:30 +0100)]
comment and add links to branch formal proof

20 hours agoadd copy of bpermd proof to logical formal proof (not nice but hey)
Luke Kenneth Casson Leighton [Sun, 24 May 2020 18:20:18 +0000 (19:20 +0100)]
add copy of bpermd proof to logical formal proof (not nice but hey)

20 hours agotrack down overwrite of variable b
Luke Kenneth Casson Leighton [Sun, 24 May 2020 17:58:02 +0000 (18:58 +0100)]
track down overwrite of variable b

21 hours agoFix proof of bpermd module
Michael Nolan [Sun, 24 May 2020 15:17:12 +0000 (11:17 -0400)]
Fix proof of bpermd module

21 hours agoFix bpermd and make tests pass
Michael Nolan [Sun, 24 May 2020 15:15:54 +0000 (11:15 -0400)]
Fix bpermd and make tests pass

21 hours agoFix test_pipe_caller to conform to new Data() interface on outputs
Michael Nolan [Sun, 24 May 2020 15:15:14 +0000 (11:15 -0400)]
Fix test_pipe_caller to conform to new Data() interface on outputs

23 hours agoadd stub regfiles.py
Luke Kenneth Casson Leighton [Sun, 24 May 2020 15:05:00 +0000 (16:05 +0100)]
add stub regfiles.py

24 hours agohmm...
Luke Kenneth Casson Leighton [Sun, 24 May 2020 14:00:03 +0000 (15:00 +0100)]
hmm...

24 hours agoadd very rapid DummyALU for test purposes in MultiCompUnit
Luke Kenneth Casson Leighton [Sun, 24 May 2020 13:54:41 +0000 (14:54 +0100)]
add very rapid DummyALU for test purposes in MultiCompUnit

24 hours agocomments on branch pipeline
Luke Kenneth Casson Leighton [Sun, 24 May 2020 13:47:20 +0000 (14:47 +0100)]
comments on branch pipeline

25 hours agoconvert CR pipeline to Data.ok
Luke Kenneth Casson Leighton [Sun, 24 May 2020 13:36:28 +0000 (14:36 +0100)]
convert CR pipeline to Data.ok

25 hours agoconvert ALU to output Data on int reg
Luke Kenneth Casson Leighton [Sun, 24 May 2020 13:07:02 +0000 (14:07 +0100)]
convert ALU to output Data on int reg

25 hours agoconvert logical to output Data on int reg
Luke Kenneth Casson Leighton [Sun, 24 May 2020 13:01:28 +0000 (14:01 +0100)]
convert logical to output Data on int reg

25 hours agostart using Data in pipelines
Luke Kenneth Casson Leighton [Sun, 24 May 2020 12:47:12 +0000 (13:47 +0100)]
start using Data in pipelines

26 hours agocleanup/code-munge on ALU main stage proof
Luke Kenneth Casson Leighton [Sun, 24 May 2020 12:09:54 +0000 (13:09 +0100)]
cleanup/code-munge on ALU main stage proof

26 hours agoerror in alu output stage formal proof setup
Luke Kenneth Casson Leighton [Sun, 24 May 2020 12:03:53 +0000 (13:03 +0100)]
error in alu output stage formal proof setup

26 hours agooutput registers need to be Data type (consistently)
Luke Kenneth Casson Leighton [Sun, 24 May 2020 12:01:50 +0000 (13:01 +0100)]
output registers need to be Data type (consistently)

26 hours agospelling mistake in variable
Luke Kenneth Casson Leighton [Sun, 24 May 2020 11:59:37 +0000 (12:59 +0100)]
spelling mistake in variable

26 hours agoTODO mention OP_MTMSR/OP_MFMSR
Luke Kenneth Casson Leighton [Sun, 24 May 2020 11:54:55 +0000 (12:54 +0100)]
TODO mention OP_MTMSR/OP_MFMSR

26 hours agoadd RA to trap pipeline, for OP_MTMSR/OP_MFMSR
Luke Kenneth Casson Leighton [Sun, 24 May 2020 11:51:56 +0000 (12:51 +0100)]
add RA to trap pipeline, for OP_MTMSR/OP_MFMSR

34 hours agomove docstring to wiki for compunit
Luke Kenneth Casson Leighton [Sun, 24 May 2020 04:33:57 +0000 (05:33 +0100)]
move docstring to wiki for compunit

39 hours agoAdded branch and shift_rot imports to fu/compunits.py and created
colepoirier [Sat, 23 May 2020 22:55:31 +0000 (15:55 -0700)]
Added branch and shift_rot imports to fu/compunits.py and created
BranchFunctionUnit and ShiftRotPipeSpec classes

39 hours agoAdd a few test cases with zero_a set, in combination with imm_ok
Cesar Strauss [Sat, 23 May 2020 22:52:08 +0000 (19:52 -0300)]
Add a few test cases with zero_a set, in combination with imm_ok

39 hours agoAllow zero_a to be set when simulating an operation
Cesar Strauss [Sat, 23 May 2020 22:39:29 +0000 (19:39 -0300)]
Allow zero_a to be set when simulating an operation

40 hours agoadd input / output stage missing modules
Luke Kenneth Casson Leighton [Sat, 23 May 2020 22:24:07 +0000 (23:24 +0100)]
add input / output stage missing modules

41 hours agocommon function for op zero and op immed
Luke Kenneth Casson Leighton [Sat, 23 May 2020 20:47:17 +0000 (21:47 +0100)]
common function for op zero and op immed

43 hours agoChoose between RA (src1) and zero immediate, conditioned on zero_a
Cesar Strauss [Sat, 23 May 2020 17:22:54 +0000 (14:22 -0300)]
Choose between RA (src1) and zero immediate, conditioned on zero_a

43 hours agoupdate docs on compunits
Luke Kenneth Casson Leighton [Sat, 23 May 2020 19:02:27 +0000 (20:02 +0100)]
update docs on compunits

43 hours agoremove extraneous test_isel
Luke Kenneth Casson Leighton [Sat, 23 May 2020 18:44:13 +0000 (19:44 +0100)]
remove extraneous test_isel

44 hours agoadd comments
Luke Kenneth Casson Leighton [Sat, 23 May 2020 18:22:47 +0000 (19:22 +0100)]
add comments

44 hours agodocument purpose of regspec module
Luke Kenneth Casson Leighton [Sat, 23 May 2020 18:12:06 +0000 (19:12 +0100)]
document purpose of regspec module

44 hours agosplit out RegSpecs into separate module
Luke Kenneth Casson Leighton [Sat, 23 May 2020 18:05:31 +0000 (19:05 +0100)]
split out RegSpecs into separate module

44 hours agoadd TODO on multi-in multi-out Function Units
Luke Kenneth Casson Leighton [Sat, 23 May 2020 17:53:11 +0000 (18:53 +0100)]
add TODO on multi-in multi-out Function Units

44 hours agosplit out RegSpec API into separate class (TODO: move to separate file)
Luke Kenneth Casson Leighton [Sat, 23 May 2020 17:50:57 +0000 (18:50 +0100)]
split out RegSpec API into separate class (TODO: move to separate file)

44 hours agoadd notes on FunctionUnit API
Luke Kenneth Casson Leighton [Sat, 23 May 2020 17:40:49 +0000 (18:40 +0100)]
add notes on FunctionUnit API

45 hours agomake MultiCompUnit and testing ALU use regspec API and nmutil pipeline API
Luke Kenneth Casson Leighton [Sat, 23 May 2020 17:25:47 +0000 (18:25 +0100)]
make MultiCompUnit and testing ALU use regspec API and nmutil pipeline API

45 hours agoremove unneeded imports
Luke Kenneth Casson Leighton [Sat, 23 May 2020 17:24:45 +0000 (18:24 +0100)]
remove unneeded imports

45 hours agomake demo/test ALU look like nmigen pipeline API
Luke Kenneth Casson Leighton [Sat, 23 May 2020 17:08:08 +0000 (18:08 +0100)]
make demo/test ALU look like nmigen pipeline API

47 hours agoadd stub DataMerger class
Luke Kenneth Casson Leighton [Sat, 23 May 2020 15:21:21 +0000 (16:21 +0100)]
add stub DataMerger class

47 hours agoadd link to regspecs on wiki
Luke Kenneth Casson Leighton [Sat, 23 May 2020 14:57:25 +0000 (15:57 +0100)]
add link to regspecs on wiki

2 days agoadd regspec capability to MultiCompUnit
Luke Kenneth Casson Leighton [Sat, 23 May 2020 14:12:14 +0000 (15:12 +0100)]
add regspec capability to MultiCompUnit

2 days agoModify proof of isel to use full CR register
Michael Nolan [Sat, 23 May 2020 13:24:35 +0000 (09:24 -0400)]
Modify proof of isel to use full CR register

2 days agoAdd test_isel
Michael Nolan [Sat, 23 May 2020 13:16:23 +0000 (09:16 -0400)]
Add test_isel

2 days agomake immediate-or-RA selection optional based on awareness of operation subset
Luke Kenneth Casson Leighton [Sat, 23 May 2020 13:04:06 +0000 (14:04 +0100)]
make immediate-or-RA selection optional based on awareness of operation subset
in MultiCompUnit

2 days agostart to morph MultiCompUnit to take "regspec" as the way to decide the latch and
Luke Kenneth Casson Leighton [Sat, 23 May 2020 12:39:48 +0000 (13:39 +0100)]
start to morph MultiCompUnit to take "regspec" as the way to decide the latch and
oper_i configuration

2 days agoadd CR_ISEL formal proof to CR pipeline
Luke Kenneth Casson Leighton [Sat, 23 May 2020 10:58:43 +0000 (11:58 +0100)]
add CR_ISEL formal proof to CR pipeline

2 days agoadd CR_ISEL (and unit test) to CR pipeline
Luke Kenneth Casson Leighton [Sat, 23 May 2020 10:35:24 +0000 (11:35 +0100)]
add CR_ISEL (and unit test) to CR pipeline

2 days agoupdate to (corrected) csv files for CR_ISEL
Luke Kenneth Casson Leighton [Sat, 23 May 2020 10:20:34 +0000 (11:20 +0100)]
update to (corrected) csv files for CR_ISEL

2 days agoselect bits 2:5 from BC to get CR0 to 7 in DecodeCRin
Luke Kenneth Casson Leighton [Sat, 23 May 2020 03:13:22 +0000 (04:13 +0100)]
select bits 2:5 from BC to get CR0 to 7 in DecodeCRin

2 days agoadd gitignore
Luke Kenneth Casson Leighton [Sat, 23 May 2020 02:19:49 +0000 (03:19 +0100)]
add gitignore

2 days agoCR field on Br input data is specd as 0:3 range
Luke Kenneth Casson Leighton [Sat, 23 May 2020 02:18:10 +0000 (03:18 +0100)]
CR field on Br input data is specd as 0:3 range

2 days agoadd b to CR pipe input data, for isel
Luke Kenneth Casson Leighton [Sat, 23 May 2020 02:15:08 +0000 (03:15 +0100)]
add b to CR pipe input data, for isel

2 days agoadd TODO and link to SHIFT_ROT formal bugreport
Luke Kenneth Casson Leighton [Fri, 22 May 2020 20:37:46 +0000 (21:37 +0100)]
add TODO and link to SHIFT_ROT formal bugreport

2 days agoremove xer.so from ShiftRot formal proof
Luke Kenneth Casson Leighton [Fri, 22 May 2020 20:30:56 +0000 (21:30 +0100)]
remove xer.so from ShiftRot formal proof

2 days agoremove sticky overflow from Shift Rot pipeline
Luke Kenneth Casson Leighton [Fri, 22 May 2020 19:06:41 +0000 (20:06 +0100)]
remove sticky overflow from Shift Rot pipeline

2 days agotest branch ctr ok flag
Luke Kenneth Casson Leighton [Fri, 22 May 2020 18:59:59 +0000 (19:59 +0100)]
test branch ctr ok flag

2 days agocleaner way to test link register ok
Luke Kenneth Casson Leighton [Fri, 22 May 2020 18:52:55 +0000 (19:52 +0100)]
cleaner way to test link register ok

2 days agowhitespace
Luke Kenneth Casson Leighton [Fri, 22 May 2020 18:49:12 +0000 (19:49 +0100)]
whitespace

2 days agoFix link handling in branch proof
Michael Nolan [Fri, 22 May 2020 18:43:32 +0000 (14:43 -0400)]
Fix link handling in branch proof

2 days agoUpdate to latest wiki version - fix cr0 input for OP_CNTZ
Michael Nolan [Fri, 22 May 2020 18:30:58 +0000 (14:30 -0400)]
Update to latest wiki version - fix cr0 input for OP_CNTZ

2 days agovariable-name munging for branch formal
Luke Kenneth Casson Leighton [Fri, 22 May 2020 18:29:26 +0000 (19:29 +0100)]
variable-name munging for branch formal

2 days agoAdd formal proof for branch unit, fix bug with bcreg
Michael Nolan [Fri, 22 May 2020 18:20:13 +0000 (14:20 -0400)]
Add formal proof for branch unit, fix bug with bcreg

2 days agocleanup logical pipe formal proof
Luke Kenneth Casson Leighton [Fri, 22 May 2020 18:20:26 +0000 (19:20 +0100)]
cleanup logical pipe formal proof

2 days agosplit out Logical Input and Output stages to common code, allows removal
Luke Kenneth Casson Leighton [Fri, 22 May 2020 18:19:16 +0000 (19:19 +0100)]
split out Logical Input and Output stages to common code, allows removal
of XER.SO from Logical pipeline