soc.git
15 months agoattempting to add SPRs to rfid test
Luke Kenneth Casson Leighton [Wed, 1 Jul 2020 16:41:16 +0000 (17:41 +0100)]
attempting to add SPRs to rfid test

15 months agoadd OP_SC
Luke Kenneth Casson Leighton [Wed, 1 Jul 2020 16:14:47 +0000 (17:14 +0100)]
add OP_SC

15 months agotrap test check results
Luke Kenneth Casson Leighton [Wed, 1 Jul 2020 15:51:10 +0000 (16:51 +0100)]
trap test check results

15 months agoadd name "test_issuer" to ilang conversion
Luke Kenneth Casson Leighton [Wed, 1 Jul 2020 14:36:00 +0000 (15:36 +0100)]
add name "test_issuer" to ilang conversion

15 months agoadd in trap compunit
Luke Kenneth Casson Leighton [Wed, 1 Jul 2020 14:34:24 +0000 (15:34 +0100)]
add in trap compunit

15 months agoadd rfid and td/tw trap test
Luke Kenneth Casson Leighton [Wed, 1 Jul 2020 14:32:15 +0000 (15:32 +0100)]
add rfid and td/tw trap test

15 months agocontinue debugging trap pipeline
Luke Kenneth Casson Leighton [Wed, 1 Jul 2020 12:37:32 +0000 (13:37 +0100)]
continue debugging trap pipeline

15 months agodebugging trap pipeline
Luke Kenneth Casson Leighton [Wed, 1 Jul 2020 12:06:42 +0000 (13:06 +0100)]
debugging trap pipeline

15 months agostart running trap unit test, fixing errors
Luke Kenneth Casson Leighton [Wed, 1 Jul 2020 11:21:46 +0000 (12:21 +0100)]
start running trap unit test, fixing errors

15 months agoadd lte ltu for use by twi and other trap functions
Luke Kenneth Casson Leighton [Tue, 30 Jun 2020 14:51:09 +0000 (15:51 +0100)]
add lte ltu for use by twi and other trap functions

15 months agoadd in pseudocode keyword into mdwn isa files
Luke Kenneth Casson Leighton [Tue, 30 Jun 2020 11:31:42 +0000 (12:31 +0100)]
add in pseudocode keyword into mdwn isa files

15 months agocode-morph on div pipeline
Luke Kenneth Casson Leighton [Tue, 30 Jun 2020 10:57:00 +0000 (11:57 +0100)]
code-morph on div pipeline

15 months agoadd README for fu directory
Luke Kenneth Casson Leighton [Mon, 29 Jun 2020 21:20:41 +0000 (22:20 +0100)]
add README for fu directory

15 months agouse correct ALUHelpers in div test
Luke Kenneth Casson Leighton [Mon, 29 Jun 2020 15:08:16 +0000 (16:08 +0100)]
use correct ALUHelpers in div test

15 months agosort out syntax errors in div
Luke Kenneth Casson Leighton [Mon, 29 Jun 2020 15:03:56 +0000 (16:03 +0100)]
sort out syntax errors in div

15 months agofirst unit test for div
Luke Kenneth Casson Leighton [Mon, 29 Jun 2020 15:03:46 +0000 (16:03 +0100)]
first unit test for div

15 months agoupdate submodule to fix div bug
Luke Kenneth Casson Leighton [Mon, 29 Jun 2020 14:38:20 +0000 (15:38 +0100)]
update submodule to fix div bug

15 months agoadd ignore for parsetab.py
Luke Kenneth Casson Leighton [Mon, 29 Jun 2020 14:03:59 +0000 (15:03 +0100)]
add ignore for parsetab.py

15 months agoadd autogenerated do not commit comment
Luke Kenneth Casson Leighton [Mon, 29 Jun 2020 14:02:49 +0000 (15:02 +0100)]
add autogenerated do not commit comment

15 months agoupdate submodule to div overflow
Luke Kenneth Casson Leighton [Mon, 29 Jun 2020 13:58:43 +0000 (14:58 +0100)]
update submodule to div overflow

15 months agoseparate out divide by zero cases
Luke Kenneth Casson Leighton [Mon, 29 Jun 2020 13:40:49 +0000 (14:40 +0100)]
separate out divide by zero cases

15 months agoupdate OV and OV32 ISACaller flags if overflow occurs
Luke Kenneth Casson Leighton [Mon, 29 Jun 2020 13:39:27 +0000 (14:39 +0100)]
update OV and OV32 ISACaller flags if overflow occurs

15 months agoattempting to add overflow setting in ISACaller
Luke Kenneth Casson Leighton [Mon, 29 Jun 2020 13:29:27 +0000 (14:29 +0100)]
attempting to add overflow setting in ISACaller

15 months agowhoops, hex parser digits are in multiples of 4 bits
Luke Kenneth Casson Leighton [Mon, 29 Jun 2020 12:28:08 +0000 (13:28 +0100)]
whoops, hex parser digits are in multiples of 4 bits

15 months agofetch instructions from bare wishbone fetch unit
Luke Kenneth Casson Leighton [Mon, 29 Jun 2020 10:53:25 +0000 (11:53 +0100)]
fetch instructions from bare wishbone fetch unit

15 months agoStart with a simpler test case
Cesar Strauss [Sun, 28 Jun 2020 22:17:31 +0000 (19:17 -0300)]
Start with a simpler test case

Leave other variants (immediate, rdmaskn) for later.

15 months agoLet p.ready_o be active while the test ALU is idle
Cesar Strauss [Sun, 28 Jun 2020 21:38:03 +0000 (18:38 -0300)]
Let p.ready_o be active while the test ALU is idle

The valid/ready protocol doesn't actually forbid p.ready_o
being active while p.valid_i is inactive. It just mean that
the ALU is idle, and is ready to accept new data.

This should help avoiding potential combinatorial loops from
p.ready_o to p.valid_i.

15 months agoadd cached fetch unit pass-through args
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 21:41:18 +0000 (22:41 +0100)]
add cached fetch unit pass-through args

15 months agoneed args to WishboneArbiter, match data width size
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 21:38:37 +0000 (22:38 +0100)]
need args to WishboneArbiter, match data width size

15 months agoAdd missing ports to the test ALU
Cesar Strauss [Sun, 28 Jun 2020 20:44:10 +0000 (17:44 -0300)]
Add missing ports to the test ALU

15 months agoread from instruction memory using FetchUnitInterface
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 20:14:52 +0000 (21:14 +0100)]
read from instruction memory using FetchUnitInterface

15 months agoadd Config Fetch interface and quick unit test
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 19:37:07 +0000 (20:37 +0100)]
add Config Fetch interface and quick unit test

15 months agoadd test instruction memory
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 19:21:23 +0000 (20:21 +0100)]
add test instruction memory

15 months agoadd readonly option to TestMemory
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 19:19:14 +0000 (20:19 +0100)]
add readonly option to TestMemory

15 months agoexpand instruction bus width to 64 bit, start on a mini-cache
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 17:23:08 +0000 (18:23 +0100)]
expand instruction bus width to 64 bit, start on a mini-cache
for instructions (one line)

15 months agoparameterise minerva i-cache
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 16:20:15 +0000 (17:20 +0100)]
parameterise minerva i-cache

15 months agogot Pi2LSUI FSM working
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 14:39:10 +0000 (15:39 +0100)]
got Pi2LSUI FSM working

15 months agosram address do not cut by LSBs
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 12:17:09 +0000 (13:17 +0100)]
sram address do not cut by LSBs

15 months agonew Pi2LSUI working, using PortInterfaceBase
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 11:03:24 +0000 (12:03 +0100)]
new Pi2LSUI working, using PortInterfaceBase

15 months agostart new version of Pi2LSUI based on PortInterfaceBase
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 10:43:17 +0000 (11:43 +0100)]
start new version of Pi2LSUI based on PortInterfaceBase

15 months agopass addr/mask through to PortInterfaceBase rd/wr addr
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 10:24:30 +0000 (11:24 +0100)]
pass addr/mask through to PortInterfaceBase rd/wr addr

15 months agocleanup (remove unneeded imports)
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 10:19:03 +0000 (11:19 +0100)]
cleanup (remove unneeded imports)

15 months agomore code-shuffle for TestMemoryPortInterface
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 10:16:48 +0000 (11:16 +0100)]
more code-shuffle for TestMemoryPortInterface

15 months agomore code-shuffle for TestMemoryPortInterface
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 10:13:24 +0000 (11:13 +0100)]
more code-shuffle for TestMemoryPortInterface

15 months agominor cleanup, put get/set rdport/wrport into function
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 09:38:17 +0000 (10:38 +0100)]
minor cleanup, put get/set rdport/wrport into function

15 months agomerge LDSTPort into TestMemoryPortInterface
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 09:23:31 +0000 (10:23 +0100)]
merge LDSTPort into TestMemoryPortInterface

15 months agouse PortInterface connect_port
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 09:21:19 +0000 (10:21 +0100)]
use PortInterface connect_port

15 months agouse PortInterface connect_port
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 09:18:57 +0000 (10:18 +0100)]
use PortInterface connect_port

15 months agoattempt to get Pi2LSUI FSM working
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 09:14:36 +0000 (10:14 +0100)]
attempt to get Pi2LSUI FSM working

15 months agoonly activate ld_in_progress if addr is ok
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 20:35:27 +0000 (21:35 +0100)]
only activate ld_in_progress if addr is ok

15 months agomake Memory accessible via TestSRAMBareLoadStoreUnit
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 19:21:12 +0000 (20:21 +0100)]
make Memory accessible via TestSRAMBareLoadStoreUnit

15 months agoincrease (double) address width in TstL0CacheBuffer
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 19:12:55 +0000 (20:12 +0100)]
increase (double) address width in TstL0CacheBuffer

15 months agoincrease (double) address width in TstL0CacheBuffer
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 19:12:02 +0000 (20:12 +0100)]
increase (double) address width in TstL0CacheBuffer

15 months agounit test in l0_cache to connect to testpi and test_bare_wb
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 19:05:26 +0000 (20:05 +0100)]
unit test in l0_cache to connect to testpi and test_bare_wb

15 months agomake PortInterface modules consistent with same API
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 18:43:00 +0000 (19:43 +0100)]
make PortInterface modules consistent with same API

15 months agouse ConfigMemoryPortInterface in TstL0CacheBuffer
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 18:24:34 +0000 (19:24 +0100)]
use ConfigMemoryPortInterface in TstL0CacheBuffer

15 months agofix TestMemLoadStoreUnit, it required a FSM to monitor write
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 16:50:07 +0000 (17:50 +0100)]
fix TestMemLoadStoreUnit, it required a FSM to monitor write
and also needed to honour the "busy_o" signal

15 months agoadd wishbone Pi2LSUI test
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 14:20:24 +0000 (15:20 +0100)]
add wishbone Pi2LSUI test

15 months agoreconfigureable PortInterface testing now possible
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 12:34:57 +0000 (13:34 +0100)]
reconfigureable PortInterface testing now possible

16 months agoname issue in Pi2LSUI
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 23:29:36 +0000 (00:29 +0100)]
name issue in Pi2LSUI

16 months agowhitespace and imports
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 23:26:58 +0000 (00:26 +0100)]
whitespace and imports

16 months agowhitespace
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 23:25:17 +0000 (00:25 +0100)]
whitespace

16 months agoslight reorg on test_pi2ls.py
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 22:40:08 +0000 (23:40 +0100)]
slight reorg on test_pi2ls.py

16 months agocorrect address in pi2ls
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 22:38:37 +0000 (23:38 +0100)]
correct address in pi2ls

16 months agooops forgot to initialise base class of TestMemLoadStoreUnit
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 22:22:37 +0000 (23:22 +0100)]
oops forgot to initialise base class of TestMemLoadStoreUnit

16 months agoadd in LenExpand shift/mask
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 21:06:32 +0000 (22:06 +0100)]
add in LenExpand shift/mask

16 months agoadd quick test showing Pi2LSUI not quite reading/writing to
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 19:47:16 +0000 (20:47 +0100)]
add quick test showing Pi2LSUI not quite reading/writing to
correct addresses

16 months agoremove extraneous yields
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 19:40:52 +0000 (20:40 +0100)]
remove extraneous yields

16 months agoModify pi2ls so it passes the portinterface unit tests
Michael Nolan [Fri, 26 Jun 2020 19:36:41 +0000 (15:36 -0400)]
Modify pi2ls so it passes the portinterface unit tests

16 months agoset address ok and fix unit test to check it properly
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 19:37:46 +0000 (20:37 +0100)]
set address ok and fix unit test to check it properly

16 months agoadd pi.busy_o connection, increase to 64 bit
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 19:30:18 +0000 (20:30 +0100)]
add pi.busy_o connection, increase to 64 bit

16 months agounit test broken is ok :)
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 19:12:30 +0000 (20:12 +0100)]
unit test broken is ok :)

16 months agoset pi.ld.ok to 1 if pi.is_ld_i is set
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 19:09:57 +0000 (20:09 +0100)]
set pi.ld.ok to 1 if pi.is_ld_i is set

16 months agoMove tests for pimem to new file, add ability to test pi2ls.py
Michael Nolan [Fri, 26 Jun 2020 18:58:54 +0000 (14:58 -0400)]
Move tests for pimem to new file, add ability to test pi2ls.py

16 months agoload/store unit test needed to wait for busy_o
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 18:00:07 +0000 (19:00 +0100)]
load/store unit test needed to wait for busy_o
otherwise, the bus was still processing the previous transaction

16 months agowhitespace
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 17:58:38 +0000 (18:58 +0100)]
whitespace

16 months agoclean up output from BareLoadStoreUnit
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 17:58:28 +0000 (18:58 +0100)]
clean up output from BareLoadStoreUnit

16 months agohalve the test memory size again
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 16:20:20 +0000 (17:20 +0100)]
halve the test memory size again

16 months agoshrink test memory size down to only 64 words
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 16:17:44 +0000 (17:17 +0100)]
shrink test memory size down to only 64 words

16 months agoinvestigating why write-enable not getting passed through
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 15:52:34 +0000 (16:52 +0100)]
investigating why write-enable not getting passed through
on nmigen_soc sram

16 months agowhoops forgot to call parent elaborate
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 13:35:23 +0000 (14:35 +0100)]
whoops forgot to call parent elaborate

16 months agoadd test of SRAM through wishbone bus
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 13:24:51 +0000 (14:24 +0100)]
add test of SRAM through wishbone bus

16 months agocode-morph which redirects lsmem unit test through new ConfigLoadStoreUnit
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 12:14:47 +0000 (13:14 +0100)]
code-morph which redirects lsmem unit test through new ConfigLoadStoreUnit
this to allow wishbone-SRAM test version to be tested with the same
unit test

16 months agoadd a test SRAM that lives behind a minerva LoadStoreUnitInterface
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 11:44:23 +0000 (12:44 +0100)]
add a test SRAM that lives behind a minerva LoadStoreUnitInterface

16 months agodynamically specify wishbone layout (no longer hardcoded addr/data)
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 11:16:20 +0000 (12:16 +0100)]
dynamically specify wishbone layout (no longer hardcoded addr/data)

16 months agoadd reconfigureable Load/Store class
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 10:36:34 +0000 (11:36 +0100)]
add reconfigureable Load/Store class

16 months agoextra parameterification of minerva LoadStoreUnits
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 08:53:26 +0000 (09:53 +0100)]
extra parameterification of minerva LoadStoreUnits

16 months agoallow Pi2LSUI to accept incoming PortInterface and LoadStoreUnitInterface
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 21:12:47 +0000 (22:12 +0100)]
allow Pi2LSUI to accept incoming PortInterface and LoadStoreUnitInterface

16 months agoadd extra parameter, mask_wid, to TestMemLoadStoreUnit
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 20:59:39 +0000 (21:59 +0100)]
add extra parameter, mask_wid, to TestMemLoadStoreUnit

16 months agostart connecting up Pi2LSUI
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 19:41:35 +0000 (20:41 +0100)]
start connecting up Pi2LSUI

16 months agoadd LenExpand module, tidyup on docstring
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 19:29:25 +0000 (20:29 +0100)]
add LenExpand module, tidyup on docstring

16 months agoadd beginnings of Pi2LSUI
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 19:25:13 +0000 (20:25 +0100)]
add beginnings of Pi2LSUI

16 months agoadd nmigen-soc to dependencies
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 11:53:27 +0000 (12:53 +0100)]
add nmigen-soc to dependencies

16 months agoadd attempt at mapping between PortInterface and LoadStoreUnitInterface
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 09:56:35 +0000 (10:56 +0100)]
add attempt at mapping between PortInterface and LoadStoreUnitInterface

16 months agorename LoadStoreInterface signals to include _i and _o suffixes
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 09:43:42 +0000 (10:43 +0100)]
rename LoadStoreInterface signals to include _i and _o suffixes
got fed up of not knowing which Signal was which direction

16 months agowhitespace
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 09:34:03 +0000 (10:34 +0100)]
whitespace

16 months agoRevert "modify PortInterface so subfields include the port's name"
Michael Nolan [Wed, 24 Jun 2020 19:43:29 +0000 (15:43 -0400)]
Revert "modify PortInterface so subfields include the port's name"

No longer necessary with changes to nmutil f61e3beee

This reverts commit 8c63d6dfe17825ca984854e33e20589df6c5bdb6.

16 months agoUpdate comments for LoadStoreUnitInterface
Michael Nolan [Wed, 24 Jun 2020 18:20:49 +0000 (14:20 -0400)]
Update comments for LoadStoreUnitInterface

16 months agoHave lsmem handle stall and valid signals correctly
Michael Nolan [Wed, 24 Jun 2020 18:18:42 +0000 (14:18 -0400)]
Have lsmem handle stall and valid signals correctly

16 months agoUpdate comments on LoadStoreUnitInterface again
Michael Nolan [Wed, 24 Jun 2020 18:03:12 +0000 (14:03 -0400)]
Update comments on LoadStoreUnitInterface again