soc.git
13 months agowhoops spelling mistake outOut_carry not outPut_carry
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 17:13:33 +0000 (18:13 +0100)]
whoops spelling mistake outOut_carry not outPut_carry

13 months agoconvert mul test to use Power Decode subset
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 16:22:52 +0000 (17:22 +0100)]
convert mul test to use Power Decode subset

13 months agoconvert shift_rot to subset decoder
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 16:18:25 +0000 (17:18 +0100)]
convert shift_rot to subset decoder

13 months agoconvert branch test to PowerDecodeSubset form
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 16:16:27 +0000 (17:16 +0100)]
convert branch test to PowerDecodeSubset form

13 months agoconvert CR to PowerDecodeSubset format
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 16:13:09 +0000 (17:13 +0100)]
convert CR to PowerDecodeSubset format

13 months agobit of a big reorg of data structures
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 15:59:40 +0000 (16:59 +0100)]
bit of a big reorg of data structures

ALU test_pipe_caller.py is now testing with a subset PowerDecoder2
and the field names need to change to match up.

13 months agosplit out PowerDecode2 into PowerDecodeSubset
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 15:14:11 +0000 (16:14 +0100)]
split out PowerDecode2 into PowerDecodeSubset

13 months agolarge stack of moving stuff around in dcache
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 13:40:25 +0000 (14:40 +0100)]
large stack of moving stuff around in dcache

13 months agoadjust indentation of dcache_slow
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 13:11:32 +0000 (14:11 +0100)]
adjust indentation of dcache_slow

13 months agomore dcache translation
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 13:01:22 +0000 (14:01 +0100)]
more dcache translation

13 months agoadd start on cache_ram.vhdl to nmigen conversion
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 12:24:42 +0000 (13:24 +0100)]
add start on cache_ram.vhdl to nmigen conversion

13 months agomore dcache translation
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 12:22:45 +0000 (13:22 +0100)]
more dcache translation

13 months agoallow Decode2ToExecute1Type to take an opkls argument
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 11:00:36 +0000 (12:00 +0100)]
allow Decode2ToExecute1Type to take an opkls argument

13 months agowhoops truncated the mb and me fields
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 10:58:30 +0000 (11:58 +0100)]
whoops truncated the mb and me fields

13 months agominor reorg on PowerDecoder
Luke Kenneth Casson Leighton [Mon, 7 Sep 2020 00:01:39 +0000 (01:01 +0100)]
minor reorg on PowerDecoder

13 months agocomment, nothing unusual when Trap Type is DEC
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 21:31:17 +0000 (22:31 +0100)]
comment, nothing unusual when Trap Type is DEC

13 months agodecoder immediate b split out to DecodeBImm
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 21:21:09 +0000 (22:21 +0100)]
decoder immediate b split out to DecodeBImm

13 months agodecoder immediate a split out to DecodeAImm
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 21:16:00 +0000 (22:16 +0100)]
decoder immediate a split out to DecodeAImm

13 months agoadd row subset selector for PowerDecode.
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 20:42:51 +0000 (21:42 +0100)]
add row subset selector for PowerDecode.
allows functions to be used to create subset decoders

13 months agoadd row_subset (doesnt do anything yet)
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 20:22:09 +0000 (21:22 +0100)]
add row_subset (doesnt do anything yet)

13 months agopass col_subset throughout PowerDecoder
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 20:15:32 +0000 (21:15 +0100)]
pass col_subset throughout PowerDecoder

13 months agoreorganise PowerOp to be dynamic
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 19:59:48 +0000 (20:59 +0100)]
reorganise PowerOp to be dynamic

13 months agoreorg of PowerOp to be able to dynamically subset it
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 19:33:16 +0000 (20:33 +0100)]
reorg of PowerOp to be able to dynamically subset it

13 months agogrr, autopep8 messing up
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 19:19:03 +0000 (20:19 +0100)]
grr, autopep8 messing up

13 months agocopy dec SPR into decoder cur_state
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 18:46:41 +0000 (19:46 +0100)]
copy dec SPR into decoder cur_state

13 months agoadd reset option to Register
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 18:43:40 +0000 (19:43 +0100)]
add reset option to Register

13 months agowark-wark, fast regs is binary-addressed
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 17:00:31 +0000 (18:00 +0100)]
wark-wark, fast regs is binary-addressed

13 months agoadd unit test for slow SPRs (SPRG0/1)
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 16:49:20 +0000 (17:49 +0100)]
add unit test for slow SPRs (SPRG0/1)
add test mapping for slow SPR numbers

13 months agominor code-munge on SPR-to-FAST mapping
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 16:35:02 +0000 (17:35 +0100)]
minor code-munge on SPR-to-FAST mapping

13 months agouse with subTest in spr unit test
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 16:34:13 +0000 (17:34 +0100)]
use with subTest in spr unit test

13 months agoredo generation of microwatt.v from litex
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 16:33:48 +0000 (17:33 +0100)]
redo generation of microwatt.v from litex

13 months agoadd comments for DEC / TB
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 12:08:57 +0000 (13:08 +0100)]
add comments for DEC / TB

13 months agoadd a DEC/TB FSM to TestIssuer
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 11:56:48 +0000 (12:56 +0100)]
add a DEC/TB FSM to TestIssuer

this operates on alternative cycles, because it reads/writes from the
Fast Regfile directly

13 months agomove DEC and TB from StateRegs to FastRegs for several reasons
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 11:50:47 +0000 (12:50 +0100)]
move DEC and TB from StateRegs to FastRegs for several reasons
first: SPR pipeline already has fast1 read/write
second: a new DecodeStateIn/Out object would be needed
        instead just add FastRegs.DEC/TB to DecodeA/Out
third: there is probably a third somewhere

13 months agoadd DEC SPR to CoreState and PowerDecoder, activate 0x900 interrupt
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 11:13:16 +0000 (12:13 +0100)]
add DEC SPR to CoreState and PowerDecoder, activate 0x900 interrupt

13 months agoadd DEC and TB to State regfile
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 11:11:45 +0000 (12:11 +0100)]
add DEC and TB to State regfile

13 months agoadd DEC/TB SPRs to spr pipeline
Luke Kenneth Casson Leighton [Sun, 6 Sep 2020 11:11:25 +0000 (12:11 +0100)]
add DEC/TB SPRs to spr pipeline

13 months agoadd comments on MSR read
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 20:43:04 +0000 (21:43 +0100)]
add comments on MSR read

13 months agomove GPIO IRQ to 15 to match microwatt modifications
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 20:25:56 +0000 (21:25 +0100)]
move GPIO IRQ to 15 to match microwatt modifications

13 months agohmmm XICS data being asserted on wb bus for too long
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 19:52:35 +0000 (20:52 +0100)]
hmmm XICS data being asserted on wb bus for too long

13 months agoargh missed a VHDL "&" translating to Cat
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 19:44:49 +0000 (20:44 +0100)]
argh missed a VHDL "&" translating to Cat

13 months agoreduce XICS address lookup by 2 bits
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 18:06:37 +0000 (19:06 +0100)]
reduce XICS address lookup by 2 bits

13 months agoMSR read in INSN_READ only occurs for 1 cycle
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 17:15:36 +0000 (18:15 +0100)]
MSR read in INSN_READ only occurs for 1 cycle

13 months agosync on ICP eint
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 16:58:00 +0000 (17:58 +0100)]
sync on ICP eint

13 months agoconnect XICS core irq to Decode2 eint
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 16:35:17 +0000 (17:35 +0100)]
connect XICS core irq to Decode2 eint

13 months agowhoops, combinatorial loop on pending_priority
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 16:20:15 +0000 (17:20 +0100)]
whoops, combinatorial loop on pending_priority

13 months agouse stbcix in test
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 16:10:26 +0000 (17:10 +0100)]
use stbcix in test

13 months agoXICS addresses in words: divide by 4
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 16:07:04 +0000 (17:07 +0100)]
XICS addresses in words: divide by 4

13 months agowhoops, ICS in litex sim needs to be 0x1000 size region
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 15:38:56 +0000 (16:38 +0100)]
whoops, ICS in litex sim needs to be 0x1000 size region

13 months agoadd lwzcix unit test
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 15:38:40 +0000 (16:38 +0100)]
add lwzcix unit test

13 months agoincrease wishbone address width to 29 for xics and gpio
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 15:32:23 +0000 (16:32 +0100)]
increase wishbone address width to 29 for xics and gpio
this may not be exactly correct, have to see how it goes

13 months agosubmodule update
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 14:17:24 +0000 (15:17 +0100)]
submodule update

13 months agoadd simple GPIO wishbone bus to litex sim.py
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 14:03:21 +0000 (15:03 +0100)]
add simple GPIO wishbone bus to litex sim.py

13 months agoadd stbcix and lwzcix to power_enum list
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 14:02:53 +0000 (15:02 +0100)]
add stbcix and lwzcix to power_enum list

13 months agoadd simple GPIO peripheral to verilog TestIssuer
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 13:38:08 +0000 (14:38 +0100)]
add simple GPIO peripheral to verilog TestIssuer

13 months agomove wb read/write to separate util test library and use them
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 13:30:46 +0000 (14:30 +0100)]
move wb read/write to separate util test library and use them

13 months agoadd simple wishbone GPIO peripheral
Luke Kenneth Casson Leighton [Sat, 5 Sep 2020 13:27:30 +0000 (14:27 +0100)]
add simple wishbone GPIO peripheral

13 months agoAdd unit test replicating failing proof case
Samuel A. Falvo II [Sat, 5 Sep 2020 00:23:06 +0000 (17:23 -0700)]
Add unit test replicating failing proof case

13 months agoadd sld test with RB=64 to see what happens
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 23:48:23 +0000 (00:48 +0100)]
add sld test with RB=64 to see what happens

13 months agoreduce CSR data width to 8 as an experiment
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 23:48:08 +0000 (00:48 +0100)]
reduce CSR data width to 8 as an experiment

13 months agoadd UART reserved IRQ @ 0
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 19:56:44 +0000 (20:56 +0100)]
add UART reserved IRQ @ 0

13 months agoadd XICS memory regions, shrink litex CSR memmap size to do it
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 19:48:30 +0000 (20:48 +0100)]
add XICS memory regions, shrink litex CSR memmap size to do it

13 months agoadding XICS wb slave devices to litex sim
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 19:03:02 +0000 (20:03 +0100)]
adding XICS wb slave devices to litex sim
also linking external interrupt line

13 months agobring out XICS ICS interrupt levels so that they can be wired to peripherals
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 15:16:40 +0000 (16:16 +0100)]
bring out XICS ICS interrupt levels so that they can be wired to peripherals

13 months agoadding option to include XICS external interrupts.
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 15:11:10 +0000 (16:11 +0100)]
adding option to include XICS external interrupts.
XICS ICP and ICS are included, the wishbone slave ports added to TestIssuer
then if ext_irq is raised in core, execution jumps to 0x500 through a TRAP

13 months agoadd means to run hello_world.bin under simulation
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 12:01:09 +0000 (13:01 +0100)]
add means to run hello_world.bin under simulation
works with both microwatt and libresoc

13 months agoupdate to match refactored power-instruction-analyzer API
Jacob Lifshay [Fri, 4 Sep 2020 04:32:56 +0000 (21:32 -0700)]
update to match refactored power-instruction-analyzer API

matches the api of power-instruction-analyzer commit e828d2acecc25a82d5c29b765163a10993547566

13 months agoProvide full name and email in copyright notice.
Samuel A. Falvo II [Thu, 3 Sep 2020 22:12:58 +0000 (15:12 -0700)]
Provide full name and email in copyright notice.

13 months agodo more on dcache conversion
Luke Kenneth Casson Leighton [Thu, 3 Sep 2020 19:29:21 +0000 (20:29 +0100)]
do more on dcache conversion

13 months agotesting microwatt 3.bin (2.bin ok)
Luke Kenneth Casson Leighton [Thu, 3 Sep 2020 07:45:23 +0000 (08:45 +0100)]
testing microwatt 3.bin (2.bin ok)

13 months agowhen mtocrf FXM is 0, the CR has to be set to CR7
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 22:08:27 +0000 (23:08 +0100)]
when mtocrf FXM is 0, the CR has to be set to CR7

13 months agofix bug in cmpli (and cmplw)
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 17:48:34 +0000 (18:48 +0100)]
fix bug in cmpli (and cmplw)

13 months agosign-extend lhax needs 16-64, separate from lwax which is 32-64
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 16:48:17 +0000 (17:48 +0100)]
sign-extend lhax needs 16-64, separate from lwax which is 32-64

13 months agoadd bc ctr regression test when CTR=0 and CTR=1
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 16:38:03 +0000 (17:38 +0100)]
add bc ctr regression test when CTR=0 and CTR=1

13 months agoupdate submodule
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 14:13:31 +0000 (15:13 +0100)]
update submodule

13 months agobug in carry32 handling in OP_CMP
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 14:13:22 +0000 (15:13 +0100)]
bug in carry32 handling in OP_CMP

13 months agoadd cmpl regression test (one binary, one assembly)
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 14:13:06 +0000 (15:13 +0100)]
add cmpl regression test (one binary, one assembly)

13 months agoadd cmpl microwatt 1.bin test, cmpl
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 11:44:15 +0000 (12:44 +0100)]
add cmpl microwatt 1.bin test, cmpl

13 months agoseries of extensive modifications to fix long-standing bug in CR handling
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 11:32:38 +0000 (12:32 +0100)]
series of extensive modifications to fix long-standing bug in CR handling
cr as a FieldSelectableInt is being removed

13 months agoadd XER to fastregs and "construct" it in mfspr/mtspr
Luke Kenneth Casson Leighton [Mon, 31 Aug 2020 11:06:24 +0000 (12:06 +0100)]
add XER to fastregs and "construct" it in mfspr/mtspr

13 months agoredo OP_CMP based on microwatt. L=1 had been ignored
Luke Kenneth Casson Leighton [Sun, 30 Aug 2020 19:49:58 +0000 (20:49 +0100)]
redo OP_CMP based on microwatt.  L=1 had been ignored

13 months agoreversal of FXM mask for one-hot selection in OP_MTCR decode
Luke Kenneth Casson Leighton [Sun, 30 Aug 2020 14:45:03 +0000 (15:45 +0100)]
reversal of FXM mask for one-hot selection in OP_MTCR decode

13 months agoworking on dcache.py
Luke Kenneth Casson Leighton [Sun, 30 Aug 2020 12:05:36 +0000 (13:05 +0100)]
working on dcache.py

13 months agotidyup on mul proof
Luke Kenneth Casson Leighton [Sun, 30 Aug 2020 10:00:37 +0000 (11:00 +0100)]
tidyup on mul proof

13 months agoset mul post_stage o.ok only when needed, and fix xer_so pass-through
Luke Kenneth Casson Leighton [Sun, 30 Aug 2020 09:51:30 +0000 (10:51 +0100)]
set mul post_stage o.ok only when needed, and fix xer_so pass-through
https://bugs.libre-soc.org/show_bug.cgi?id=482

13 months agoMerge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Sun, 30 Aug 2020 03:24:22 +0000 (20:24 -0700)]
Merge branch 'master' of git.libre-soc.org:soc

13 months agoicache.py commit progress, about a third through the process
Cole Poirier [Sun, 30 Aug 2020 03:23:18 +0000 (20:23 -0700)]
icache.py commit progress, about a third through the process

13 months agoQualify XER_OV output in proof
Samuel A. Falvo II [Sat, 29 Aug 2020 23:53:49 +0000 (16:53 -0700)]
Qualify XER_OV output in proof

13 months agoFix test breakage in MUL proofs
Samuel A. Falvo II [Sat, 29 Aug 2020 23:27:54 +0000 (16:27 -0700)]
Fix test breakage in MUL proofs

13 months agoMerge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Sat, 29 Aug 2020 22:58:31 +0000 (15:58 -0700)]
Merge branch 'master' of git.libre-soc.org:soc

13 months agommu.py, dcache.py, mem_types.py change types capitalization because I
Cole Poirier [Sat, 29 Aug 2020 22:56:15 +0000 (15:56 -0700)]
mmu.py, dcache.py, mem_types.py change types capitalization because I
was making typing errors, and this make more sense. Mmu -> MMU, Dcache
-> DCache, Icache -> ICache

13 months agomem_types add more types from common.vhdl specifially for icache,
Cole Poirier [Sat, 29 Aug 2020 22:41:07 +0000 (15:41 -0700)]
mem_types add more types from common.vhdl specifially for icache,
Fetch1ToIcacheType() and IcacheToDecode1Type()

13 months agomem_types.py arrange in alphabetical order for ease of reference, align
Cole Poirier [Sat, 29 Aug 2020 22:32:38 +0000 (15:32 -0700)]
mem_types.py arrange in alphabetical order for ease of reference, align
formatting

13 months agoBROKEN: xer_ov_o != dut.o.xer_ov.data ???!!!
Samuel A. Falvo II [Sat, 29 Aug 2020 22:24:15 +0000 (15:24 -0700)]
BROKEN: xer_ov_o != dut.o.xer_ov.data ???!!!

13 months agommu.py remove duplicate comment left over from mmu.vhdl
Cole Poirier [Sat, 29 Aug 2020 22:06:01 +0000 (15:06 -0700)]
mmu.py remove duplicate comment left over from mmu.vhdl

13 months agoicache.py initial commit of first attempt at translation of icache.vhdl
Cole Poirier [Sat, 29 Aug 2020 22:02:56 +0000 (15:02 -0700)]
icache.py initial commit of first attempt at translation of icache.vhdl

13 months agoMove new write_gtkw and its example to nmutil
Cesar Strauss [Fri, 28 Aug 2020 09:55:10 +0000 (06:55 -0300)]
Move new write_gtkw and its example to nmutil

But keep using it to generate the GTKWave document for this unit test.

13 months agominor code-shuffle, comments
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 19:56:29 +0000 (20:56 +0100)]
minor code-shuffle, comments

13 months agoslowly morphing towards using an XER bit-field selector in decoder
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 19:42:35 +0000 (20:42 +0100)]
slowly morphing towards using an XER bit-field selector in decoder

13 months agoMUL pipeline formal proofs complete, I *think*.
Samuel A. Falvo II [Sat, 29 Aug 2020 19:41:30 +0000 (12:41 -0700)]
MUL pipeline formal proofs complete, I *think*.