soc.git
15 months agoadd "respect_pc" boolean to ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 13:20:06 +0000 (14:20 +0100)]
add "respect_pc" boolean to ISACaller

15 months agoadd optional instruction memory
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 13:07:59 +0000 (14:07 +0100)]
add optional instruction memory

15 months agosplit out TestIssuer into separate module
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 11:17:31 +0000 (12:17 +0100)]
split out TestIssuer into separate module

15 months agoremove unneeded yield
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 11:08:08 +0000 (12:08 +0100)]
remove unneeded yield

15 months agoenable all tests again in test_core.py and test_issuer.py
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 05:41:09 +0000 (06:41 +0100)]
enable all tests again in test_core.py and test_issuer.py

15 months agogot test_issuer FSM operating. bit of a hack
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 05:39:53 +0000 (06:39 +0100)]
got test_issuer FSM operating.  bit of a hack

15 months agodebugging test_issuer, getting FSM working
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 04:42:10 +0000 (05:42 +0100)]
debugging test_issuer, getting FSM working

15 months agooutput to issuer_simulator.vcd
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 04:14:40 +0000 (05:14 +0100)]
output to issuer_simulator.vcd

15 months agoadd first version unit test for TestIssuer
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 18:33:05 +0000 (19:33 +0100)]
add first version unit test for TestIssuer

15 months agoreduce instruction depth to 6 bits in TestIssuer
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 18:32:46 +0000 (19:32 +0100)]
reduce instruction depth to 6 bits in TestIssuer

15 months agomove debug statements to check function
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 18:21:20 +0000 (19:21 +0100)]
move debug statements to check function

15 months agohack LD/ST ad/st together, allow PC to be set externally
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 18:12:01 +0000 (19:12 +0100)]
hack LD/ST ad/st together, allow PC to be set externally

15 months agomove check regs in simple core to separate function
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 17:29:37 +0000 (18:29 +0100)]
move check regs in simple core to separate function

15 months agomove test core reg set up into separate function
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 17:24:43 +0000 (18:24 +0100)]
move test core reg set up into separate function

15 months agoset up a TestIssuer class with a FSM for doing instruction issue to simple core
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 17:18:20 +0000 (18:18 +0100)]
set up a TestIssuer class with a FSM for doing instruction issue to simple core

15 months agoadd ports to TestMemory
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 17:16:53 +0000 (18:16 +0100)]
add ports to TestMemory

15 months agoadd beginnings of TestIssuer class, to issue instructions to simple core
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 14:39:03 +0000 (15:39 +0100)]
add beginnings of TestIssuer class, to issue instructions to simple core

16 months agoweird: adding TestMemory with no port causes nmigen recursion-exceeded
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 13:00:12 +0000 (14:00 +0100)]
weird: adding TestMemory with no port causes nmigen recursion-exceeded

16 months agorefer to signals directly in Test Core
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 12:57:41 +0000 (13:57 +0100)]
refer to signals directly in Test Core

16 months agoadd test instruction memory SRAM
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 12:41:17 +0000 (13:41 +0100)]
add test instruction memory SRAM

16 months agoupdate popcount docstring
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 11:15:42 +0000 (12:15 +0100)]
update popcount docstring

16 months agostart trying to fill in some comments in Minerva L1 cache code
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 23:52:30 +0000 (00:52 +0100)]
start trying to fill in some comments in Minerva L1 cache code

16 months agowhitespace cleanup
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 20:56:24 +0000 (21:56 +0100)]
whitespace cleanup

16 months agoimports and syntax errors fixed (found test_cache.py)
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 20:55:39 +0000 (21:55 +0100)]
imports and syntax errors fixed (found test_cache.py)

16 months agomore whitespace
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 19:53:43 +0000 (20:53 +0100)]
more whitespace

16 months agomore whitespace on minerva (no unit tests, so cannot check it)
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 19:51:56 +0000 (20:51 +0100)]
more whitespace on minerva (no unit tests, so cannot check it)

16 months agowhitespace cleanup, remove minerva DataSelector class
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 19:46:25 +0000 (20:46 +0100)]
whitespace cleanup, remove minerva DataSelector class

16 months agohave to set up addr/st rel-go link before setting up nmigen Simulator
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 19:05:32 +0000 (20:05 +0100)]
have to set up addr/st rel-go link before setting up nmigen Simulator
LD/ST now works in test_core.py

16 months agoadd in memory setup/check but disable LDST Unit Tests in core.py
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 14:54:49 +0000 (15:54 +0100)]
add in memory setup/check but disable LDST Unit Tests in core.py
LDST is still busy after 2nd instruction, bug needs tracking down

16 months agomove setup/check memory into helper functions for use in test_core.py
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 14:40:36 +0000 (15:40 +0100)]
move setup/check memory into helper functions for use in test_core.py

16 months agowhoops LDSTCompUnit was identified as a Function.ALU not a Function.LDST
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 14:33:35 +0000 (15:33 +0100)]
whoops LDSTCompUnit was identified as a Function.ALU not a Function.LDST

16 months agoadd in TstL0CacheBuffer but disable temporarily
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 14:26:05 +0000 (15:26 +0100)]
add in TstL0CacheBuffer but disable temporarily

16 months agoadd optional LDSTFunctionUnit to compunits
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 20:22:04 +0000 (21:22 +0100)]
add optional LDSTFunctionUnit to compunits

16 months agounit tests showing byte-reverse works
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 17:08:23 +0000 (18:08 +0100)]
unit tests showing byte-reverse works

16 months agoadd sim-qemu test for byte-reversed LD/ST
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 16:51:17 +0000 (17:51 +0100)]
add sim-qemu test for byte-reversed LD/ST

16 months agoadd in byte-reverse from op PowerDecode2 field
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 16:40:20 +0000 (17:40 +0100)]
add in byte-reverse from op PowerDecode2 field

16 months agoerror in address width (truncated) in setting up L0CacheBuffer
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 14:50:35 +0000 (15:50 +0100)]
error in address width (truncated) in setting up L0CacheBuffer

16 months agoerror in naming that ended up in gtkwave from a proxy
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 14:49:27 +0000 (15:49 +0100)]
error in naming that ended up in gtkwave from a proxy

16 months agoadd another LD/ST example to qemu-sim test,
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 14:37:30 +0000 (15:37 +0100)]
add another LD/ST example to qemu-sim test,
mirroring the one in ldst compunit test

16 months agoadd byte-reversal on LD and ST in L0CacheBuffer
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 14:36:57 +0000 (15:36 +0100)]
add byte-reversal on LD and ST in L0CacheBuffer

16 months agoreasonably certain that the careful and slow use of little-endian data read/write
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 14:00:12 +0000 (15:00 +0100)]
reasonably certain that the careful and slow use of little-endian data read/write
and explicit endian-ness swapping is correct, when comparing the
simulator against qemu

16 months agoWait for all active rel signals to be high, and only then pulse go.
Cesar Strauss [Sat, 13 Jun 2020 23:51:14 +0000 (20:51 -0300)]
Wait for all active rel signals to be high, and only then pulse go.

It's the best we can do without parallel processes.

16 months agofirst cut at qemu memory dump and compare
Luke Kenneth Casson Leighton [Fri, 12 Jun 2020 18:44:09 +0000 (19:44 +0100)]
first cut at qemu memory dump and compare

16 months agonote possible BE/LE mode needed for memory reads/writes
Luke Kenneth Casson Leighton [Fri, 12 Jun 2020 15:28:32 +0000 (16:28 +0100)]
note possible BE/LE mode needed for memory reads/writes

16 months agoupdate ld/st test to see what is going on
Luke Kenneth Casson Leighton [Fri, 12 Jun 2020 14:58:21 +0000 (15:58 +0100)]
update ld/st test to see what is going on

16 months agotracking down what looks like an error in the Simulator Mem ld/st
Luke Kenneth Casson Leighton [Fri, 12 Jun 2020 14:41:16 +0000 (15:41 +0100)]
tracking down what looks like an error in the Simulator Mem ld/st

16 months agodebug printout of sim and hardware memory, shows mismatch of depths
Luke Kenneth Casson Leighton [Fri, 12 Jun 2020 14:03:10 +0000 (15:03 +0100)]
debug printout of sim and hardware memory, shows mismatch of depths

16 months agouse ALUHelpers in LDSTCompUnit test
Luke Kenneth Casson Leighton [Fri, 12 Jun 2020 13:46:25 +0000 (14:46 +0100)]
use ALUHelpers in LDSTCompUnit test

16 months agosome ugly hacks that get LD/ST immediate working
Luke Kenneth Casson Leighton [Thu, 11 Jun 2020 19:03:30 +0000 (20:03 +0100)]
some ugly hacks that get LD/ST immediate working

16 months agoeven more complexity in CompALUMulti, to deal with an edge case where
Luke Kenneth Casson Leighton [Thu, 11 Jun 2020 14:29:41 +0000 (15:29 +0100)]
even more complexity in CompALUMulti, to deal with an edge case where
go-write is requested immediately (same cycle as go-req).
the set and reset on "req_l" happen to come in on the same cycle.
the result: the latch *remains* set high.
solution: record the go signals for one extra cycle (sync) and push
them into the req-reset and wr_any signals

16 months agomust distinguish between rd/write xer_ca sim helpers
Luke Kenneth Casson Leighton [Thu, 11 Jun 2020 10:54:27 +0000 (11:54 +0100)]
must distinguish between rd/write xer_ca sim helpers

16 months agofixing get_rd_sim_xer_ca, has to only read carry if available
Luke Kenneth Casson Leighton [Thu, 11 Jun 2020 10:53:21 +0000 (11:53 +0100)]
fixing get_rd_sim_xer_ca, has to only read carry if available

16 months agoyield needed for unit tests to work (has to go)
Luke Kenneth Casson Leighton [Thu, 11 Jun 2020 10:53:00 +0000 (11:53 +0100)]
yield needed for unit tests to work (has to go)

16 months agoread and write version of get_sim_xer_ca are different
Luke Kenneth Casson Leighton [Thu, 11 Jun 2020 10:31:05 +0000 (11:31 +0100)]
read and write version of get_sim_xer_ca are different

16 months agouse ALUHelpers in shift_rot
Luke Kenneth Casson Leighton [Thu, 11 Jun 2020 10:23:10 +0000 (11:23 +0100)]
use ALUHelpers in shift_rot

16 months agoadd fast spr1/2 sim ALUHelpers
Luke Kenneth Casson Leighton [Thu, 11 Jun 2020 06:14:49 +0000 (07:14 +0100)]
add fast spr1/2 sim ALUHelpers

16 months agorename get_sim_cr_a to get_wr_sim_cr_a for now
Luke Kenneth Casson Leighton [Thu, 11 Jun 2020 06:10:27 +0000 (07:10 +0100)]
rename get_sim_cr_a to get_wr_sim_cr_a for now
add read-version of get_sim_cr_a

16 months agomove Decode2ToExecute1Type to separate module
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 23:56:58 +0000 (00:56 +0100)]
move Decode2ToExecute1Type to separate module

16 months agowhitespace
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 23:48:01 +0000 (00:48 +0100)]
whitespace

16 months agomodify qemu.py to set qemu's cr to 0
Michael Nolan [Wed, 10 Jun 2020 19:28:30 +0000 (15:28 -0400)]
modify qemu.py to set qemu's cr to 0

16 months agolink ST.go directly to ST.rel
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 16:41:35 +0000 (17:41 +0100)]
link ST.go directly to ST.rel

16 months agorename unit test function in ld/st compalu_multi
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 16:38:58 +0000 (17:38 +0100)]
rename unit test function in ld/st compalu_multi

16 months agohmmm very confused about LD/ST CompUnit unit test
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 16:35:13 +0000 (17:35 +0100)]
hmmm very confused about LD/ST CompUnit unit test

16 months agowrong data structure being imported, duplicate CompLDSTOpSubset
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 16:26:47 +0000 (17:26 +0100)]
wrong data structure being imported, duplicate CompLDSTOpSubset

16 months agoremove old code
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 16:23:40 +0000 (17:23 +0100)]
remove old code

16 months agoset data_len in compldst_multi unit test
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 16:11:25 +0000 (17:11 +0100)]
set data_len in compldst_multi unit test

16 months agoyield ports from data_o and addr_o
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 16:09:46 +0000 (17:09 +0100)]
yield ports from data_o and addr_o

16 months agoexpand LenExpand to 4 bits in order to cover 1/2/4/8 (0b1000)
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 16:04:33 +0000 (17:04 +0100)]
expand LenExpand to 4 bits in order to cover 1/2/4/8 (0b1000)

16 months agogot L0CacheBuffer shift/mask working on a preliminary level
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 15:43:29 +0000 (16:43 +0100)]
got L0CacheBuffer shift/mask working on a preliminary level

16 months agowhitespace
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 14:51:48 +0000 (15:51 +0100)]
whitespace

16 months agoadd use of classes in L0Cache unit tests
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 14:50:26 +0000 (15:50 +0100)]
add use of classes in L0Cache unit tests

16 months agostart using unittest suite in l0_cache.py
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 14:44:03 +0000 (15:44 +0100)]
start using unittest suite in l0_cache.py

16 months agocreates an import error and stops unit tests from running
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 14:39:13 +0000 (15:39 +0100)]
creates an import error and stops unit tests from running

Revert "PortInterface refactoring"

This reverts commit 8e58e66142991e308985a463cfff396a36e3f816.

16 months agoadd in LenExpander to L0CacheBuffer, not used yet
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 14:36:56 +0000 (15:36 +0100)]
add in LenExpander to L0CacheBuffer, not used yet

16 months agomake resetless for all signals in DataMergerRecord
Tobias Platen [Wed, 10 Jun 2020 14:38:24 +0000 (16:38 +0200)]
make resetless for all signals in DataMergerRecord

16 months agoPortInterface refactoring
Tobias Platen [Wed, 10 Jun 2020 14:28:04 +0000 (16:28 +0200)]
PortInterface refactoring

16 months agoexception if rolls in addr_split.py
Tobias Platen [Wed, 10 Jun 2020 13:57:02 +0000 (15:57 +0200)]
exception if rolls in addr_split.py

16 months agoadd link to bug 361 in FU test
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 13:27:05 +0000 (14:27 +0100)]
add link to bug 361 in FU test

16 months agoTODO on RA immediate-zero mode
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 13:25:27 +0000 (14:25 +0100)]
TODO on RA immediate-zero mode

16 months agore-do cookie-cut of alu test_pipe_caller.py over to div. again
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 13:20:27 +0000 (14:20 +0100)]
re-do cookie-cut of alu test_pipe_caller.py over to div. again

16 months agouse ALUHelpers in output stage of test_pipe_caller
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 13:08:16 +0000 (14:08 +0100)]
use ALUHelpers in output stage of test_pipe_caller

16 months agouse sim-get helpers in ALU input fetch
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 13:03:39 +0000 (14:03 +0100)]
use sim-get helpers in ALU input fetch

16 months agouse ALUHelpers in output phase of test_alu_compunit.py
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 12:55:40 +0000 (13:55 +0100)]
use ALUHelpers in output phase of test_alu_compunit.py

16 months agocontinue ALUHelpers check alu outputs code-morph
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 12:54:24 +0000 (13:54 +0100)]
continue ALUHelpers check alu outputs code-morph

16 months agocode-morph ALU output test check phase
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 12:33:19 +0000 (13:33 +0100)]
code-morph ALU output test check phase

16 months agocode-morph regspecmap functions, split into separate read/write
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 12:18:08 +0000 (13:18 +0100)]
code-morph regspecmap functions, split into separate read/write

16 months agostarting on alu output check
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 12:09:45 +0000 (13:09 +0100)]
starting on alu output check

16 months agoilang file output change from alu_pipeline.il to div_pipeline.il
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 11:33:38 +0000 (12:33 +0100)]
ilang file output change from alu_pipeline.il to div_pipeline.il

16 months agocookie-cut alu test_pipe_caller.py over
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 11:31:54 +0000 (12:31 +0100)]
cookie-cut alu test_pipe_caller.py over

16 months agomove to common ALUHelpers for ShiftRot test_pipe_caller.py
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 11:25:48 +0000 (12:25 +0100)]
move to common ALUHelpers for ShiftRot test_pipe_caller.py

16 months agomove to common ALUHelpers for Logical test_pipe_caller.py
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 11:21:43 +0000 (12:21 +0100)]
move to common ALUHelpers for Logical test_pipe_caller.py

16 months agomove to common ALUHelpers for CR test_pipe_caller.py
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 11:20:17 +0000 (12:20 +0100)]
move to common ALUHelpers for CR test_pipe_caller.py

16 months agomove to common ALUHelpers for branch test_pipe_caller.py
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 11:13:27 +0000 (12:13 +0100)]
move to common ALUHelpers for branch test_pipe_caller.py

16 months agocode-munge test_pipe_caller for ALU,
Luke Kenneth Casson Leighton [Wed, 10 Jun 2020 11:09:20 +0000 (12:09 +0100)]
code-munge test_pipe_caller for ALU,
plan to remove duplicated code

16 months agocreate div pipe setup stage
Jacob Lifshay [Wed, 10 Jun 2020 06:53:06 +0000 (23:53 -0700)]
create div pipe setup stage

16 months agoKeep the sequencer in the "done" state until ready_i is asserted
Cesar Strauss [Tue, 9 Jun 2020 22:45:05 +0000 (19:45 -0300)]
Keep the sequencer in the "done" state until ready_i is asserted

Generate valid_o from the "done" state.

16 months agoexperimenting with CR/LR/XER etc in qemu
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 22:38:39 +0000 (23:38 +0100)]
experimenting with CR/LR/XER etc in qemu

16 months agoadd means to get pc and other qemu registers
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 22:12:58 +0000 (23:12 +0100)]
add means to get pc and other qemu registers

16 months agorename truncaddr to splitaddr, return LSBs and MSBs
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 17:53:35 +0000 (18:53 +0100)]
rename truncaddr to splitaddr, return LSBs and MSBs

16 months agoadd len-expander to L0CacheBuffer, so as to be able to mask the LD/ST data
Luke Kenneth Casson Leighton [Tue, 9 Jun 2020 17:53:09 +0000 (18:53 +0100)]
add len-expander to L0CacheBuffer, so as to be able to mask the LD/ST data