soc.git
15 months agoadd halted condition in ISACaller, when attn instruction encountered
Luke Kenneth Casson Leighton [Tue, 7 Jul 2020 14:42:52 +0000 (15:42 +0100)]
add halted condition in ISACaller, when attn instruction encountered

15 months agodebugging termination / OP_ATTN
Luke Kenneth Casson Leighton [Tue, 7 Jul 2020 14:27:50 +0000 (15:27 +0100)]
debugging termination / OP_ATTN

15 months agoadd ATTN unit test
Luke Kenneth Casson Leighton [Tue, 7 Jul 2020 13:15:56 +0000 (14:15 +0100)]
add ATTN unit test

15 months agoadd core start/stop capability, and OP_ATTN support
Luke Kenneth Casson Leighton [Tue, 7 Jul 2020 13:14:46 +0000 (14:14 +0100)]
add core start/stop capability, and OP_ATTN support

15 months agoadd in SPR test cases into test_issuer.py
Luke Kenneth Casson Leighton [Tue, 7 Jul 2020 12:42:20 +0000 (13:42 +0100)]
add in SPR test cases into test_issuer.py

15 months agouse ComMULOpSubset in mul pipeline
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 22:28:38 +0000 (23:28 +0100)]
use ComMULOpSubset in mul pipeline

15 months agoremove alu unneeded op record data
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 22:26:56 +0000 (23:26 +0100)]
remove alu unneeded op record data

15 months agoremove alu unneeded op record data
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 22:23:51 +0000 (23:23 +0100)]
remove alu unneeded op record data

15 months agoremove alu unneeded op record data
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 22:22:45 +0000 (23:22 +0100)]
remove alu unneeded op record data

15 months agoadd mul unit to test_issuer
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 22:15:55 +0000 (23:15 +0100)]
add mul unit to test_issuer

15 months agoadd mul compunit
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 22:13:00 +0000 (23:13 +0100)]
add mul compunit

15 months agowhoops forgot that the mul pipeline is actually a pipeline (3 stage, first one)
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 22:08:53 +0000 (23:08 +0100)]
whoops forgot that the mul pipeline is actually a pipeline (3 stage, first one)

15 months agodo abs slightly differently in SelectableInt
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 19:48:26 +0000 (20:48 +0100)]
do abs slightly differently in SelectableInt

15 months agocontinue mul unit test debugging
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 19:43:48 +0000 (20:43 +0100)]
continue mul unit test debugging

15 months agoadd MULS (signed) version of multiply
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 19:19:58 +0000 (20:19 +0100)]
add MULS (signed) version of multiply

15 months agoimprove debug for test_sim.py
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 19:19:48 +0000 (20:19 +0100)]
improve debug for test_sim.py

15 months agoadd mullw test to qemu sim
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 19:19:26 +0000 (20:19 +0100)]
add mullw test to qemu sim

15 months agofix SelectableInt abs
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 19:19:06 +0000 (20:19 +0100)]
fix SelectableInt abs

15 months agoadd first simulator mul test
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 18:56:33 +0000 (19:56 +0100)]
add first simulator mul test

15 months agoinvestigating mul pipeline
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 18:49:49 +0000 (19:49 +0100)]
investigating mul pipeline

15 months agoSelectableInt: make __mul__ return enough space to fit the result
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 18:44:58 +0000 (19:44 +0100)]
SelectableInt: make __mul__ return enough space to fit the result

15 months agofirst cut at mul test pipeline
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 16:02:09 +0000 (17:02 +0100)]
first cut at mul test pipeline

15 months agoadd first cut at fu mul pipeline
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 15:34:31 +0000 (16:34 +0100)]
add first cut at fu mul pipeline

15 months agoadding mtspr tests
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 13:12:12 +0000 (14:12 +0100)]
adding mtspr tests

15 months agoadding OP_MTMSR test
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 13:11:47 +0000 (14:11 +0100)]
adding OP_MTMSR test

15 months agoadd mtmsr internal op
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 13:11:09 +0000 (14:11 +0100)]
add mtmsr internal op

15 months agoadd mtmsr internal op
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 13:10:59 +0000 (14:10 +0100)]
add mtmsr internal op

15 months agosort out initialisation of TstL0CacheBuffer in ldst compunit test
Luke Kenneth Casson Leighton [Mon, 6 Jul 2020 13:08:04 +0000 (14:08 +0100)]
sort out initialisation of TstL0CacheBuffer in ldst compunit test

15 months agoAssert n.ready_i at the beginning of the cycle
Cesar Strauss [Mon, 6 Jul 2020 11:12:59 +0000 (08:12 -0300)]
Assert n.ready_i at the beginning of the cycle

This simulates the common case where we are ready for the
result as soon as the ALU delivers it.
The special case for the zero-delay operation is no longer
needed.

15 months agoRemove wait state to demonstrate zero-delay reception.
Cesar Strauss [Mon, 6 Jul 2020 10:56:51 +0000 (07:56 -0300)]
Remove wait state to demonstrate zero-delay reception.

15 months agoSimplify waiting loops
Cesar Strauss [Mon, 6 Jul 2020 10:49:05 +0000 (07:49 -0300)]
Simplify waiting loops

15 months agoFinally add some well needed comments
Cesar Strauss [Mon, 6 Jul 2020 09:44:24 +0000 (06:44 -0300)]
Finally add some well needed comments

15 months agoSimplify waiting loops
Cesar Strauss [Mon, 6 Jul 2020 08:53:57 +0000 (05:53 -0300)]
Simplify waiting loops

15 months agoAdd some wait states in each process
Cesar Strauss [Sun, 5 Jul 2020 22:57:14 +0000 (19:57 -0300)]
Add some wait states in each process

15 months agoNegate inputs after use
Cesar Strauss [Sun, 5 Jul 2020 22:46:03 +0000 (19:46 -0300)]
Negate inputs after use

15 months agoAdd other tests
Cesar Strauss [Sun, 5 Jul 2020 22:44:00 +0000 (19:44 -0300)]
Add other tests

15 months agoImplement receiver
Cesar Strauss [Sun, 5 Jul 2020 22:30:45 +0000 (19:30 -0300)]
Implement receiver

15 months agoImplement sender.
Cesar Strauss [Sun, 5 Jul 2020 22:13:26 +0000 (19:13 -0300)]
Implement sender.

15 months agoBegin a new parallel test
Cesar Strauss [Sat, 4 Jul 2020 14:45:36 +0000 (11:45 -0300)]
Begin a new parallel test

The purpose of this test is really to better develop a
parallel test concept, by testing against a simple
target.

15 months agoadd mtmsr tests (fail)
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 21:32:56 +0000 (22:32 +0100)]
add mtmsr tests (fail)

15 months agocheck trap compunit output properly
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 21:18:34 +0000 (22:18 +0100)]
check trap compunit output properly

15 months agocheck msr in trap test, fix OP_RFID
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 21:17:13 +0000 (22:17 +0100)]
check msr in trap test, fix OP_RFID

15 months agoadd an illegal instruction trap test
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 20:54:58 +0000 (21:54 +0100)]
add an illegal instruction trap test

15 months agoset up a trap function for microcode override
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 20:54:42 +0000 (21:54 +0100)]
set up a trap function for microcode override

15 months agobig reorg on PowerDecoder2, actually Decode2Execute1Type
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 15:40:30 +0000 (16:40 +0100)]
big reorg on PowerDecoder2, actually Decode2Execute1Type
plan is to move the decoding of instruction fields closer to the
CompUnits

15 months agostop debug output in power_decoder
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 15:29:35 +0000 (16:29 +0100)]
stop debug output in power_decoder

15 months agocomments in power_regspec_map.py
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 14:36:18 +0000 (15:36 +0100)]
comments in power_regspec_map.py

15 months agocomment on spr2, not needed
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 14:30:58 +0000 (15:30 +0100)]
comment on spr2, not needed

15 months agocheck xer_out not xer_in
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 14:29:27 +0000 (15:29 +0100)]
check xer_out not xer_in

15 months agosplit out Decode2ToExecuteType fields involving registers
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 14:27:23 +0000 (15:27 +0100)]
split out Decode2ToExecuteType fields involving registers
into constants Decode2ToOperand

15 months agosigh read and write xer detection, fix spr and trap compunit tests
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 14:16:13 +0000 (15:16 +0100)]
sigh read and write xer detection, fix spr and trap compunit tests

15 months agocheck spr1 in test spr compunit
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 12:56:44 +0000 (13:56 +0100)]
check spr1 in test spr compunit

15 months agoget/set slow spr in spr test_pipe_caller
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 12:52:38 +0000 (13:52 +0100)]
get/set slow spr in spr test_pipe_caller

15 months agoadd first spr compunit test (not working yet)
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 12:29:29 +0000 (13:29 +0100)]
add first spr compunit test (not working yet)

15 months agoadd SPR test case, commented out for now
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 12:25:46 +0000 (13:25 +0100)]
add SPR test case, commented out for now

15 months agomove valid signal out of Decode2ToExecute1Type and into PowerDecoder2
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 12:18:03 +0000 (13:18 +0100)]
move valid signal out of Decode2ToExecute1Type and into PowerDecoder2

15 months agoadd slow spr regfile regspec support
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 12:12:28 +0000 (13:12 +0100)]
add slow spr regfile regspec support

15 months agoremap SPR PowerISA numbers to internal SPR enum
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 12:04:22 +0000 (13:04 +0100)]
remap SPR PowerISA numbers to internal SPR enum

15 months agocomment out SPR for now, needs SPR regfile
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 11:22:28 +0000 (12:22 +0100)]
comment out SPR for now, needs SPR regfile

15 months agoadd SPR compunit
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 11:18:10 +0000 (12:18 +0100)]
add SPR compunit

15 months agomissing initialisation of disasm_start
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 11:09:08 +0000 (12:09 +0100)]
missing initialisation of disasm_start

15 months agocheck NIA on trap fu test
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 10:52:20 +0000 (11:52 +0100)]
check NIA on trap fu test

15 months agoOP_RFID needs to read SRR0/1, OP_SC needs to write
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 10:52:09 +0000 (11:52 +0100)]
OP_RFID needs to read SRR0/1, OP_SC needs to write

15 months agofix qemu trap test
Luke Kenneth Casson Leighton [Sun, 5 Jul 2020 10:34:16 +0000 (11:34 +0100)]
fix qemu trap test

15 months agocater for illegal instruction (generates a trap)
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 23:52:35 +0000 (00:52 +0100)]
cater for illegal instruction (generates a trap)

15 months agoadd sc back in
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 21:35:19 +0000 (22:35 +0100)]
add sc back in

15 months agocomments in trap about exceptions using microcoding
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 21:32:38 +0000 (22:32 +0100)]
comments in trap about exceptions using microcoding

15 months agoadd pspec to test_core.py
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 20:01:34 +0000 (21:01 +0100)]
add pspec to test_core.py

15 months agoadd pspec to test_core.py
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 20:01:04 +0000 (21:01 +0100)]
add pspec to test_core.py

15 months agomore rename spr1/spr2 to fast1/fast2
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 19:56:29 +0000 (20:56 +0100)]
more rename spr1/spr2 to fast1/fast2

15 months agowhitespace
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 19:49:50 +0000 (20:49 +0100)]
whitespace

15 months agomore updating spr1/spr2 to fast1/fast2
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 19:45:45 +0000 (20:45 +0100)]
more updating spr1/spr2 to fast1/fast2

15 months agomore updating spr1/spr2 to fast1/fast2
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 19:44:50 +0000 (20:44 +0100)]
more updating spr1/spr2 to fast1/fast2

15 months agorename spr1/spr2 to fast1/fast2 in branch
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 19:41:00 +0000 (20:41 +0100)]
rename spr1/spr2 to fast1/fast2 in branch

15 months agoupdate trap docstring
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 18:18:05 +0000 (19:18 +0100)]
update trap docstring

15 months agouse new consts module
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 18:01:05 +0000 (19:01 +0100)]
use new consts module

15 months agosorting out trap fastregs
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 17:44:23 +0000 (18:44 +0100)]
sorting out trap fastregs

15 months agosort out trap test reg checking
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 17:14:03 +0000 (18:14 +0100)]
sort out trap test reg checking

15 months agoresolve spr names in ISACaller
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 16:59:52 +0000 (17:59 +0100)]
resolve spr names in ISACaller

15 months agorename spr1 to fast1 in trap data
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 16:52:44 +0000 (17:52 +0100)]
rename spr1 to fast1 in trap data

15 months agosorting out fast/spr naming
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 16:52:20 +0000 (17:52 +0100)]
sorting out fast/spr naming

15 months agooops initialise Function Unit class with idx
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 14:08:52 +0000 (15:08 +0100)]
oops initialise Function Unit class with idx

15 months agoadd first cookie-cut test_trap_compunit.py
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 14:07:39 +0000 (15:07 +0100)]
add first cookie-cut test_trap_compunit.py

15 months agoadd gitignores
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 14:07:19 +0000 (15:07 +0100)]
add gitignores

15 months agodebugging decoding of SPRs (fast)
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 14:04:18 +0000 (15:04 +0100)]
debugging decoding of SPRs (fast)

15 months agoadd spr test, add decode of spr in/out
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 13:19:38 +0000 (14:19 +0100)]
add spr test, add decode of spr in/out

15 months agoadd spr main stage
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 12:22:09 +0000 (13:22 +0100)]
add spr main stage

15 months agoadd spr input record
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 11:59:19 +0000 (12:59 +0100)]
add spr input record

15 months agoadd SPR pipeline
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 11:56:42 +0000 (12:56 +0100)]
add SPR pipeline

15 months agoreduce steps per stage to 8
Luke Kenneth Casson Leighton [Sat, 4 Jul 2020 09:50:31 +0000 (10:50 +0100)]
reduce steps per stage to 8

15 months agoset only div/rem supported
Luke Kenneth Casson Leighton [Fri, 3 Jul 2020 03:12:34 +0000 (04:12 +0100)]
set only div/rem supported

15 months agoallow flexible selection of the types of ALUs
Luke Kenneth Casson Leighton [Thu, 2 Jul 2020 23:22:00 +0000 (00:22 +0100)]
allow flexible selection of the types of ALUs

15 months agofix unit tests due to change in using pspec
Luke Kenneth Casson Leighton [Thu, 2 Jul 2020 23:10:10 +0000 (00:10 +0100)]
fix unit tests due to change in using pspec

15 months agouse Mock class (more convenient)
Luke Kenneth Casson Leighton [Thu, 2 Jul 2020 23:09:47 +0000 (00:09 +0100)]
use Mock class (more convenient)

15 months agoallow ALU names to propagate through from FU to CompUnit ALU
Luke Kenneth Casson Leighton [Thu, 2 Jul 2020 21:52:52 +0000 (22:52 +0100)]
allow ALU names to propagate through from FU to CompUnit ALU

15 months agoname function unit ALUs
Luke Kenneth Casson Leighton [Thu, 2 Jul 2020 21:37:21 +0000 (22:37 +0100)]
name function unit ALUs

15 months agocomment out DIV unit for now
Luke Kenneth Casson Leighton [Thu, 2 Jul 2020 19:58:27 +0000 (20:58 +0100)]
comment out DIV unit for now

15 months agoincrease combinatorial stages to 8
Luke Kenneth Casson Leighton [Thu, 2 Jul 2020 19:22:32 +0000 (20:22 +0100)]
increase combinatorial stages to 8

15 months agoreduce DIV radix to 1
Luke Kenneth Casson Leighton [Thu, 2 Jul 2020 19:17:07 +0000 (20:17 +0100)]
reduce DIV radix to 1

15 months agoadd DIV function unit to compunits
Luke Kenneth Casson Leighton [Thu, 2 Jul 2020 18:28:10 +0000 (19:28 +0100)]
add DIV function unit to compunits