soc.git
16 months agotoo much debug info going past, so add the test registers to the
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:42:04 +0000 (14:42 +0100)]
too much debug info going past, so add the test registers to the
failed log message

16 months agomissed import
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:34:06 +0000 (14:34 +0100)]
missed import

16 months agocalling the test dictionary from the constructor is effectively
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:33:08 +0000 (14:33 +0100)]
calling the test dictionary from the constructor is effectively
what unittest does.  this results in multiple copies of the test
being called (once by the dictionary-loop, once by unittest infrastructure)

getting the name of the actual test is a good thing.  used inspect.stack()
to find the name of the calling test

16 months agowhoops spelling
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:29:13 +0000 (14:29 +0100)]
whoops spelling

16 months agoadd the div pipe kind plus prog.assembly to the assert debug output
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:06:48 +0000 (14:06 +0100)]
add the div pipe kind plus prog.assembly to the assert debug output

16 months agocall test_write_ilang only once - ends up being called 9 times otherwise
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:05:53 +0000 (14:05 +0100)]
call test_write_ilang only once - ends up being called 9 times otherwise

16 months agofix how long div tests run, de-comment FSM and DivPipeCore
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 12:59:29 +0000 (13:59 +0100)]
fix how long div tests run, de-comment FSM and DivPipeCore

16 months agoargh! work-in-progress breaking / fixing how to do div unit tests
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 12:56:25 +0000 (13:56 +0100)]
argh!  work-in-progress breaking / fixing how to do div unit tests

16 months agowhoops must add DivTestCasesLong to get it to produce test_data
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 12:23:17 +0000 (13:23 +0100)]
whoops must add DivTestCasesLong to get it to produce test_data

16 months agoremove bad hack calling trunc_divs/trunc_mods
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 12:19:17 +0000 (13:19 +0100)]
remove bad hack calling trunc_divs/trunc_mods
see https://bugs.libre-soc.org/show_bug.cgi?id=436

16 months agore-enable commented-out div unit tests
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 11:52:28 +0000 (12:52 +0100)]
re-enable commented-out div unit tests

16 months agosplit out "all" div into separate unit test (takes a really long time)
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 11:50:07 +0000 (12:50 +0100)]
split out "all" div into separate unit test (takes a really long time)

16 months agoreduce variable size, continuation not needed
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 11:45:27 +0000 (12:45 +0100)]
reduce variable size, continuation not needed

16 months agocomment about timeline does not exist
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 11:43:59 +0000 (12:43 +0100)]
comment about timeline does not exist

16 months agoah ha! not using "with" was not calling the "close" function
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 11:06:08 +0000 (12:06 +0100)]
ah ha!  not using "with" was not calling the "close" function

16 months agoread into a BytesIO to avoid "too many open files"
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 10:54:24 +0000 (11:54 +0100)]
read into a BytesIO to avoid "too many open files"
 see https://bugs.libre-soc.org/show_bug.cgi?id=438

16 months agowhitespace / comments
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 10:46:19 +0000 (11:46 +0100)]
whitespace / comments

16 months agorestore modification to caller.py from reversion of div (use of pia
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 10:35:00 +0000 (11:35 +0100)]
restore modification to caller.py from reversion of div (use of pia
not properly documented)

16 months agoRevert "working on div's test_pipe_caller"
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 10:30:32 +0000 (11:30 +0100)]
Revert "working on div's test_pipe_caller"

This reverts commit 8bf37997d31250126a664aeb3bd67ac0cd72a70c.

the build / install dependencies have not been properly documented,
making it impossible for anyone to install this at the moment.

that in turn makes it impossible for anyone to run:

* the div test_pipe_caller unit test
* the test_issuer.py test
* the test_core.py test
* the compunit test_div_compunit.py test

the modifications to caller.py whilst correct are reverted as a
side-effect due to violation of the development guidelines on
"single purpose commit"

16 months agobug found in pseudocode reader when assembly code has zero args
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 10:14:16 +0000 (11:14 +0100)]
bug found in pseudocode reader when assembly code has zero args

16 months agosubmodule update
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 10:09:14 +0000 (11:09 +0100)]
submodule update
see https://bugs.libre-soc.org/show_bug.cgi?id=439

16 months agocode review comments for trap and proof
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 09:40:32 +0000 (10:40 +0100)]
code review comments for trap and proof

16 months agomade it clear what is meant by the slice numbering being inverted
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 09:25:59 +0000 (10:25 +0100)]
made it clear what is meant by the slice numbering being inverted
see https://bugs.libre-soc.org/show_bug.cgi?id=325#c126

16 months agoRefactorin of common code
Samuel A. Falvo II [Fri, 24 Jul 2020 05:37:28 +0000 (22:37 -0700)]
Refactorin of common code

16 months agoAddress code review comments
Samuel A. Falvo II [Fri, 24 Jul 2020 05:29:55 +0000 (22:29 -0700)]
Address code review comments

- Remove hypervisor-related checks and main logic.
- Use field() to work with subfields of arbitrary signals.
- Use FormXXX classes to access opcode subfields.

16 months agoworking on div's test_pipe_caller
Jacob Lifshay [Fri, 24 Jul 2020 04:59:09 +0000 (21:59 -0700)]
working on div's test_pipe_caller

16 months agoadd power-instruction-analyzer as a dependency
Jacob Lifshay [Fri, 24 Jul 2020 02:36:02 +0000 (19:36 -0700)]
add power-instruction-analyzer as a dependency

16 months agoformat
Jacob Lifshay [Fri, 24 Jul 2020 02:35:49 +0000 (19:35 -0700)]
format

16 months agosyntax error
Luke Kenneth Casson Leighton [Thu, 23 Jul 2020 21:49:32 +0000 (22:49 +0100)]
syntax error

16 months agosupport 32-bit mem width setting
Luke Kenneth Casson Leighton [Thu, 23 Jul 2020 21:42:59 +0000 (22:42 +0100)]
support 32-bit mem width setting

16 months agotry SDRAM SDR
Luke Kenneth Casson Leighton [Thu, 23 Jul 2020 21:42:29 +0000 (22:42 +0100)]
try SDRAM SDR

16 months agoallow imem to be 64/32 bit wide
Luke Kenneth Casson Leighton [Thu, 23 Jul 2020 21:41:19 +0000 (22:41 +0100)]
allow imem to be 64/32 bit wide

16 months agobegin core in running state
Luke Kenneth Casson Leighton [Thu, 23 Jul 2020 19:28:51 +0000 (20:28 +0100)]
begin core in running state

16 months agotry different MEMTEST_xxx sizes with 64 bit bus width
Luke Kenneth Casson Leighton [Thu, 23 Jul 2020 19:28:37 +0000 (20:28 +0100)]
try different MEMTEST_xxx sizes with 64 bit bus width

16 months agoUpdate libreriscv HDL_workflow/coriolis2
Cole Poirier [Thu, 23 Jul 2020 19:43:24 +0000 (12:43 -0700)]
Update libreriscv HDL_workflow/coriolis2

16 months agoadd all div* and mod* instructions to test_pipe_caller
Jacob Lifshay [Thu, 23 Jul 2020 00:42:37 +0000 (17:42 -0700)]
add all div* and mod* instructions to test_pipe_caller

16 months agoworking on fsm
Jacob Lifshay [Wed, 22 Jul 2020 23:55:51 +0000 (16:55 -0700)]
working on fsm

16 months agoMerge remote-tracking branch 'origin/master'
Jacob Lifshay [Wed, 22 Jul 2020 22:19:40 +0000 (15:19 -0700)]
Merge remote-tracking branch 'origin/master'

16 months agoformat code
Jacob Lifshay [Wed, 22 Jul 2020 22:18:03 +0000 (15:18 -0700)]
format code

16 months agore-add CRG (clock reset generator)
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 21:11:57 +0000 (22:11 +0100)]
re-add CRG (clock reset generator)

16 months agomissing ports from issuer, when doing verilog
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 20:27:42 +0000 (21:27 +0100)]
missing ports from issuer, when doing verilog

16 months agoadd clock domain using snippet taken from random file
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 20:20:30 +0000 (21:20 +0100)]
add clock domain using snippet taken from random file

16 months agocleanup in litex core.py
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 20:11:32 +0000 (21:11 +0100)]
cleanup in litex core.py

16 months agoupdate comments
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 19:56:55 +0000 (20:56 +0100)]
update comments

16 months agoadd dummy irq set/get
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 19:49:59 +0000 (20:49 +0100)]
add dummy irq set/get

16 months agoadd boot-helper.S etc from microwatt litex core
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 19:45:19 +0000 (20:45 +0100)]
add boot-helper.S etc from microwatt litex core

16 months agoset additional MSR bits according to v3.0B spec when trap occurs
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 19:18:30 +0000 (20:18 +0100)]
set additional MSR bits according to v3.0B spec when trap occurs

16 months agouse (new) MSRb and PIb which has auto-bigendian numbers
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 19:11:40 +0000 (20:11 +0100)]
use (new) MSRb and PIb which has auto-bigendian numbers

16 months agosigh, auto-create some little/big-endian classes for accessing MSR/PI fields
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 19:08:29 +0000 (20:08 +0100)]
sigh, auto-create some little/big-endian classes for accessing MSR/PI fields

16 months agomissed import of Builder, set cpu_type to "None" temporarily
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 18:31:32 +0000 (19:31 +0100)]
missed import of Builder, set cpu_type to "None" temporarily

16 months agobegin converting litex sim to libre-soc
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 18:09:00 +0000 (19:09 +0100)]
begin converting litex sim to libre-soc

16 months agowhoops forgot field accessor
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 18:08:40 +0000 (19:08 +0100)]
whoops forgot field accessor

16 months agodo not use wildcard import
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 15:36:01 +0000 (16:36 +0100)]
do not use wildcard import

16 months agostart from vexriscv sim.py from
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 15:33:55 +0000 (16:33 +0100)]
start from vexriscv sim.py from
https://github.com/enjoy-digital/litex_vexriscv_smp

16 months agocorrect syntax error
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 15:32:47 +0000 (16:32 +0100)]
correct syntax error

16 months agofirst version of litex core (to be submitted upstream once tested)
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 15:30:35 +0000 (16:30 +0100)]
first version of litex core (to be submitted upstream once tested)

16 months agowhoops typo, 63-start not 3-start (doh)
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 14:53:00 +0000 (15:53 +0100)]
whoops typo, 63-start not 3-start (doh)

16 months agofield number ordering wrong way round?
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 14:48:18 +0000 (15:48 +0100)]
field number ordering wrong way round?
see https://bugs.libre-soc.org/show_bug.cgi?id=325#c107

16 months agosyntax error
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 14:42:23 +0000 (15:42 +0100)]
syntax error

16 months agoreview trap main_stage.py modifications: we are not doing hypervisor
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 13:57:13 +0000 (14:57 +0100)]
review trap main_stage.py modifications: we are not doing hypervisor
see https://bugs.libre-soc.org/show_bug.cgi?id=325#c104

16 months agocomments, add page spec numbers for branch ops into proof
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 12:53:43 +0000 (13:53 +0100)]
comments, add page spec numbers for branch ops into proof

16 months agoadd comment headings with spec page numbers
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 12:50:31 +0000 (13:50 +0100)]
add comment headings with spec page numbers

16 months agocomment on op.insn ordering
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 12:45:58 +0000 (13:45 +0100)]
comment on op.insn ordering

16 months agocode-shuffle, add comments
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 12:42:53 +0000 (13:42 +0100)]
code-shuffle, add comments

16 months agoadd TT.size and use it in PowerDecoder and trap input record
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 11:59:13 +0000 (12:59 +0100)]
add TT.size and use it in PowerDecoder and trap input record

16 months agoinline comments in trap proof
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 11:57:24 +0000 (12:57 +0100)]
inline comments in trap proof

16 months agonote that traptype MUST increase in bitwidth corresponding to additions
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 11:54:56 +0000 (12:54 +0100)]
note that traptype MUST increase in bitwidth corresponding to additions
to TT

16 months agofix branch main_stage proof, add ctr 32-bit, fix BCREG
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 10:41:44 +0000 (11:41 +0100)]
fix branch main_stage proof, add ctr 32-bit, fix BCREG

16 months agorework branch proof to use br_input_record
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 10:14:32 +0000 (11:14 +0100)]
rework branch proof to use br_input_record

16 months agoupdate README for pipe_data.py
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 09:50:47 +0000 (10:50 +0100)]
update README for pipe_data.py

16 months agoreduce number of FastRegs read ports
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 09:29:58 +0000 (10:29 +0100)]
reduce number of FastRegs read ports

16 months agocomments on what goes into CommonPipeSpec
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 09:29:36 +0000 (10:29 +0100)]
comments on what goes into CommonPipeSpec

16 months agoComplete FV properties for OP_TRAP instructions.
Samuel A. Falvo II [Wed, 22 Jul 2020 06:03:34 +0000 (23:03 -0700)]
Complete FV properties for OP_TRAP instructions.

16 months agoPEP8 compliance
Samuel A. Falvo II [Wed, 22 Jul 2020 03:08:32 +0000 (20:08 -0700)]
PEP8 compliance

16 months agoworking on FSMDivCoreStage
Jacob Lifshay [Wed, 22 Jul 2020 02:03:56 +0000 (19:03 -0700)]
working on FSMDivCoreStage

16 months agofix test_div_state_fsm
Jacob Lifshay [Wed, 22 Jul 2020 01:16:37 +0000 (18:16 -0700)]
fix test_div_state_fsm

16 months agoCompleted SC FV properties
Samuel A. Falvo II [Tue, 21 Jul 2020 21:45:59 +0000 (14:45 -0700)]
Completed SC FV properties

16 months agoRefine properties to comply with spec
Samuel A. Falvo II [Tue, 21 Jul 2020 21:16:34 +0000 (14:16 -0700)]
Refine properties to comply with spec

16 months agoFix where msr_i gets its value from
Samuel A. Falvo II [Tue, 21 Jul 2020 19:16:09 +0000 (12:16 -0700)]
Fix where msr_i gets its value from

16 months agoMerge in recent updates to TRAP FV properties.
Samuel A. Falvo II [Tue, 21 Jul 2020 19:00:22 +0000 (12:00 -0700)]
Merge in recent updates to TRAP FV properties.

16 months agoconvert branch pipeline to use msr/cia as immediates
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 18:36:39 +0000 (19:36 +0100)]
convert branch pipeline to use msr/cia as immediates

16 months agoput set_msr and set_cia back in for now
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 18:36:09 +0000 (19:36 +0100)]
put set_msr and set_cia back in for now

16 months agointeresting bug in test_compunit.py when there are no operands
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 18:35:39 +0000 (19:35 +0100)]
interesting bug in test_compunit.py when there are no operands
rdmask, if left set, interferes with the next instruction, but
only when there are no operands

16 months agotesting if MultiCompUnit can handle no input regs (it can)
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 17:49:10 +0000 (18:49 +0100)]
testing if MultiCompUnit can handle no input regs (it can)

16 months agodisable cxxsim for now
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 17:39:52 +0000 (18:39 +0100)]
disable cxxsim for now

16 months agomove cia and msr to trap input record
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 14:25:27 +0000 (15:25 +0100)]
move cia and msr to trap input record

16 months agoset ISACaller.msr rather than namespace[MSR]
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 14:23:04 +0000 (15:23 +0100)]
set ISACaller.msr rather than namespace[MSR]

16 months agowhen running an exception (trap) after "reset" must copy msr/cia state
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 14:22:28 +0000 (15:22 +0100)]
when running an exception (trap) after "reset" must copy msr/cia state

16 months agospurious imports of FHDLTestCase, should be from nmutil
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 14:14:00 +0000 (15:14 +0100)]
spurious imports of FHDLTestCase, should be from nmutil

16 months agowhitespace
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 13:30:47 +0000 (14:30 +0100)]
whitespace

16 months agoadd PC (CIA) to PowerDecode2 "state" for passing into input records
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 13:24:30 +0000 (14:24 +0100)]
add PC (CIA) to PowerDecode2 "state" for passing into input records
see https://bugs.libre-soc.org/show_bug.cgi?id=435

16 months agoadd msr exception bits setting function in hardware
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 13:10:54 +0000 (14:10 +0100)]
add msr exception bits setting function in hardware
and do same thing in ISACaller trap

16 months agomake cxxsim optional and print warning
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 12:53:28 +0000 (13:53 +0100)]
make cxxsim optional and print warning

16 months agocorrections to trap proof see
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 09:50:37 +0000 (10:50 +0100)]
corrections to trap proof see
https://bugs.libre-soc.org/show_bug.cgi?id=421#c17 and
https://bugs.libre-soc.org/show_bug.cgi?id=421#c18

16 months agouse alias for msr_i in trap proof
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 09:45:33 +0000 (10:45 +0100)]
use alias for msr_i in trap proof

16 months agocorrect trap spec page interrupt ref
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 09:41:36 +0000 (10:41 +0100)]
correct trap spec page interrupt ref

16 months agoRework SC properties to conform to style
Samuel A. Falvo II [Mon, 20 Jul 2020 23:17:00 +0000 (16:17 -0700)]
Rework SC properties to conform to style

16 months agoFormal properties for RFID.
Samuel A. Falvo II [Mon, 20 Jul 2020 23:08:50 +0000 (16:08 -0700)]
Formal properties for RFID.

16 months agoDocument the move of sdir from data_i to op.
Cesar Strauss [Mon, 20 Jul 2020 22:00:59 +0000 (19:00 -0300)]
Document the move of sdir from data_i to op.

Also, give op.sdir a name based on "op", to distinguish it
from internal signals.

16 months agoRemove extra yield from test case.
Cesar Strauss [Mon, 20 Jul 2020 20:13:27 +0000 (17:13 -0300)]
Remove extra yield from test case.

Seems pysim is correct, after all. There seems to be some
strange interaction between cxxrtl and python.