soc.git
15 months agoreorder / reorganise reset signals slightly
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 12:01:03 +0000 (13:01 +0100)]
reorder / reorganise reset signals slightly

15 months agofix div tests
Jacob Lifshay [Wed, 7 Oct 2020 04:01:15 +0000 (21:01 -0700)]
fix div tests

15 months agoupdate submodule
Jacob Lifshay [Wed, 7 Oct 2020 03:59:40 +0000 (20:59 -0700)]
update submodule

15 months agoFix forgotten test_pipe_caller changes from e0b4334c7d83dda41d5610239150079f30a2f713
Jacob Lifshay [Wed, 7 Oct 2020 01:36:06 +0000 (18:36 -0700)]
Fix forgotten test_pipe_caller changes from e0b4334c7d83dda41d5610239150079f30a2f713

15 months agoremove redunant signals
Tobias Platen [Tue, 6 Oct 2020 19:31:14 +0000 (21:31 +0200)]
remove redunant signals

15 months agoupdate comments on pimem.py
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 19:18:02 +0000 (20:18 +0100)]
update comments on pimem.py

15 months agotest_mmu_dcache_pi.py
Tobias Platen [Tue, 6 Oct 2020 18:51:34 +0000 (20:51 +0200)]
test_mmu_dcache_pi.py

15 months agocomments
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 17:18:09 +0000 (18:18 +0100)]
comments

15 months agoadd ports function to DummyPLL
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 17:09:48 +0000 (18:09 +0100)]
add ports function to DummyPLL

15 months agouse pdecode2.do not pdecode2.e in test_pipe_caller tests
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 17:08:16 +0000 (18:08 +0100)]
use pdecode2.do not pdecode2.e in test_pipe_caller tests

15 months agoskip Decode2ToOperand from PowerDecodeSubset
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 17:05:42 +0000 (18:05 +0100)]
skip Decode2ToOperand from PowerDecodeSubset

15 months agocomment SRR1 mem.exception
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 16:22:09 +0000 (17:22 +0100)]
comment SRR1 mem.exception

15 months agoadd SRR1 setting for LDST memory exception trap
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 15:58:14 +0000 (16:58 +0100)]
add SRR1 setting for LDST memory exception trap

15 months agopassing LDSTException over to Trap Pipeline
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 15:33:45 +0000 (16:33 +0100)]
passing LDSTException over to Trap Pipeline

15 months agoadd LDSTException decode/handling in PowerDecoder2
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 15:07:32 +0000 (16:07 +0100)]
add LDSTException decode/handling in PowerDecoder2

15 months agomake LDSTException fields added from list of fieldnames
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 15:05:36 +0000 (16:05 +0100)]
make LDSTException fields added from list of fieldnames

15 months agomove LDSTException to mem_types
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 14:48:17 +0000 (15:48 +0100)]
move LDSTException to mem_types

15 months agosubmodule update
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 13:06:36 +0000 (14:06 +0100)]
submodule update

15 months agoadd LDSTException to PortInterface
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 13:03:53 +0000 (14:03 +0100)]
add LDSTException to PortInterface

15 months agoadd sdr bypass routing via JTAG boundary scan
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 12:37:06 +0000 (13:37 +0100)]
add sdr bypass routing via JTAG boundary scan

15 months agoadd divde regression test
Jacob Lifshay [Tue, 6 Oct 2020 02:52:40 +0000 (19:52 -0700)]
add divde regression test

15 months agoupdate submodule
Jacob Lifshay [Tue, 6 Oct 2020 02:52:26 +0000 (19:52 -0700)]
update submodule

15 months agoadd moduw regression test
Jacob Lifshay [Tue, 6 Oct 2020 02:17:24 +0000 (19:17 -0700)]
add moduw regression test

15 months agoupdate submodule
Jacob Lifshay [Tue, 6 Oct 2020 02:16:24 +0000 (19:16 -0700)]
update submodule

15 months agoadd workaround for nmigen bug #502
Jacob Lifshay [Tue, 6 Oct 2020 01:59:39 +0000 (18:59 -0700)]
add workaround for nmigen bug #502

This fixes modsw

15 months agoupdate submodule
Jacob Lifshay [Tue, 6 Oct 2020 01:58:21 +0000 (18:58 -0700)]
update submodule

15 months agoadd modsw regression
Jacob Lifshay [Tue, 6 Oct 2020 01:07:56 +0000 (18:07 -0700)]
add modsw regression

15 months agoadd test case for divweu regression
Jacob Lifshay [Tue, 6 Oct 2020 01:06:51 +0000 (18:06 -0700)]
add test case for divweu regression

15 months agoupdate submodule
Jacob Lifshay [Tue, 6 Oct 2020 01:03:35 +0000 (18:03 -0700)]
update submodule

15 months agoprint regs in hex
Jacob Lifshay [Tue, 6 Oct 2020 00:16:29 +0000 (17:16 -0700)]
print regs in hex

15 months agoadd debug / investigation print statements
Luke Kenneth Casson Leighton [Mon, 5 Oct 2020 23:16:46 +0000 (00:16 +0100)]
add debug / investigation print statements

15 months ago`deepcopy` from cache instead of recreating parsers for `GardenSnakeCompiler`
Jacob Lifshay [Mon, 5 Oct 2020 22:21:33 +0000 (15:21 -0700)]
`deepcopy` from cache instead of recreating parsers for `GardenSnakeCompiler`

changes `make develop` time from about 1m30s to 1m09s for me

15 months agoformat code
Jacob Lifshay [Mon, 5 Oct 2020 22:20:40 +0000 (15:20 -0700)]
format code

15 months agoicache.py fix ispow2() util fn per https://bugs.libre-soc.org/show_bug.cgi?id=485#c53
Cole Poirier [Mon, 5 Oct 2020 16:44:36 +0000 (09:44 -0700)]
icache.py fix ispow2() util fn per https://bugs.libre-soc.org/show_bug.cgi?id=485#c53

15 months agowhoops fix syntax error
Luke Kenneth Casson Leighton [Mon, 5 Oct 2020 11:51:25 +0000 (12:51 +0100)]
whoops fix syntax error

15 months agowhoops fix syntax error
Luke Kenneth Casson Leighton [Mon, 5 Oct 2020 11:30:26 +0000 (12:30 +0100)]
whoops fix syntax error

15 months agoreturn test rather than "if test return True else False"
Luke Kenneth Casson Leighton [Mon, 5 Oct 2020 10:51:17 +0000 (11:51 +0100)]
return test rather than "if test return True else False"

15 months agowhitespace
Luke Kenneth Casson Leighton [Mon, 5 Oct 2020 10:49:40 +0000 (11:49 +0100)]
whitespace

15 months agowhitespace
Luke Kenneth Casson Leighton [Mon, 5 Oct 2020 10:44:03 +0000 (11:44 +0100)]
whitespace

15 months agoicache.py add python asserts that were a TODO commented section from
Cole Poirier [Mon, 5 Oct 2020 01:46:11 +0000 (18:46 -0700)]
icache.py add python asserts that were a TODO commented section from
icache.vhdl, print all constant values at start of icache_sim() in alphabetic order, make constant naming consistent

15 months agoicache.py fix formatting, mostly due to reduced indentation in preceding
Cole Poirier [Mon, 5 Oct 2020 00:30:09 +0000 (17:30 -0700)]
icache.py fix formatting, mostly due to reduced indentation in preceding
commits, remove uneccessary Display() statements

15 months agoicache.py remove comment that contained the entirety of microwatt's
Cole Poirier [Mon, 5 Oct 2020 00:14:14 +0000 (17:14 -0700)]
icache.py remove comment that contained the entirety of microwatt's
icache_tb.vhdl as it is no longer needed

15 months agoicache.py move icache_miss WAIT_ACK FSM state into method icache_miss_wait_ack()...
Cole Poirier [Mon, 5 Oct 2020 00:12:35 +0000 (17:12 -0700)]
icache.py move icache_miss WAIT_ACK FSM state into method icache_miss_wait_ack() to reduce clutter, indentation

15 months agoicache.py move icache_miss CLR_TAG FSM state into method icache_miss_clr_tag() to...
Cole Poirier [Mon, 5 Oct 2020 00:01:34 +0000 (17:01 -0700)]
icache.py move icache_miss CLR_TAG FSM state into method icache_miss_clr_tag() to reduce clutter, indentation

15 months agoicache.py move icache_miss IDLE FSM state into method icache_miss_idle()
Cole Poirier [Mon, 5 Oct 2020 00:00:04 +0000 (17:00 -0700)]
icache.py move icache_miss IDLE FSM state into method icache_miss_idle()
to reduce clutter, indentation

15 months agosimplify create_args
Jacob Lifshay [Mon, 5 Oct 2020 00:47:54 +0000 (17:47 -0700)]
simplify create_args

15 months agoSort returned variables to make sure `overflow` is last
Jacob Lifshay [Mon, 5 Oct 2020 00:32:45 +0000 (17:32 -0700)]
Sort returned variables to make sure `overflow` is last

Fixes #509

15 months agoformat caller.py
Jacob Lifshay [Mon, 5 Oct 2020 00:28:26 +0000 (17:28 -0700)]
format caller.py

15 months agochange div FSM pipeline unit to not have a combinatorial path directly from inputs...
Jacob Lifshay [Sun, 4 Oct 2020 22:17:41 +0000 (15:17 -0700)]
change div FSM pipeline unit to not have a combinatorial path directly from inputs to outputs

Fixes #510

15 months agosignificant reorg of the litex pinspecs to use pinmux JSON files
Luke Kenneth Casson Leighton [Sun, 4 Oct 2020 18:11:32 +0000 (19:11 +0100)]
significant reorg of the litex pinspecs to use pinmux JSON files

15 months agosubmodule update
Luke Kenneth Casson Leighton [Sun, 4 Oct 2020 16:44:18 +0000 (17:44 +0100)]
submodule update

15 months agoremove ls180io import
Luke Kenneth Casson Leighton [Sun, 4 Oct 2020 14:38:26 +0000 (15:38 +0100)]
remove ls180io import

15 months agomove ls180io.py back into ls180.py
Luke Kenneth Casson Leighton [Sun, 4 Oct 2020 14:37:25 +0000 (15:37 +0100)]
move ls180io.py back into ls180.py

15 months agoallow i2c to be routed via JTAG
Luke Kenneth Casson Leighton [Sat, 3 Oct 2020 19:46:44 +0000 (20:46 +0100)]
allow i2c to be routed via JTAG

15 months agonope. put it back and connect to platform pads in LS180Platform
Luke Kenneth Casson Leighton [Sat, 3 Oct 2020 19:27:23 +0000 (20:27 +0100)]
nope.  put it back and connect to platform pads in LS180Platform

15 months agomove iopad litex creation to ls180soc.py
Luke Kenneth Casson Leighton [Sat, 3 Oct 2020 19:14:20 +0000 (20:14 +0100)]
move iopad litex creation to ls180soc.py

15 months agominor reorg on JTAG, allow alternative pinset dict to be passed in
Luke Kenneth Casson Leighton [Sat, 3 Oct 2020 13:20:19 +0000 (14:20 +0100)]
minor reorg on JTAG, allow alternative pinset dict to be passed in

15 months agoadd regression testcase
Jacob Lifshay [Sat, 3 Oct 2020 01:04:39 +0000 (18:04 -0700)]
add regression testcase

15 months agoupdate submodule
Jacob Lifshay [Sat, 3 Oct 2020 01:04:17 +0000 (18:04 -0700)]
update submodule

15 months agoicache.py add req_hit_way as arg to icache_comb, actually ran file this
Cole Poirier [Fri, 2 Oct 2020 21:18:28 +0000 (14:18 -0700)]
icache.py add req_hit_way as arg to icache_comb, actually ran file this
time to make sure it's correct, fixes https://bugs.libre-soc.org/show_bug.cgi?id=485#c37

15 months agoadd pinmux generator to create litex pinmap
Luke Kenneth Casson Leighton [Fri, 2 Oct 2020 18:54:22 +0000 (19:54 +0100)]
add pinmux generator to create litex pinmap

15 months agoadd pinmux as submodule
Luke Kenneth Casson Leighton [Fri, 2 Oct 2020 18:35:49 +0000 (19:35 +0100)]
add pinmux as submodule

15 months agoicache.py add missing comb signal assignments per https://bugs.libre-soc.org/show_bug...
Cole Poirier [Thu, 1 Oct 2020 23:17:57 +0000 (16:17 -0700)]
icache.py add missing comb signal assignments per https://bugs.libre-soc.org/show_bug.cgi?id=485#c32

15 months agoarg CacheRam read output needs delay by 1 cycle
Luke Kenneth Casson Leighton [Thu, 1 Oct 2020 17:39:58 +0000 (18:39 +0100)]
arg CacheRam read output needs delay by 1 cycle

15 months agodo not pass cache row array around, just the current row
Luke Kenneth Casson Leighton [Thu, 1 Oct 2020 17:35:58 +0000 (18:35 +0100)]
do not pass cache row array around, just the current row

15 months agorevert bug in icache wishbone ack
Luke Kenneth Casson Leighton [Thu, 1 Oct 2020 17:16:27 +0000 (18:16 +0100)]
revert bug in icache wishbone ack

15 months agoadd clksel, pll to ls180
Luke Kenneth Casson Leighton [Thu, 1 Oct 2020 17:10:26 +0000 (18:10 +0100)]
add clksel, pll to ls180

15 months agocreate dummy PLL block, connect up to core and clock-selector
Luke Kenneth Casson Leighton [Thu, 1 Oct 2020 13:28:54 +0000 (14:28 +0100)]
create dummy PLL block, connect up to core and clock-selector

15 months agoAdd GTKWave document to test_compunit_fsm
Cesar Strauss [Thu, 1 Oct 2020 10:44:25 +0000 (07:44 -0300)]
Add GTKWave document to test_compunit_fsm

15 months agoadd I2C into ls180
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 21:33:25 +0000 (22:33 +0100)]
add I2C into ls180

15 months agoadd ASIC version of I2C Master
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 21:30:44 +0000 (22:30 +0100)]
add ASIC version of I2C Master

15 months agoclean up row store and wb adr in icache
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 12:52:17 +0000 (13:52 +0100)]
clean up row store and wb adr in icache

15 months agohmm only set wishbone address if ack is actually received
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 12:23:08 +0000 (13:23 +0100)]
hmm only set wishbone address if ack is actually received

15 months agoadd more debug prints in icache
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 11:47:37 +0000 (12:47 +0100)]
add more debug prints in icache

15 months agoremove more reviewed comments
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:53:10 +0000 (10:53 +0100)]
remove more reviewed comments

15 months agoremove reviewed comments
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:45:50 +0000 (10:45 +0100)]
remove reviewed comments

15 months agocomb on wr_index not sync
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:30:41 +0000 (10:30 +0100)]
comb on wr_index not sync

15 months agostart removing reviewed comments
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:30:12 +0000 (10:30 +0100)]
start removing reviewed comments

15 months agouse same constant name (confusing otherwise)
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:22:29 +0000 (10:22 +0100)]
use same constant name (confusing otherwise)

15 months agoneed asserts
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:22:08 +0000 (10:22 +0100)]
need asserts

15 months agohalve the number of icache lines for now
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:19:00 +0000 (10:19 +0100)]
halve the number of icache lines for now

15 months agouse Repl rather than for-loop to copy bit
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:17:38 +0000 (10:17 +0100)]
use Repl rather than for-loop to copy bit

15 months agomove loop invariant test out of loop
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:09:02 +0000 (10:09 +0100)]
move loop invariant test out of loop

15 months agoreduce size of ilang file by a factor of FIVE
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:03:34 +0000 (10:03 +0100)]
reduce size of ilang file by a factor of FIVE

15 months agostore tag in temp signal
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 08:55:58 +0000 (09:55 +0100)]
store tag in temp signal

15 months agoreduce gate usage by getting cache row only not entire cache array
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 08:51:14 +0000 (09:51 +0100)]
reduce gate usage by getting cache row only not entire cache array

15 months agofix read_tag to use word_select correctly
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 08:45:56 +0000 (09:45 +0100)]
fix read_tag to use word_select correctly

15 months agoforgot to add PLRUs as submodules
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 08:43:40 +0000 (09:43 +0100)]
forgot to add PLRUs as submodules

15 months agoicache.py fix combinatorial loop with by testing temp stbs_zero and
Cole Poirier [Tue, 29 Sep 2020 18:57:28 +0000 (11:57 -0700)]
icache.py fix combinatorial loop with by testing temp stbs_zero and
setting Signal stbs_done

15 months agoicache.py fix is_last_row_addr, get_next_row_addr
Cole Poirier [Tue, 29 Sep 2020 18:45:18 +0000 (11:45 -0700)]
icache.py fix is_last_row_addr, get_next_row_addr

15 months agoicache.py trying to sort out test failure, added r field req_adr to
Cole Poirier [Tue, 29 Sep 2020 18:27:36 +0000 (11:27 -0700)]
icache.py trying to sort out test failure, added r field req_adr to
properly implement WB spec compliant adressing

15 months agoicache.py fix test stbs_done signal, not stbs_zero temp signal
Cole Poirier [Tue, 29 Sep 2020 18:00:28 +0000 (11:00 -0700)]
icache.py fix test stbs_done signal, not stbs_zero temp signal

15 months agoicache.py fix rarange
Cole Poirier [Tue, 29 Sep 2020 17:55:49 +0000 (10:55 -0700)]
icache.py fix rarange

15 months agoicache.py fixed numerous bugs as specified by lkcl on bugzilla, now
Cole Poirier [Tue, 29 Sep 2020 17:37:20 +0000 (10:37 -0700)]
icache.py fixed numerous bugs as specified by lkcl on bugzilla, now
passes first unit test!

15 months agoicache.py use d_out as input to assignment instead of as assignee, now
Cole Poirier [Mon, 28 Sep 2020 23:07:11 +0000 (16:07 -0700)]
icache.py use d_out as input to assignment instead of as assignee, now
the right stuff is connected and the test fails in an interesting way,
add signal names

15 months agoreduce not-connected IO pins
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 15:58:48 +0000 (16:58 +0100)]
reduce not-connected IO pins

15 months agomissing pspec
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 15:58:29 +0000 (16:58 +0100)]
missing pspec

15 months agoconnect SDRAM dqm to wrdata_mask
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 15:53:23 +0000 (16:53 +0100)]
connect SDRAM dqm to wrdata_mask

15 months agolots of sorting out iopads
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 11:33:33 +0000 (12:33 +0100)]
lots of sorting out iopads
* add sdram clock
* rename serial to uart
* disable I2C for now (needs bi-directional pads)
* make sdram and sd0 "en" only one pin (sort out litex issue)
* add "NC" pins so that there are no missing pins

15 months agoadd "nocore" option to build verilog
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 11:27:34 +0000 (12:27 +0100)]
add "nocore" option to build verilog