soc.git
2 years agoUpdate to latest wiki version, fix bug in prty pseudocode
Michael Nolan [Fri, 15 May 2020 14:21:30 +0000 (10:21 -0400)]
Update to latest wiki version, fix bug in prty pseudocode

2 years agoadd count leading zero test into logical test_pipe_caller.py
Luke Kenneth Casson Leighton [Fri, 15 May 2020 13:19:53 +0000 (14:19 +0100)]
add count leading zero test into logical test_pipe_caller.py

2 years agolink countzero in to Logical pipeline
Luke Kenneth Casson Leighton [Fri, 15 May 2020 13:15:41 +0000 (14:15 +0100)]
link countzero in to Logical pipeline

2 years agooutput countzero ilang
Luke Kenneth Casson Leighton [Fri, 15 May 2020 12:58:57 +0000 (13:58 +0100)]
output countzero ilang

2 years agoremove countzero vhdl tb code
Luke Kenneth Casson Leighton [Fri, 15 May 2020 12:54:20 +0000 (13:54 +0100)]
remove countzero vhdl tb code

2 years agoswap encode responses, 3210 not 0123 for left mode
Luke Kenneth Casson Leighton [Fri, 15 May 2020 11:43:30 +0000 (12:43 +0100)]
swap encode responses, 3210 not 0123 for left mode

2 years agoadd some more tests to countzero
Luke Kenneth Casson Leighton [Fri, 15 May 2020 11:28:15 +0000 (12:28 +0100)]
add some more tests to countzero

2 years agocool! countzero unit test works!
Luke Kenneth Casson Leighton [Fri, 15 May 2020 11:18:25 +0000 (12:18 +0100)]
cool!  countzero unit test works!

2 years agocode-munging
Luke Kenneth Casson Leighton [Fri, 15 May 2020 11:13:26 +0000 (12:13 +0100)]
code-munging

2 years agobit of code-morphing of countzero.py
Luke Kenneth Casson Leighton [Fri, 15 May 2020 11:08:20 +0000 (12:08 +0100)]
bit of code-morphing of countzero.py

2 years agomake module combinatorial
Luke Kenneth Casson Leighton [Fri, 15 May 2020 10:54:35 +0000 (11:54 +0100)]
make module combinatorial

2 years agoconverted countzero from microwatt
Tobias Platen [Fri, 15 May 2020 09:03:37 +0000 (11:03 +0200)]
converted countzero from microwatt

2 years agominor cleanup
Luke Kenneth Casson Leighton [Thu, 14 May 2020 21:27:30 +0000 (22:27 +0100)]
minor cleanup

2 years agomore code-munging
Luke Kenneth Casson Leighton [Thu, 14 May 2020 21:12:37 +0000 (22:12 +0100)]
more code-munging

2 years agorandom commenting and code-morph of Logical
Luke Kenneth Casson Leighton [Thu, 14 May 2020 21:02:59 +0000 (22:02 +0100)]
random commenting and code-morph of Logical

2 years agotidy up rotator main stage
Luke Kenneth Casson Leighton [Thu, 14 May 2020 20:54:48 +0000 (21:54 +0100)]
tidy up rotator main stage

2 years agosmall code-shuffle
Luke Kenneth Casson Leighton [Thu, 14 May 2020 20:47:50 +0000 (21:47 +0100)]
small code-shuffle

2 years agoupdate submodule for parity
Luke Kenneth Casson Leighton [Thu, 14 May 2020 19:48:22 +0000 (20:48 +0100)]
update submodule for parity

2 years agoAdd patch for cmpb
Michael Nolan [Thu, 14 May 2020 19:19:58 +0000 (15:19 -0400)]
Add patch for cmpb

2 years agoupdate submodule isa tables to match OP_CMPB moving to Logical
Luke Kenneth Casson Leighton [Thu, 14 May 2020 19:07:18 +0000 (20:07 +0100)]
update submodule isa tables to match OP_CMPB moving to Logical

2 years agoadd parity test
Luke Kenneth Casson Leighton [Thu, 14 May 2020 19:04:46 +0000 (20:04 +0100)]
add parity test

2 years agoadd the ever-weird parity instruction
Luke Kenneth Casson Leighton [Thu, 14 May 2020 19:03:18 +0000 (20:03 +0100)]
add the ever-weird parity instruction

2 years agoclarify code, use temporary
Luke Kenneth Casson Leighton [Thu, 14 May 2020 18:40:03 +0000 (19:40 +0100)]
clarify code, use temporary

2 years agosimplify popcount
Luke Kenneth Casson Leighton [Thu, 14 May 2020 18:38:48 +0000 (19:38 +0100)]
simplify popcount

2 years agoadd popcount test
Luke Kenneth Casson Leighton [Thu, 14 May 2020 18:18:15 +0000 (19:18 +0100)]
add popcount test

2 years agoadd (untested) popcount
Luke Kenneth Casson Leighton [Thu, 14 May 2020 18:13:32 +0000 (19:13 +0100)]
add (untested) popcount

2 years agodebug info on assertion
Luke Kenneth Casson Leighton [Thu, 14 May 2020 17:16:28 +0000 (18:16 +0100)]
debug info on assertion

2 years agoadd comment about CMP swapping
Luke Kenneth Casson Leighton [Thu, 14 May 2020 17:13:38 +0000 (18:13 +0100)]
add comment about CMP swapping

2 years agocleanup Logical
Luke Kenneth Casson Leighton [Thu, 14 May 2020 16:57:34 +0000 (17:57 +0100)]
cleanup Logical

2 years agoinvert test condition in formal proof of ALU output stage
Luke Kenneth Casson Leighton [Thu, 14 May 2020 16:39:45 +0000 (17:39 +0100)]
invert test condition in formal proof of ALU output stage

2 years agomove inversion of cmp into output stage by inverting the is +ve and is -ve test
Luke Kenneth Casson Leighton [Thu, 14 May 2020 16:34:39 +0000 (17:34 +0100)]
move inversion of cmp into output stage by inverting the is +ve and is -ve test
this saves on 2x 64-bit MUXes if the actual operands A and B were swapped
instead

2 years agoidea: invert pos/neg test in output stage, uses an XOR instead of QTY 2 64-bit
Luke Kenneth Casson Leighton [Thu, 14 May 2020 16:20:53 +0000 (17:20 +0100)]
idea: invert pos/neg test in output stage, uses an XOR instead of QTY 2 64-bit
MUXes and a mess/morass of code

2 years agoImplement OP_CMP
Michael Nolan [Thu, 14 May 2020 15:40:22 +0000 (11:40 -0400)]
Implement OP_CMP

Had to reverse the a and b inputs if a cmp is detected though. Ugh

2 years agoAdd OP_CMPB
Michael Nolan [Thu, 14 May 2020 15:06:43 +0000 (11:06 -0400)]
Add OP_CMPB

2 years agoUpdate to latest wiki version
Michael Nolan [Thu, 14 May 2020 15:06:32 +0000 (11:06 -0400)]
Update to latest wiki version

2 years agoFix bug in shift_rot, update proof to handle new interface
Michael Nolan [Thu, 14 May 2020 14:35:44 +0000 (10:35 -0400)]
Fix bug in shift_rot, update proof to handle new interface

2 years agominor experimental rework of LDSTCompUnit to suit score6600 integration
Luke Kenneth Casson Leighton [Thu, 14 May 2020 13:04:22 +0000 (14:04 +0100)]
minor experimental rework of LDSTCompUnit to suit score6600 integration

2 years agoadd TODO comments on Logical pipeline
Luke Kenneth Casson Leighton [Thu, 14 May 2020 10:04:04 +0000 (11:04 +0100)]
add TODO comments on Logical pipeline

2 years agowhoops assertion that the Logical pipeline Function Unit is... um... LOGICAL
Luke Kenneth Casson Leighton [Thu, 14 May 2020 09:51:56 +0000 (10:51 +0100)]
whoops assertion that the Logical pipeline Function Unit is... um... LOGICAL

2 years agomove forward to logical pipelines Function type
Luke Kenneth Casson Leighton [Thu, 14 May 2020 09:45:42 +0000 (10:45 +0100)]
move forward to logical pipelines Function type

2 years agoadd logical pipeline to Power decode Function enum
Luke Kenneth Casson Leighton [Thu, 14 May 2020 09:39:07 +0000 (10:39 +0100)]
add logical pipeline to Power decode Function enum

2 years agoAdd test for random rlcd(l/r) instructions
Michael Nolan [Wed, 13 May 2020 22:47:44 +0000 (18:47 -0400)]
Add test for random rlcd(l/r) instructions

2 years agoFix bug in rotator preventing use of 64 bit rlcl/r
Michael Nolan [Wed, 13 May 2020 22:44:49 +0000 (18:44 -0400)]
Fix bug in rotator preventing use of 64 bit rlcl/r

2 years agoUpdate to latest wiki version
Michael Nolan [Wed, 13 May 2020 22:00:23 +0000 (18:00 -0400)]
Update to latest wiki version

2 years agoadd TODO placeholders for popcount and parity
Luke Kenneth Casson Leighton [Wed, 13 May 2020 21:54:51 +0000 (22:54 +0100)]
add TODO placeholders for popcount and parity

2 years agominor tidyup
Luke Kenneth Casson Leighton [Wed, 13 May 2020 21:45:05 +0000 (22:45 +0100)]
minor tidyup

2 years agocomments on ALU pipeline
Luke Kenneth Casson Leighton [Wed, 13 May 2020 21:42:51 +0000 (22:42 +0100)]
comments on ALU pipeline

2 years agoupdate comment on Logical pipeline
Luke Kenneth Casson Leighton [Wed, 13 May 2020 21:40:12 +0000 (22:40 +0100)]
update comment on Logical pipeline

2 years agoremove Logical operations from ALU pipeline
Luke Kenneth Casson Leighton [Wed, 13 May 2020 21:37:21 +0000 (22:37 +0100)]
remove Logical operations from ALU pipeline

2 years agosplit out Logical operations into separate pipeline
Luke Kenneth Casson Leighton [Wed, 13 May 2020 21:35:16 +0000 (22:35 +0100)]
split out Logical operations into separate pipeline

2 years agocomments (and whitespace
Luke Kenneth Casson Leighton [Wed, 13 May 2020 21:19:54 +0000 (22:19 +0100)]
comments (and whitespace

2 years agoFix too wide bitfield being selected for opcode 30
Michael Nolan [Wed, 13 May 2020 20:41:37 +0000 (16:41 -0400)]
Fix too wide bitfield being selected for opcode 30

2 years agoFix weirdness with rldicl and friends in test_caller.py
Michael Nolan [Wed, 13 May 2020 20:22:44 +0000 (16:22 -0400)]
Fix weirdness with rldicl and friends in test_caller.py

2 years agoAdd support for OP_EXTS
Michael Nolan [Wed, 13 May 2020 19:54:55 +0000 (15:54 -0400)]
Add support for OP_EXTS

2 years agorestore field decoders (works with BE/LE) in rotator
Luke Kenneth Casson Leighton [Wed, 13 May 2020 19:23:11 +0000 (20:23 +0100)]
restore field decoders (works with BE/LE) in rotator

2 years agominor cleanup of shift_rot main_stage
Luke Kenneth Casson Leighton [Wed, 13 May 2020 18:55:41 +0000 (19:55 +0100)]
minor cleanup of shift_rot main_stage

2 years agoAdd missing input stage and pipe_data
Michael Nolan [Wed, 13 May 2020 18:52:26 +0000 (14:52 -0400)]
Add missing input stage and pipe_data

2 years agosimplift right_mask and left_mask rotator sub-functions, remove TODO comments
Luke Kenneth Casson Leighton [Wed, 13 May 2020 18:51:12 +0000 (19:51 +0100)]
simplift right_mask and left_mask rotator sub-functions, remove TODO comments

2 years agoFix bug with ROTL32 helper
Michael Nolan [Wed, 13 May 2020 18:02:13 +0000 (14:02 -0400)]
Fix bug with ROTL32 helper

Turns out it's supposed to duplicate the lower 32 bits to the high 32
bits, and do a 64 bit rotate

2 years agoSomewhat working now?
Michael Nolan [Wed, 13 May 2020 17:51:13 +0000 (13:51 -0400)]
Somewhat working now?

2 years agoIntegrate rotator.py into shift_rot unit
Michael Nolan [Wed, 13 May 2020 17:45:06 +0000 (13:45 -0400)]
Integrate rotator.py into shift_rot unit

2 years agoUpdate cmp test in test_caller.py
Michael Nolan [Wed, 13 May 2020 15:35:41 +0000 (11:35 -0400)]
Update cmp test in test_caller.py

2 years agoAdd assertions to ALU and shift_rot test that the instruction FU is right
Michael Nolan [Wed, 13 May 2020 14:26:38 +0000 (10:26 -0400)]
Add assertions to ALU and shift_rot test that the instruction FU is right

2 years agoAdd SHIFT_ROT FU
Michael Nolan [Wed, 13 May 2020 14:23:21 +0000 (10:23 -0400)]
Add SHIFT_ROT FU

2 years agoModify alu test to put reg1 *OR* reg3 into alu input A
Michael Nolan [Wed, 13 May 2020 14:12:36 +0000 (10:12 -0400)]
Modify alu test to put reg1 *OR* reg3 into alu input A

2 years agoUpdate TODO
Michael Nolan [Wed, 13 May 2020 14:07:56 +0000 (10:07 -0400)]
Update TODO

2 years agoremove operand c from ALU in/out
Luke Kenneth Casson Leighton [Wed, 13 May 2020 00:02:21 +0000 (01:02 +0100)]
remove operand c from ALU in/out

2 years agotemporary reorg of reg/immediate reading
Luke Kenneth Casson Leighton [Tue, 12 May 2020 20:57:18 +0000 (21:57 +0100)]
temporary reorg of reg/immediate reading

2 years agoadd 3rd register input to ALUInputData
Luke Kenneth Casson Leighton [Tue, 12 May 2020 20:21:49 +0000 (21:21 +0100)]
add 3rd register input to ALUInputData

2 years agoconnect LDSTMulti to 6600 Scoreboard
Luke Kenneth Casson Leighton [Tue, 12 May 2020 18:10:41 +0000 (19:10 +0100)]
connect LDSTMulti to 6600 Scoreboard

2 years agowhen doing LD-immediate only acknowledge register 1 rd-req
Luke Kenneth Casson Leighton [Tue, 12 May 2020 12:34:30 +0000 (13:34 +0100)]
when doing LD-immediate only acknowledge register 1 rd-req

2 years agoAdd new shift_rot FU for shifts and rotates
Michael Nolan [Tue, 12 May 2020 17:37:42 +0000 (13:37 -0400)]
Add new shift_rot FU for shifts and rotates

2 years agoRemove rotates and shifts from alu
Michael Nolan [Tue, 12 May 2020 17:29:02 +0000 (13:29 -0400)]
Remove rotates and shifts from alu

2 years agoMassively spead up test_pipe_caller.py
Michael Nolan [Mon, 11 May 2020 22:45:22 +0000 (18:45 -0400)]
Massively spead up test_pipe_caller.py

2 years agoRevert "Greatly speed up test_pipe_caller.py"
Michael Nolan [Mon, 11 May 2020 22:20:54 +0000 (18:20 -0400)]
Revert "Greatly speed up test_pipe_caller.py"

This reverts commit 54025cace312817b0f9d831865441a0e52db573a.

2 years agoGreatly speed up test_pipe_caller.py
Michael Nolan [Mon, 11 May 2020 21:46:01 +0000 (17:46 -0400)]
Greatly speed up test_pipe_caller.py

2 years agocomments from discussion
Luke Kenneth Casson Leighton [Mon, 11 May 2020 18:18:29 +0000 (19:18 +0100)]
comments from discussion
https://bugs.libre-soc.org/show_bug.cgi?id=305#c43

2 years agoReverse bit order for cr0 in proof
Michael Nolan [Mon, 11 May 2020 15:32:20 +0000 (11:32 -0400)]
Reverse bit order for cr0 in proof

2 years agoCheck output of cr0 from alu
Michael Nolan [Mon, 11 May 2020 15:30:34 +0000 (11:30 -0400)]
Check output of cr0 from alu

2 years agoAdd carry in input to alu testbench
Michael Nolan [Mon, 11 May 2020 15:19:13 +0000 (11:19 -0400)]
Add carry in input to alu testbench

2 years agoAdd ability to specify initial state for SPRs
Michael Nolan [Mon, 11 May 2020 15:15:37 +0000 (11:15 -0400)]
Add ability to specify initial state for SPRs

2 years agoFix proof_input_stage.py
Michael Nolan [Mon, 11 May 2020 14:33:08 +0000 (10:33 -0400)]
Fix proof_input_stage.py

2 years agoFix rlwimi by reordering the inputs *again*
Michael Nolan [Mon, 11 May 2020 14:28:28 +0000 (10:28 -0400)]
Fix rlwimi by reordering the inputs *again*

2 years agoRe-enable rlwinm test
Michael Nolan [Mon, 11 May 2020 14:23:00 +0000 (10:23 -0400)]
Re-enable rlwinm test

2 years agoCheck write register number too
Michael Nolan [Mon, 11 May 2020 14:10:25 +0000 (10:10 -0400)]
Check write register number too

2 years agoReorder the register reads so the field in read_reg2 is last
Michael Nolan [Mon, 11 May 2020 14:04:07 +0000 (10:04 -0400)]
Reorder the register reads so the field in read_reg2 is last

2 years agoHave test_pipe_caller actually read from the registers specified in instruction
Michael Nolan [Mon, 11 May 2020 13:55:52 +0000 (09:55 -0400)]
Have test_pipe_caller actually read from the registers specified in instruction

2 years agoActually implement rlwimi
Michael Nolan [Sun, 10 May 2020 23:16:17 +0000 (19:16 -0400)]
Actually implement rlwimi

2 years agocomment input signals
Luke Kenneth Casson Leighton [Mon, 11 May 2020 12:55:40 +0000 (13:55 +0100)]
comment input signals

2 years agocleanup rotator.py
Luke Kenneth Casson Leighton [Mon, 11 May 2020 12:10:26 +0000 (13:10 +0100)]
cleanup rotator.py

2 years agoadd docstring, missing return module
Luke Kenneth Casson Leighton [Mon, 11 May 2020 10:47:26 +0000 (11:47 +0100)]
add docstring, missing return module

2 years agostart cleanup of rotator.py, Cat order is inverted
Luke Kenneth Casson Leighton [Mon, 11 May 2020 10:44:00 +0000 (11:44 +0100)]
start cleanup of rotator.py, Cat order is inverted

2 years agoconvert microwatt rotator to nmigen (first draft)
Luke Kenneth Casson Leighton [Mon, 11 May 2020 10:29:49 +0000 (11:29 +0100)]
convert microwatt rotator to nmigen (first draft)

2 years agoAdd test for rlwnm
Michael Nolan [Sun, 10 May 2020 22:55:16 +0000 (18:55 -0400)]
Add test for rlwnm

2 years agoImplement rlwimi as well
Michael Nolan [Sun, 10 May 2020 22:52:45 +0000 (18:52 -0400)]
Implement rlwimi as well

2 years agoImplement rlwinm in alu
Michael Nolan [Sun, 10 May 2020 20:05:23 +0000 (16:05 -0400)]
Implement rlwinm in alu

2 years agoAdd test for rlwinm
Michael Nolan [Sun, 10 May 2020 20:03:35 +0000 (16:03 -0400)]
Add test for rlwinm

2 years agoReduce BMC depth on proof_main_stage.py
Michael Nolan [Sun, 10 May 2020 16:26:27 +0000 (12:26 -0400)]
Reduce BMC depth on proof_main_stage.py

2 years agouse temporary python vars rather than copy signals (shorter code)
Luke Kenneth Casson Leighton [Sun, 10 May 2020 05:42:43 +0000 (06:42 +0100)]
use temporary python vars rather than copy signals (shorter code)

2 years agoAdd shift left and shift right to main stage proof
Michael Nolan [Sat, 9 May 2020 23:22:28 +0000 (19:22 -0400)]
Add shift left and shift right to main stage proof