soc.git
6 months agoradix: reading first page table entry
Tobias Platen [Wed, 10 Mar 2021 18:41:11 +0000 (19:41 +0100)]
radix: reading first page table entry

6 months agoadd walk_tree arguments it needs
Luke Kenneth Casson Leighton [Wed, 10 Mar 2021 16:32:28 +0000 (16:32 +0000)]
add walk_tree arguments it needs
see https://bugs.libre-soc.org/show_bug.cgi?id=604#c13

6 months agofix address must convert to SelectableInt
Luke Kenneth Casson Leighton [Tue, 9 Mar 2021 19:40:19 +0000 (19:40 +0000)]
fix address must convert to SelectableInt

6 months agocall decode_ptre on address to obtain shift, mbits, and pgbase
Luke Kenneth Casson Leighton [Tue, 9 Mar 2021 19:38:24 +0000 (19:38 +0000)]
call decode_ptre on address to obtain shift, mbits, and pgbase

6 months agowhitespace
Tobias Platen [Tue, 9 Mar 2021 19:03:10 +0000 (20:03 +0100)]
whitespace

6 months agoRADIX: call self._walk_tree in ld and st
Tobias Platen [Tue, 9 Mar 2021 18:59:51 +0000 (19:59 +0100)]
RADIX: call self._walk_tree in ld and st

6 months agodebug radix mmu ISACaller
Luke Kenneth Casson Leighton [Tue, 9 Mar 2021 18:09:53 +0000 (18:09 +0000)]
debug radix mmu ISACaller

6 months agocomment out broken spr code
Tobias Platen [Tue, 9 Mar 2021 17:06:59 +0000 (18:06 +0100)]
comment out broken spr code

6 months ago_walk_tree: access sprs
Tobias Platen [Tue, 9 Mar 2021 16:34:17 +0000 (17:34 +0100)]
_walk_tree: access sprs

6 months agocreate first check_perms RADIX ISACaller function
Luke Kenneth Casson Leighton [Tue, 9 Mar 2021 13:09:35 +0000 (13:09 +0000)]
create first check_perms RADIX ISACaller function

6 months agomove Mem class out of ISACaller
Luke Kenneth Casson Leighton [Tue, 9 Mar 2021 12:56:49 +0000 (12:56 +0000)]
move Mem class out of ISACaller

6 months agocleanup imports
Luke Kenneth Casson Leighton [Tue, 9 Mar 2021 12:41:58 +0000 (12:41 +0000)]
cleanup imports

6 months agomove ISACaller RADIX MMU class to separate module
Luke Kenneth Casson Leighton [Tue, 9 Mar 2021 12:38:08 +0000 (12:38 +0000)]
move ISACaller RADIX MMU class to separate module

6 months agoadd pgtable and pte calculation to RADIX ISACaller
Luke Kenneth Casson Leighton [Tue, 9 Mar 2021 12:30:02 +0000 (12:30 +0000)]
add pgtable and pte calculation to RADIX ISACaller

6 months agoEnable VL==0 vector instruction skip test case
Cesar Strauss [Tue, 9 Mar 2021 11:00:04 +0000 (08:00 -0300)]
Enable VL==0 vector instruction skip test case

6 months agoAdd some extra debug traces to the GTKWave document
Cesar Strauss [Tue, 9 Mar 2021 10:57:41 +0000 (07:57 -0300)]
Add some extra debug traces to the GTKWave document

6 months agoCreate a new signal for the Simulator to wait on
Cesar Strauss [Tue, 9 Mar 2021 10:49:03 +0000 (07:49 -0300)]
Create a new signal for the Simulator to wait on

We wait on "core busy" before simulating an instruction. Trouble is, on a
VL==0 loop, there is no issue, so busy is never toggled. As a solution,
export a new insn_done signal with is pulsed either at end of Execute, or
when going back to Fetch due to skipping a vector instruction.

6 months agostart adding _get_prtable_addr
Luke Kenneth Casson Leighton [Mon, 8 Mar 2021 22:43:18 +0000 (22:43 +0000)]
start adding _get_prtable_addr

6 months agoactually make it possible to disable svp64 on commandline of test_issuer.py
Luke Kenneth Casson Leighton [Mon, 8 Mar 2021 17:21:34 +0000 (17:21 +0000)]
actually make it possible to disable svp64 on commandline of test_issuer.py

6 months agoadd option in TestRunner to disable svp64 via commandline test_runner.py nosvp64
Luke Kenneth Casson Leighton [Mon, 8 Mar 2021 17:00:36 +0000 (17:00 +0000)]
add option in TestRunner to disable svp64 via commandline test_runner.py nosvp64
currently does nothing

6 months agoadd option to cut out SVP64 from PowerDecoder2
Luke Kenneth Casson Leighton [Mon, 8 Mar 2021 12:10:00 +0000 (12:10 +0000)]
add option to cut out SVP64 from PowerDecoder2

6 months agocorrect comments in sv.add rc=1
Luke Kenneth Casson Leighton [Mon, 8 Mar 2021 12:07:50 +0000 (12:07 +0000)]
correct comments in sv.add rc=1

6 months agoRemove the unused internal insn_done signal
Cesar Strauss [Mon, 8 Mar 2021 10:22:57 +0000 (07:22 -0300)]
Remove the unused internal insn_done signal

This was used previously to enable writing to the PC register, but it's
done now within a state transition.

6 months agoFix argument order to match function declaration
Cesar Strauss [Sun, 7 Mar 2021 22:32:45 +0000 (19:32 -0300)]
Fix argument order to match function declaration

No harm was done, since the second inversion undid the first.
Just the VCD traces were switched.

6 months agoFix missing NIA update on ISACaller
Cesar Strauss [Sun, 7 Mar 2021 20:55:39 +0000 (17:55 -0300)]
Fix missing NIA update on ISACaller

The effect of this bug was mostly hidden because NIA is later updated at
the end of the SV Loop, in call(). However, in a VL==0 loop, the effect
is apparent, as PC is incremented by 4 instead of 8.

6 months agowhoops should be "make gitupdate"
Luke Kenneth Casson Leighton [Sun, 7 Mar 2021 21:35:46 +0000 (21:35 +0000)]
whoops should be "make gitupdate"

6 months agoRADIX: read SPRs
Tobias Platen [Sun, 7 Mar 2021 18:22:57 +0000 (19:22 +0100)]
RADIX: read SPRs

6 months agoRADIX: implement memassign and call
Tobias Platen [Sun, 7 Mar 2021 16:39:23 +0000 (17:39 +0100)]
RADIX: implement memassign and call

6 months agoadd SVSTATE read to DMI interface
Luke Kenneth Casson Leighton [Sun, 7 Mar 2021 15:05:24 +0000 (15:05 +0000)]
add SVSTATE read to DMI interface

6 months agoMerge WAIT_RESET into INSN_FETCH on the Issue FSM
Cesar Strauss [Sun, 7 Mar 2021 11:49:55 +0000 (08:49 -0300)]
Merge WAIT_RESET into INSN_FETCH on the Issue FSM

In a VL==0 loop, while we are skipping vector instructions, there needs to
be a way to stop the core. Unfortunately, this means duplicating the
corresponding code at instruction end, since there is no state in common
on either loop (the VL==0 instruction skip loop and the VL>1 vector loop).

This does makes it a little non-deterministic.

Normally, we would stop the core at instruction end, but could instead end
up stopping at instruction start. For this to happen, you need to stop the
core at the right moment, just after the instruction ended and before
the next instruction begins.

A way to avoid this, if necessary, would be to create a duplicate of the
INSN_FETCH state, that doesn't wait on "core stop" release.

Since we are now waiting on "core stop" release at instruction start
anyway, there is no need for the special WAIT_RESET state anymore.

6 months agomove DMI stuff to separate function in issuer.py
Luke Kenneth Casson Leighton [Sun, 7 Mar 2021 11:34:32 +0000 (11:34 +0000)]
move DMI stuff to separate function in issuer.py

6 months agoupdate comments in issuer.py
Luke Kenneth Casson Leighton [Sun, 7 Mar 2021 11:30:34 +0000 (11:30 +0000)]
update comments in issuer.py

6 months agoadd Rc=1 SVP64 unit test to svp64_cases.py
Luke Kenneth Casson Leighton [Sun, 7 Mar 2021 11:12:36 +0000 (11:12 +0000)]
add Rc=1 SVP64 unit test to svp64_cases.py

6 months agoImplement the VL==0 loop
Cesar Strauss [Sun, 7 Mar 2021 09:41:47 +0000 (06:41 -0300)]
Implement the VL==0 loop

Just after decode, decide whether we proceed to Execute, or shortcut it
directly to the next Fetch.

6 months agoAllow updating the PC and SVSTATE registers while stopped
Cesar Strauss [Sat, 6 Mar 2021 22:38:00 +0000 (19:38 -0300)]
Allow updating the PC and SVSTATE registers while stopped

While the fetch address was overridden by a PC reset, the PC register
itself was updated (with NIA) only after the first instruction ended. Use
the time while the core is stopped to recognise and update the PC and
SVSTATE registers, before the first instruction starts.

6 months agoEnable the Simple-V loop test case
Cesar Strauss [Sat, 6 Mar 2021 19:39:14 +0000 (16:39 -0300)]
Enable the Simple-V loop test case

6 months agoBegin to implement the Simple-V loop
Cesar Strauss [Sat, 6 Mar 2021 19:29:34 +0000 (16:29 -0300)]
Begin to implement the Simple-V loop

After returning from executing an instruction, decide whether to return
to Fetch, or go repeat Execute again.

1) If PC or SVSTATE were updated, go directly to Fetch, without updating
   either
2) If there is no vector output, or it's the last VL loop iteration, go
   back to Fetch as well, but update the PC. In the latter case, also
   reset SRCSTEP
3) Otherwise, we are still in the loop, so increment SVSTEP, and go back
   to Execute. But, first, pass through a new state, DECODE_SV, so the new
   register numbers can be decoded.

6 months agoDo not reset pc_changed and sv_changed at instruction end
Cesar Strauss [Sat, 6 Mar 2021 17:12:08 +0000 (14:12 -0300)]
Do not reset pc_changed and sv_changed at instruction end

We need these outputs to hold stable, so the Issue FSM can know whether
it can return to the Simple-V loop, or must return to Fetch. A good place
to reset these is at the start, before any instruction is executed.

6 months agoMake the raw opcode input port of the decoder stay stable
Cesar Strauss [Sat, 6 Mar 2021 16:46:50 +0000 (13:46 -0300)]
Make the raw opcode input port of the decoder stay stable

During a Simple-V loop, the decoder will be reused repeatedly, so its
raw opcode input needs to hold stable. An alternate way would be to
pass the raw opcode and the SVP64 RM field to the issue FSM, so it could
supply these decoder inputs when needed.

6 months agoremove blackbox attribute on SPBlock_512W64B8W
Luke Kenneth Casson Leighton [Sat, 6 Mar 2021 00:31:32 +0000 (00:31 +0000)]
remove blackbox attribute on SPBlock_512W64B8W

6 months agoadd SPBlock_512W64B8W.v blackbox file
Luke Kenneth Casson Leighton [Sat, 6 Mar 2021 00:28:49 +0000 (00:28 +0000)]
add SPBlock_512W64B8W.v blackbox file

6 months agoremove sram4k wishbone bte/cti in litex interconnect
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 23:11:11 +0000 (23:11 +0000)]
remove sram4k wishbone bte/cti in litex interconnect

6 months agolitex expects wishbone "err" signals even if not used
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 21:08:28 +0000 (21:08 +0000)]
litex expects wishbone "err" signals even if not used

6 months agoextend name of sram4k block with _wb suffix
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 19:14:53 +0000 (19:14 +0000)]
extend name of sram4k block with _wb suffix

6 months agounit test: pass bool mmu
Tobias Platen [Fri, 5 Mar 2021 16:47:53 +0000 (17:47 +0100)]
unit test: pass bool mmu

6 months agoadd comments and more stub functions
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 16:33:05 +0000 (16:33 +0000)]
add comments and more stub functions

6 months agoadd segment_check function, plus quick test.
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 16:16:41 +0000 (16:16 +0000)]
add segment_check function, plus quick test.
also fix order because SelectableInt deals in BE

6 months agoadd decode_prte function to RADIX
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 14:20:21 +0000 (14:20 +0000)]
add decode_prte function to RADIX

6 months agoadd trivial LD/ST redirectors into RADIX ISACaller
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 13:53:47 +0000 (13:53 +0000)]
add trivial LD/ST redirectors into RADIX ISACaller

6 months agoMove writing of the PC state register to the issue FSM
Cesar Strauss [Fri, 5 Mar 2021 12:01:34 +0000 (09:01 -0300)]
Move writing of the PC state register to the issue FSM

Before fetch, update the PC state register with the NIA, unless PC was
modified in execute.

6 months agoMove the wait on "core stop" out of fetch, and into issue
Cesar Strauss [Fri, 5 Mar 2021 10:57:01 +0000 (07:57 -0300)]
Move the wait on "core stop" out of fetch, and into issue

During a Simple-V loop, the fetch FSM will sit idle, unable to pause the
execution. A good alternate place to wait on "core stop" release is at
instruction end, before either fetching a new instruction, or going back
to the SV loop.

On system initialization, we need to pause as well, since there was no
instruction which ended previously.

6 months agoremoving --user from make develop
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 21:32:59 +0000 (21:32 +0000)]
removing --user from make develop

6 months agowhitespace
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 21:26:47 +0000 (21:26 +0000)]
whitespace

6 months agoupdate test_caller_radix.py
Tobias Platen [Thu, 4 Mar 2021 19:16:50 +0000 (20:16 +0100)]
update test_caller_radix.py

6 months agoISACaller: add option mmu
Tobias Platen [Thu, 4 Mar 2021 19:05:44 +0000 (20:05 +0100)]
ISACaller: add option mmu

6 months agowhoops microwatt already allocates SPR 720
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 18:15:40 +0000 (18:15 +0000)]
whoops microwatt already allocates SPR 720

6 months agoadd comments from gem5-experimental mmu
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 18:06:57 +0000 (18:06 +0000)]
add comments from gem5-experimental mmu

6 months agoadd cached pgtbl0/3
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 17:47:21 +0000 (17:47 +0000)]
add cached pgtbl0/3

6 months agoadd two functions for checking permissions, to be based on microwatt
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 17:39:53 +0000 (17:39 +0000)]
add two functions for checking permissions, to be based on microwatt

6 months agoadd RADIX skeleton and unit test
Tobias Platen [Wed, 3 Mar 2021 18:23:01 +0000 (19:23 +0100)]
add RADIX skeleton and unit test

6 months agoadd debug strings
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 17:45:55 +0000 (17:45 +0000)]
add debug strings

6 months agoremove singleton pattern
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 17:07:00 +0000 (17:07 +0000)]
remove singleton pattern

6 months agoadd pywriter Makefile entry
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 16:13:43 +0000 (16:13 +0000)]
add pywriter Makefile entry

6 months agocur_state is a global, does not have to be passed as a parameter in TestIssuer
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 14:28:53 +0000 (14:28 +0000)]
cur_state is a global, does not have to be passed as a parameter in TestIssuer

6 months agoset SVSTATE in TestRunner using new TestIssuer.svstate_i
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 14:18:46 +0000 (14:18 +0000)]
set SVSTATE in TestRunner using new TestIssuer.svstate_i

6 months agoadd svstate_i to TestIssuer which mirrors pc_i
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 14:15:18 +0000 (14:15 +0000)]
add svstate_i to TestIssuer which mirrors pc_i

6 months agocomment out changing SPR 720 because 720 is not supported by the MMU pipe
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 16:32:20 +0000 (16:32 +0000)]
comment out changing SPR 720 because 720 is not supported by the MMU pipe

6 months agosort out SPR setting in MMU
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 16:24:50 +0000 (16:24 +0000)]
sort out SPR setting in MMU

6 months agooperating correctly, not directing MMU SPRs to SPR Pipeline,
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 13:55:17 +0000 (13:55 +0000)]
operating correctly, not directing MMU SPRs to SPR Pipeline,
failure with PC likely due to ISACaller not supporting SPR 720

6 months agomust always set ok for writing out data otherwise it never hits regfile
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 12:49:18 +0000 (12:49 +0000)]
must always set ok for writing out data otherwise it never hits regfile
(and causes compunit to fail)

6 months agoRevert "fix Bug 607 - unnecessary code added related to MMU in PowerDecoder2"
Luke Kenneth Casson Leighton [Mon, 1 Mar 2021 19:35:31 +0000 (19:35 +0000)]
Revert "fix Bug 607 - unnecessary code added related to MMU in PowerDecoder2"

This reverts commit 0b31706069567c4124ebac487f238342cc540d79.

6 months agomove SVP64 RM decoder to separate module
Luke Kenneth Casson Leighton [Mon, 1 Mar 2021 15:40:31 +0000 (15:40 +0000)]
move SVP64 RM decoder to separate module

6 months agoadd additional SVP64 RM decode fields
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 18:36:22 +0000 (18:36 +0000)]
add additional SVP64 RM decode fields

6 months agostart on SVP64 RM Mode decoder
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 17:19:18 +0000 (17:19 +0000)]
start on SVP64 RM Mode decoder

6 months agomore SVP64 enums
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 16:29:54 +0000 (16:29 +0000)]
more SVP64 enums

6 months agoadd SVP64 RM sub-field enums
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 16:21:42 +0000 (16:21 +0000)]
add SVP64 RM sub-field enums

6 months agomove SVP64 Extra decoders to separate module
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:47:25 +0000 (14:47 +0000)]
move SVP64 Extra decoders to separate module

6 months agofix syntax error
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:43:09 +0000 (14:43 +0000)]
fix syntax error

6 months agomove SVP64PrefixDecoder to separate module
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:42:35 +0000 (14:42 +0000)]
move SVP64PrefixDecoder to separate module

6 months agoadd PowerDecoder.no_in_vec
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:42:12 +0000 (14:42 +0000)]
add PowerDecoder.no_in_vec

6 months agoadd svp64_instrs to power_svp64
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 12:19:52 +0000 (12:19 +0000)]
add svp64_instrs to power_svp64

6 months agofix Bug 607 - unnecessary code added related to MMU in PowerDecoder2
Tobias Platen [Sun, 28 Feb 2021 11:25:51 +0000 (12:25 +0100)]
fix Bug 607 - unnecessary code added related to MMU in PowerDecoder2

6 months agofix Bug 603 - use SPR names/numbers from sprs.csv
Tobias Platen [Sun, 28 Feb 2021 11:14:31 +0000 (12:14 +0100)]
fix Bug 603 - use SPR names/numbers from sprs.csv

6 months agouse PowerDecoder2.no_out_vec instead of manual vector detection in ISACaller
Luke Kenneth Casson Leighton [Sat, 27 Feb 2021 12:43:35 +0000 (12:43 +0000)]
use PowerDecoder2.no_out_vec instead of manual vector detection in ISACaller

6 months agoadd corresponding VL=0 unit test as from 161b7d67b in svp64_cases.py
Luke Kenneth Casson Leighton [Sat, 27 Feb 2021 12:38:15 +0000 (12:38 +0000)]
add corresponding VL=0 unit test as from 161b7d67b in svp64_cases.py

6 months agoAdd traces for the new FSM
Cesar Strauss [Sat, 27 Feb 2021 09:25:47 +0000 (06:25 -0300)]
Add traces for the new FSM

6 months agoAdd a vector case with VL == 0
Cesar Strauss [Fri, 26 Feb 2021 21:45:18 +0000 (18:45 -0300)]
Add a vector case with VL == 0

This will be useful for testing the fetch <-> issue loop.

6 months agocomment on CoreState
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:50:04 +0000 (13:50 +0000)]
comment on CoreState

6 months agoremove sv_changed input to fetch_fsm, add it to issue_fsm TestIssuer
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:46:22 +0000 (13:46 +0000)]
remove sv_changed input to fetch_fsm, add it to issue_fsm TestIssuer

6 months agomoving new_svstate and update_svstate into issue FSM TestIssuer
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:40:22 +0000 (13:40 +0000)]
moving new_svstate and update_svstate into issue FSM TestIssuer

6 months agomove fetch_insn_o into issue_fsm TestIssuer
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:34:59 +0000 (13:34 +0000)]
move fetch_insn_o into issue_fsm TestIssuer

6 months agoadd comments, missing that VL loop ends after execution if no_out_vec set
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:21:31 +0000 (13:21 +0000)]
add comments, missing that VL loop ends after execution if no_out_vec set
SVP64 TestIssuer

6 months agoImplement a decode/issue FSM between fetch and execute
Cesar Strauss [Fri, 26 Feb 2021 10:47:03 +0000 (07:47 -0300)]
Implement a decode/issue FSM between fetch and execute

The idea is for it to:
* keep looping "fetch" while VL==0 on a vector instruction.
* keep looping "execute" while SRCSTEP != VL-1.
* unless PC/SVSTATE was modified by "execute", in that case do go back
to "fetch".
* update PC and SRCSTEP accordingly.

6 months agowb_get: write outputs to seperate logfile too
Tobias Platen [Wed, 24 Feb 2021 18:43:23 +0000 (19:43 +0100)]
wb_get: write outputs to seperate logfile too

6 months agoupdate mmu testcase
Tobias Platen [Wed, 24 Feb 2021 18:40:53 +0000 (19:40 +0100)]
update mmu testcase

6 months agotest_runner.py: add needed imports
Tobias Platen [Wed, 24 Feb 2021 18:39:59 +0000 (19:39 +0100)]
test_runner.py: add needed imports

6 months agoadd comments explaining split
Luke Kenneth Casson Leighton [Wed, 24 Feb 2021 15:22:20 +0000 (15:22 +0000)]
add comments explaining split
https://bugs.libre-soc.org/show_bug.cgi?id=606

6 months agomove DecodeCROut/In (at last) out of PowerDecoderSubset and into PowerDecoder2
Luke Kenneth Casson Leighton [Wed, 24 Feb 2021 15:19:16 +0000 (15:19 +0000)]
move DecodeCROut/In (at last) out of PowerDecoderSubset and into PowerDecoder2
https://bugs.libre-soc.org/show_bug.cgi?id=606

6 months agostart making write_cr0 independent of DecodeCROut
Luke Kenneth Casson Leighton [Wed, 24 Feb 2021 15:08:32 +0000 (15:08 +0000)]
start making write_cr0 independent of DecodeCROut
https://bugs.libre-soc.org/show_bug.cgi?id=606

6 months agodeduplicate
Tobias Platen [Tue, 23 Feb 2021 18:20:15 +0000 (19:20 +0100)]
deduplicate