soc.git
15 months agoAdd code, commented-out, for TRAP so as to not break test_caller.py
colepoirier [Sat, 20 Jun 2020 01:30:54 +0000 (18:30 -0700)]
Add code, commented-out, for TRAP so as to not break test_caller.py

15 months agowhitespace update
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 21:30:01 +0000 (22:30 +0100)]
whitespace update

15 months agomove trunc_div and trunc_rem to nmutil
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 21:16:55 +0000 (22:16 +0100)]
move trunc_div and trunc_rem to nmutil

15 months agoadd comments on trunc_div and trunc_rem
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 20:29:30 +0000 (21:29 +0100)]
add comments on trunc_div and trunc_rem

15 months agoadd divide-by-zero test to test_div_sim.py
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 16:49:32 +0000 (17:49 +0100)]
add divide-by-zero test to test_div_sim.py

15 months agoadd docstring comment for SelectableInt
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:39:04 +0000 (15:39 +0100)]
add docstring comment for SelectableInt

15 months agoadd test_0_moduw and correct name to trunc_rem
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:30:45 +0000 (15:30 +0100)]
add test_0_moduw and correct name to trunc_rem

15 months agoadd abs SelectableInt unit test (very quick)
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:27:25 +0000 (15:27 +0100)]
add abs SelectableInt unit test (very quick)

15 months agoadd SelectableInt.abs
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:25:04 +0000 (15:25 +0100)]
add SelectableInt.abs
https://bugs.libre-soc.org/show_bug.cgi?id=324#c19

15 months agoadd another bad hack in parser.py which identifies "undefined" slice assignment
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:21:15 +0000 (15:21 +0100)]
add another bad hack in parser.py which identifies "undefined" slice assignment

15 months agoadd in really bad hack which calls trunc_div or trunc_mod
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:14:37 +0000 (15:14 +0100)]
add in really bad hack which calls trunc_div or trunc_mod
https://bugs.libre-soc.org/show_bug.cgi?id=324#c16

15 months agoadd trunc_div and trunch_rem to decoder helpers
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:03:28 +0000 (15:03 +0100)]
add trunc_div and trunch_rem to decoder helpers
https://bugs.libre-soc.org/show_bug.cgi?id=324

15 months agoauto-assign needs to use concat / selectconcat
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 13:01:39 +0000 (14:01 +0100)]
auto-assign needs to use concat / selectconcat

15 months agowhoops detected page name wrong, for special case fixedshift
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 12:50:13 +0000 (13:50 +0100)]
whoops detected page name wrong, for special case fixedshift

15 months agobit of a mess. getting carry recognised and output for shiftrot
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 12:45:01 +0000 (13:45 +0100)]
bit of a mess.  getting carry recognised and output for shiftrot
was interfering with fixedarith carry "implicit" computation.
had to special-case this in pywriter.py and parser.py

15 months agoadd auto-assign mode detecting uninitialised variable slices
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 12:08:18 +0000 (13:08 +0100)]
add auto-assign mode detecting uninitialised variable slices

15 months agodiv needs to be floordiv
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 10:36:12 +0000 (11:36 +0100)]
div needs to be floordiv

15 months agoadd true and floor div to SelectableInt
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 09:54:14 +0000 (10:54 +0100)]
add true and floor div to SelectableInt

15 months agoadd simulator test for divw
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 09:49:20 +0000 (10:49 +0100)]
add simulator test for divw

15 months agodo mix-in for test_sim.py so that jacob can write some div tests without
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 02:06:41 +0000 (03:06 +0100)]
do mix-in for test_sim.py so that jacob can write some div tests without
having to run all the other ones

15 months agoadd TODO comments to upgrade L0CacheBuffer to a new TestMemoryLoadStoreUnit
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 02:00:58 +0000 (03:00 +0100)]
add TODO comments to upgrade L0CacheBuffer to a new TestMemoryLoadStoreUnit

15 months agoparameterise LoadStoreUnitInterface to be expandable
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 01:44:24 +0000 (02:44 +0100)]
parameterise LoadStoreUnitInterface to be expandable

15 months agodiv pipe completed except for tests
Jacob Lifshay [Thu, 18 Jun 2020 23:11:10 +0000 (16:11 -0700)]
div pipe completed except for tests

15 months agofinish code to calculate the 64-bit output of the div pipeline
Jacob Lifshay [Thu, 18 Jun 2020 22:47:12 +0000 (15:47 -0700)]
finish code to calculate the 64-bit output of the div pipeline

15 months agoactually remove todo comment for manually checking against instruction models
Jacob Lifshay [Thu, 18 Jun 2020 22:32:50 +0000 (15:32 -0700)]
actually remove todo comment for manually checking against instruction models

15 months agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Jacob Lifshay [Thu, 18 Jun 2020 22:31:14 +0000 (15:31 -0700)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

15 months agofix bug and manually check div overflow code against instruction models
Jacob Lifshay [Thu, 18 Jun 2020 22:27:39 +0000 (15:27 -0700)]
fix bug and manually check div overflow code against instruction models

15 months agoenable general test cases in test_issuer
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 17:05:59 +0000 (18:05 +0100)]
enable general test cases in test_issuer

15 months agogot loop example operational by noting when PC fastreg changed
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 17:05:40 +0000 (18:05 +0100)]
got loop example operational by noting when PC fastreg changed

16 months agouse different way to pass instructions to test_issuer ISACaller
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 10:29:29 +0000 (11:29 +0100)]
use different way to pass instructions to test_issuer ISACaller

16 months agodebugging test_issuer.py general test cases
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 10:26:35 +0000 (11:26 +0100)]
debugging test_issuer.py general test cases

16 months agoget instructions immediately from assembly code
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 10:26:10 +0000 (11:26 +0100)]
get instructions immediately from assembly code

16 months agomove test_sim.py unit tests to different class (split)
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 10:06:16 +0000 (11:06 +0100)]
move test_sim.py unit tests to different class (split)

16 months agoslightly hacky way to keep an eye on the PC
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 09:58:18 +0000 (10:58 +0100)]
slightly hacky way to keep an eye on the PC

16 months agowhoops generate core ilang not TestIssuer
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 09:52:06 +0000 (10:52 +0100)]
whoops generate core ilang not TestIssuer

16 months agouse while / exception in test_compunit loop
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 09:50:47 +0000 (10:50 +0100)]
use while / exception in test_compunit loop

16 months agoinvestigating mtocrf/mtcrf issue
Luke Kenneth Casson Leighton [Thu, 18 Jun 2020 09:45:04 +0000 (10:45 +0100)]
investigating mtocrf/mtcrf issue

16 months agoworking on adding rest of stage classes for div pipeline
Jacob Lifshay [Thu, 18 Jun 2020 02:56:07 +0000 (19:56 -0700)]
working on adding rest of stage classes for div pipeline

16 months agoadd bug reference to mtocrf/mtcrf name decoding
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 19:43:08 +0000 (20:43 +0100)]
add bug reference to mtocrf/mtcrf name decoding

16 months agodecoding assembly instruction name, move to separate function
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 19:39:21 +0000 (20:39 +0100)]
decoding assembly instruction name, move to separate function

16 months agogetting sim instruction decoder to reproduce asm instruction disassembly
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 19:20:35 +0000 (20:20 +0100)]
getting sim instruction decoder to reproduce asm instruction disassembly

16 months agoupdate submodule
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 17:32:12 +0000 (18:32 +0100)]
update submodule

16 months agoadd comment/assembly decode in power enums
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 17:31:40 +0000 (18:31 +0100)]
add comment/assembly decode in power enums

16 months agoupdate test_sim.py to do a simple execution loop: decode-execute-decode-execute
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 16:46:33 +0000 (17:46 +0100)]
update test_sim.py to do a simple execution loop: decode-execute-decode-execute

16 months agoadd loop example, required a bit of munging.
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 16:10:21 +0000 (17:10 +0100)]
add loop example, required a bit of munging.

16 months agoget fu compunit test to use ISACaller instruction-memory
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 14:55:04 +0000 (15:55 +0100)]
get fu compunit test to use ISACaller instruction-memory

16 months agogot fed up of adding arguments to ISACaller / ISA, use *args and **kwargs
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 14:46:04 +0000 (15:46 +0100)]
got fed up of adding arguments to ISACaller / ISA, use *args and **kwargs

16 months agosplit execute and setup of ISACaller instruction execution
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 14:40:46 +0000 (15:40 +0100)]
split execute and setup of ISACaller instruction execution
into two phases

16 months agocomment ISACaller setup
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 14:24:27 +0000 (15:24 +0100)]
comment ISACaller setup

16 months agostart to add in independent execution into ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 14:20:35 +0000 (15:20 +0100)]
start to add in independent execution into ISACaller

16 months agoadd a fake program counter to ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 13:42:47 +0000 (14:42 +0100)]
add a fake program counter to ISACaller

16 months agouse an independent power decoder in ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 13:42:33 +0000 (14:42 +0100)]
use an independent power decoder in ISACaller

16 months agoadd "respect_pc" boolean to ISACaller
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 13:20:06 +0000 (14:20 +0100)]
add "respect_pc" boolean to ISACaller

16 months agoadd optional instruction memory
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 13:07:59 +0000 (14:07 +0100)]
add optional instruction memory

16 months agosplit out TestIssuer into separate module
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 11:17:31 +0000 (12:17 +0100)]
split out TestIssuer into separate module

16 months agoremove unneeded yield
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 11:08:08 +0000 (12:08 +0100)]
remove unneeded yield

16 months agoenable all tests again in test_core.py and test_issuer.py
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 05:41:09 +0000 (06:41 +0100)]
enable all tests again in test_core.py and test_issuer.py

16 months agogot test_issuer FSM operating. bit of a hack
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 05:39:53 +0000 (06:39 +0100)]
got test_issuer FSM operating.  bit of a hack

16 months agodebugging test_issuer, getting FSM working
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 04:42:10 +0000 (05:42 +0100)]
debugging test_issuer, getting FSM working

16 months agooutput to issuer_simulator.vcd
Luke Kenneth Casson Leighton [Wed, 17 Jun 2020 04:14:40 +0000 (05:14 +0100)]
output to issuer_simulator.vcd

16 months agoadd first version unit test for TestIssuer
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 18:33:05 +0000 (19:33 +0100)]
add first version unit test for TestIssuer

16 months agoreduce instruction depth to 6 bits in TestIssuer
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 18:32:46 +0000 (19:32 +0100)]
reduce instruction depth to 6 bits in TestIssuer

16 months agomove debug statements to check function
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 18:21:20 +0000 (19:21 +0100)]
move debug statements to check function

16 months agohack LD/ST ad/st together, allow PC to be set externally
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 18:12:01 +0000 (19:12 +0100)]
hack LD/ST ad/st together, allow PC to be set externally

16 months agomove check regs in simple core to separate function
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 17:29:37 +0000 (18:29 +0100)]
move check regs in simple core to separate function

16 months agomove test core reg set up into separate function
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 17:24:43 +0000 (18:24 +0100)]
move test core reg set up into separate function

16 months agoset up a TestIssuer class with a FSM for doing instruction issue to simple core
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 17:18:20 +0000 (18:18 +0100)]
set up a TestIssuer class with a FSM for doing instruction issue to simple core

16 months agoadd ports to TestMemory
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 17:16:53 +0000 (18:16 +0100)]
add ports to TestMemory

16 months agoadd beginnings of TestIssuer class, to issue instructions to simple core
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 14:39:03 +0000 (15:39 +0100)]
add beginnings of TestIssuer class, to issue instructions to simple core

16 months agoweird: adding TestMemory with no port causes nmigen recursion-exceeded
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 13:00:12 +0000 (14:00 +0100)]
weird: adding TestMemory with no port causes nmigen recursion-exceeded

16 months agorefer to signals directly in Test Core
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 12:57:41 +0000 (13:57 +0100)]
refer to signals directly in Test Core

16 months agoadd test instruction memory SRAM
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 12:41:17 +0000 (13:41 +0100)]
add test instruction memory SRAM

16 months agoupdate popcount docstring
Luke Kenneth Casson Leighton [Tue, 16 Jun 2020 11:15:42 +0000 (12:15 +0100)]
update popcount docstring

16 months agostart trying to fill in some comments in Minerva L1 cache code
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 23:52:30 +0000 (00:52 +0100)]
start trying to fill in some comments in Minerva L1 cache code

16 months agowhitespace cleanup
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 20:56:24 +0000 (21:56 +0100)]
whitespace cleanup

16 months agoimports and syntax errors fixed (found test_cache.py)
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 20:55:39 +0000 (21:55 +0100)]
imports and syntax errors fixed (found test_cache.py)

16 months agomore whitespace
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 19:53:43 +0000 (20:53 +0100)]
more whitespace

16 months agomore whitespace on minerva (no unit tests, so cannot check it)
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 19:51:56 +0000 (20:51 +0100)]
more whitespace on minerva (no unit tests, so cannot check it)

16 months agowhitespace cleanup, remove minerva DataSelector class
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 19:46:25 +0000 (20:46 +0100)]
whitespace cleanup, remove minerva DataSelector class

16 months agohave to set up addr/st rel-go link before setting up nmigen Simulator
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 19:05:32 +0000 (20:05 +0100)]
have to set up addr/st rel-go link before setting up nmigen Simulator
LD/ST now works in test_core.py

16 months agoadd in memory setup/check but disable LDST Unit Tests in core.py
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 14:54:49 +0000 (15:54 +0100)]
add in memory setup/check but disable LDST Unit Tests in core.py
LDST is still busy after 2nd instruction, bug needs tracking down

16 months agomove setup/check memory into helper functions for use in test_core.py
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 14:40:36 +0000 (15:40 +0100)]
move setup/check memory into helper functions for use in test_core.py

16 months agowhoops LDSTCompUnit was identified as a Function.ALU not a Function.LDST
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 14:33:35 +0000 (15:33 +0100)]
whoops LDSTCompUnit was identified as a Function.ALU not a Function.LDST

16 months agoadd in TstL0CacheBuffer but disable temporarily
Luke Kenneth Casson Leighton [Mon, 15 Jun 2020 14:26:05 +0000 (15:26 +0100)]
add in TstL0CacheBuffer but disable temporarily

16 months agoadd optional LDSTFunctionUnit to compunits
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 20:22:04 +0000 (21:22 +0100)]
add optional LDSTFunctionUnit to compunits

16 months agounit tests showing byte-reverse works
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 17:08:23 +0000 (18:08 +0100)]
unit tests showing byte-reverse works

16 months agoadd sim-qemu test for byte-reversed LD/ST
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 16:51:17 +0000 (17:51 +0100)]
add sim-qemu test for byte-reversed LD/ST

16 months agoadd in byte-reverse from op PowerDecode2 field
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 16:40:20 +0000 (17:40 +0100)]
add in byte-reverse from op PowerDecode2 field

16 months agoerror in address width (truncated) in setting up L0CacheBuffer
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 14:50:35 +0000 (15:50 +0100)]
error in address width (truncated) in setting up L0CacheBuffer

16 months agoerror in naming that ended up in gtkwave from a proxy
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 14:49:27 +0000 (15:49 +0100)]
error in naming that ended up in gtkwave from a proxy

16 months agoadd another LD/ST example to qemu-sim test,
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 14:37:30 +0000 (15:37 +0100)]
add another LD/ST example to qemu-sim test,
mirroring the one in ldst compunit test

16 months agoadd byte-reversal on LD and ST in L0CacheBuffer
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 14:36:57 +0000 (15:36 +0100)]
add byte-reversal on LD and ST in L0CacheBuffer

16 months agoreasonably certain that the careful and slow use of little-endian data read/write
Luke Kenneth Casson Leighton [Sun, 14 Jun 2020 14:00:12 +0000 (15:00 +0100)]
reasonably certain that the careful and slow use of little-endian data read/write
and explicit endian-ness swapping is correct, when comparing the
simulator against qemu

16 months agoWait for all active rel signals to be high, and only then pulse go.
Cesar Strauss [Sat, 13 Jun 2020 23:51:14 +0000 (20:51 -0300)]
Wait for all active rel signals to be high, and only then pulse go.

It's the best we can do without parallel processes.

16 months agofirst cut at qemu memory dump and compare
Luke Kenneth Casson Leighton [Fri, 12 Jun 2020 18:44:09 +0000 (19:44 +0100)]
first cut at qemu memory dump and compare

16 months agonote possible BE/LE mode needed for memory reads/writes
Luke Kenneth Casson Leighton [Fri, 12 Jun 2020 15:28:32 +0000 (16:28 +0100)]
note possible BE/LE mode needed for memory reads/writes

16 months agoupdate ld/st test to see what is going on
Luke Kenneth Casson Leighton [Fri, 12 Jun 2020 14:58:21 +0000 (15:58 +0100)]
update ld/st test to see what is going on

16 months agotracking down what looks like an error in the Simulator Mem ld/st
Luke Kenneth Casson Leighton [Fri, 12 Jun 2020 14:41:16 +0000 (15:41 +0100)]
tracking down what looks like an error in the Simulator Mem ld/st

16 months agodebug printout of sim and hardware memory, shows mismatch of depths
Luke Kenneth Casson Leighton [Fri, 12 Jun 2020 14:03:10 +0000 (15:03 +0100)]
debug printout of sim and hardware memory, shows mismatch of depths

16 months agouse ALUHelpers in LDSTCompUnit test
Luke Kenneth Casson Leighton [Fri, 12 Jun 2020 13:46:25 +0000 (14:46 +0100)]
use ALUHelpers in LDSTCompUnit test