soc.git
12 months agoadd detection and disable of Instruction Wishbone based on JTAG command
Luke Kenneth Casson Leighton [Thu, 22 Oct 2020 15:50:37 +0000 (16:50 +0100)]
add detection and disable of Instruction Wishbone based on JTAG command

12 months agoadd detection and disable of LoadStore Wishbone based on JTAG command
Luke Kenneth Casson Leighton [Thu, 22 Oct 2020 15:49:11 +0000 (16:49 +0100)]
add detection and disable of LoadStore Wishbone based on JTAG command

12 months agoadd JTAG enable/disable of wishbone to TestIssuer
Luke Kenneth Casson Leighton [Thu, 22 Oct 2020 15:47:23 +0000 (16:47 +0100)]
add JTAG enable/disable of wishbone to TestIssuer

12 months agoadd means to JTAG interface to enable/disable "stuff" currently just WB
Luke Kenneth Casson Leighton [Thu, 22 Oct 2020 13:13:11 +0000 (14:13 +0100)]
add means to JTAG interface to enable/disable "stuff"  currently just WB

12 months agoversa_ecp5 adds ability to build and load for ulx3s85f, fixes testgpio
Cole Poirier [Wed, 21 Oct 2020 21:26:10 +0000 (14:26 -0700)]
versa_ecp5 adds ability to build and load for ulx3s85f, fixes testgpio
feature

12 months agofix up asserts (check correct pads/cores)
Luke Kenneth Casson Leighton [Wed, 21 Oct 2020 16:47:15 +0000 (17:47 +0100)]
fix up asserts (check correct pads/cores)
https://bugs.libre-soc.org/show_bug.cgi?id=511#c12

12 months agos/alu/fsm/g
Tobias Platen [Tue, 20 Oct 2020 17:42:50 +0000 (19:42 +0200)]
s/alu/fsm/g

12 months agotest case for FSMMMUStage
Tobias Platen [Tue, 20 Oct 2020 16:41:39 +0000 (18:41 +0200)]
test case for FSMMMUStage

12 months agouse random.seed to generate repro cases of the two different failure
Cole Poirier [Sun, 18 Oct 2020 00:39:22 +0000 (17:39 -0700)]
use random.seed to generate repro cases of the two different failure
modes of test_icache()

12 months agoexperiment swapping dummy trap stage over to input
Luke Kenneth Casson Leighton [Fri, 16 Oct 2020 19:51:09 +0000 (20:51 +0100)]
experiment swapping dummy trap stage over to input

12 months agore-enable tests
Luke Kenneth Casson Leighton [Fri, 16 Oct 2020 18:29:16 +0000 (19:29 +0100)]
re-enable tests

12 months agomanually run coresync clock for test issuer
Luke Kenneth Casson Leighton [Fri, 16 Oct 2020 18:28:36 +0000 (19:28 +0100)]
manually run coresync clock for test issuer

12 months agoset defaults in pspec
Luke Kenneth Casson Leighton [Fri, 16 Oct 2020 18:26:05 +0000 (19:26 +0100)]
set defaults in pspec

12 months agoupdate submodule
Luke Kenneth Casson Leighton [Fri, 16 Oct 2020 18:14:50 +0000 (19:14 +0100)]
update submodule

12 months agoadd extra (test dummy stage in trap to see if combinatorial latency is reduced
Luke Kenneth Casson Leighton [Fri, 16 Oct 2020 18:09:40 +0000 (19:09 +0100)]
add extra (test dummy stage in trap to see if combinatorial latency is reduced

12 months agoadd LGPLv3+ notice and add copyright holders
Luke Kenneth Casson Leighton [Fri, 16 Oct 2020 18:08:24 +0000 (19:08 +0100)]
add LGPLv3+ notice and add copyright holders

12 months agoadd commented-out connection to JTAG in ECP5 litex
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 20:43:22 +0000 (21:43 +0100)]
add commented-out connection to JTAG in ECP5 litex

12 months agowrong pspec variable in selecting pll clock
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 17:11:11 +0000 (18:11 +0100)]
wrong pspec variable in selecting pll clock

12 months agosorting out missing clock somewhere
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 17:05:44 +0000 (18:05 +0100)]
sorting out missing clock somewhere

12 months agouse "enable" and set default actions in getopt
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 16:43:27 +0000 (17:43 +0100)]
use "enable" and set default actions in getopt

12 months agoadd extra variant to litex core
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 14:59:21 +0000 (15:59 +0100)]
add extra variant to litex core

12 months agosyntax error
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 14:58:09 +0000 (15:58 +0100)]
syntax error

12 months agodisable gpio in litex core
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 14:53:00 +0000 (15:53 +0100)]
disable gpio in litex core

12 months agoenable/disable litex irqs based on variant name
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 12:25:49 +0000 (13:25 +0100)]
enable/disable litex irqs based on variant name

12 months agoMakefile develop, when running setup.py develop specify --user so admin
Cole Poirier [Wed, 14 Oct 2020 00:37:32 +0000 (17:37 -0700)]
Makefile develop, when running setup.py develop specify --user so admin
access is not needed

12 months agoissuer_verilog.py update to use commandline args using argparse, fix
Cole Poirier [Wed, 14 Oct 2020 00:04:43 +0000 (17:04 -0700)]
issuer_verilog.py update to use commandline args using argparse, fix
formatting

12 months agomove pia from install_requires to test_requires
Cole Poirier [Tue, 13 Oct 2020 17:21:53 +0000 (10:21 -0700)]
move pia from install_requires to test_requires

12 months agolitex/florent/versa_ecp5.py add arg --fpga [versa_ecp5|ulx3s85f] default
Cole Poirier [Mon, 12 Oct 2020 23:30:10 +0000 (16:30 -0700)]
litex/florent/versa_ecp5.py add arg --fpga [versa_ecp5|ulx3s85f] default
of versa_ecp5, to build for different fpga targets, fix whitespace,
delete ulx3s85f.py as it's no longer needed

12 months agofix ModuleNotFound/Import errors found when running pytest, just due to
Cole Poirier [Mon, 12 Oct 2020 22:24:03 +0000 (15:24 -0700)]
fix ModuleNotFound/Import errors found when running pytest, just due to
things being renamed and not kept in sync

12 months agoupdate gitlab ci
Tobias Platen [Mon, 12 Oct 2020 20:00:40 +0000 (20:00 +0000)]
update gitlab ci

12 months agoadd tested working fpga compile/build/load file for ulxs3s LFE5U-85F as ulx3s85f...
Cole Poirier [Mon, 12 Oct 2020 19:36:20 +0000 (12:36 -0700)]
add tested working fpga compile/build/load file for ulxs3s LFE5U-85F as ulx3s85f.py based on versa_ecp5.py

12 months agoadd way to bypass PLL for ECP5 and sim
Luke Kenneth Casson Leighton [Sun, 11 Oct 2020 15:01:58 +0000 (16:01 +0100)]
add way to bypass PLL for ECP5 and sim

12 months agocomment out XICS/GPIO interrupt test, causes ECP5 litex build to fail
Luke Kenneth Casson Leighton [Sun, 11 Oct 2020 13:57:38 +0000 (14:57 +0100)]
comment out XICS/GPIO interrupt test, causes ECP5 litex build to fail
(input incorrectly detected as output)

12 months agorecord commands for building ECP5
Luke Kenneth Casson Leighton [Sun, 11 Oct 2020 13:50:11 +0000 (14:50 +0100)]
record commands for building ECP5

12 months agolitex sim.py operational
Luke Kenneth Casson Leighton [Sun, 11 Oct 2020 13:19:55 +0000 (14:19 +0100)]
litex sim.py operational

12 months agoflorent/versa_ecp5.py remove uneccessary imports, specify actual import
Cole Poirier [Sat, 10 Oct 2020 20:38:11 +0000 (13:38 -0700)]
florent/versa_ecp5.py remove uneccessary imports, specify actual import
instead of evil 'import *'

12 months agoadd debug start/stop to firmware_upload script
Luke Kenneth Casson Leighton [Sat, 10 Oct 2020 16:12:54 +0000 (17:12 +0100)]
add debug start/stop to firmware_upload script

12 months agoadd DMI status / reset to firmware upload script
Luke Kenneth Casson Leighton [Sat, 10 Oct 2020 14:45:59 +0000 (15:45 +0100)]
add DMI status / reset to firmware upload script

12 months agoadd first version of firmware uploader
Luke Kenneth Casson Leighton [Sat, 10 Oct 2020 14:13:38 +0000 (15:13 +0100)]
add first version of firmware uploader

12 months agoupdate submodule
Jacob Lifshay [Fri, 9 Oct 2020 23:33:39 +0000 (16:33 -0700)]
update submodule

12 months agoupdate submodule
Jacob Lifshay [Fri, 9 Oct 2020 22:57:01 +0000 (15:57 -0700)]
update submodule

12 months agouse libresoc version of c4m-jtag repo
Luke Kenneth Casson Leighton [Fri, 9 Oct 2020 13:16:20 +0000 (14:16 +0100)]
use libresoc version of c4m-jtag repo

12 months agosubmodule update
Luke Kenneth Casson Leighton [Fri, 9 Oct 2020 11:06:48 +0000 (12:06 +0100)]
submodule update

12 months agodrop in "undefined" function into ISAcaller namespace
Luke Kenneth Casson Leighton [Fri, 9 Oct 2020 10:51:18 +0000 (11:51 +0100)]
drop in "undefined" function into ISAcaller namespace

12 months agorename undef to undefined (preserving the fact that it is a function)
Luke Kenneth Casson Leighton [Fri, 9 Oct 2020 10:34:29 +0000 (11:34 +0100)]
rename undef to undefined (preserving the fact that it is a function)

12 months agomissing yields in JTAG pads test to allow settling
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 22:36:35 +0000 (23:36 +0100)]
missing yields in JTAG pads test to allow settling

12 months agofinish converting mul tests to use common code
Jacob Lifshay [Fri, 9 Oct 2020 04:19:07 +0000 (21:19 -0700)]
finish converting mul tests to use common code

12 months agoworking on splitting out common mul pipe test code
Jacob Lifshay [Fri, 9 Oct 2020 03:24:02 +0000 (20:24 -0700)]
working on splitting out common mul pipe test code

add initial tests for mul-add instructions

12 months agoadd carry handling to pia_res_to_output
Jacob Lifshay [Fri, 9 Oct 2020 03:23:17 +0000 (20:23 -0700)]
add carry handling to pia_res_to_output

12 months agomove pia_res_to_output to common test helpers
Jacob Lifshay [Fri, 9 Oct 2020 03:21:51 +0000 (20:21 -0700)]
move pia_res_to_output to common test helpers

12 months agomove mul pipe ilang test to separate file
Jacob Lifshay [Fri, 9 Oct 2020 00:45:32 +0000 (17:45 -0700)]
move mul pipe ilang test to separate file

12 months agoadd undef()
Jacob Lifshay [Fri, 9 Oct 2020 00:31:46 +0000 (17:31 -0700)]
add undef()

12 months agoupdate submodule
Jacob Lifshay [Fri, 9 Oct 2020 00:31:27 +0000 (17:31 -0700)]
update submodule

12 months agoupdate submodule
Jacob Lifshay [Thu, 8 Oct 2020 23:56:03 +0000 (16:56 -0700)]
update submodule

12 months agomissing yields in JTAG pads test to allow settling
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 22:34:23 +0000 (23:34 +0100)]
missing yields in JTAG pads test to allow settling

12 months agominor icache cleanup
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 22:27:02 +0000 (23:27 +0100)]
minor icache cleanup

12 months agosecond attempt at https://bugs.libre-soc.org/show_bug.cgi?id=485#c59,
Cole Poirier [Thu, 8 Oct 2020 20:31:51 +0000 (13:31 -0700)]
second attempt at https://bugs.libre-soc.org/show_bug.cgi?id=485#c59,
still not working properly, but it's closer

12 months agoremove singleton dict per https://bugs.libre-soc.org/show_bug.cgi?id=485#c58
Cole Poirier [Thu, 8 Oct 2020 19:28:02 +0000 (12:28 -0700)]
remove singleton dict per https://bugs.libre-soc.org/show_bug.cgi?id=485#c58

12 months agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Thu, 8 Oct 2020 18:16:40 +0000 (20:16 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

12 months agoadd WIP test_pipe_caller.py for mmu
Tobias Platen [Thu, 8 Oct 2020 17:39:06 +0000 (19:39 +0200)]
add WIP test_pipe_caller.py for mmu

12 months agoadd incoming PortInterface to be connected to LoadStoreCompUnit
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 17:13:50 +0000 (18:13 +0100)]
add incoming PortInterface to be connected to LoadStoreCompUnit

12 months agoJTAG boundary scan test 1st attempt
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 13:48:42 +0000 (14:48 +0100)]
JTAG boundary scan test 1st attempt

12 months agorework jtag test to use JTAG class not DMITAP
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 12:47:42 +0000 (13:47 +0100)]
rework jtag test to use JTAG class not DMITAP

12 months agosplit out jtag util functions to separate module
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 12:21:36 +0000 (13:21 +0100)]
split out jtag util functions to separate module

12 months agofirst attempt at 3) of
Cole Poirier [Thu, 8 Oct 2020 01:55:14 +0000 (18:55 -0700)]
first attempt at 3) of
https://bugs.libre-soc.org/show_bug.cgi?id=485#c41, not working yet

12 months agomodify wb_get per 1) of https://bugs.libre-soc.org/show_bug.cgi?id=485#c41
Cole Poirier [Thu, 8 Oct 2020 01:14:33 +0000 (18:14 -0700)]
modify wb_get per 1) of https://bugs.libre-soc.org/show_bug.cgi?id=485#c41

12 months agoconnect mmu_done, ldst_error, cache_paradox
Tobias Platen [Wed, 7 Oct 2020 19:52:44 +0000 (21:52 +0200)]
connect mmu_done, ldst_error, cache_paradox

12 months agomissing invert_in field from shiftrot input record
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 17:28:53 +0000 (18:28 +0100)]
missing invert_in field from shiftrot input record

12 months agogit submodule update
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 15:11:20 +0000 (16:11 +0100)]
git submodule update

12 months agoreorder / reorganise reset signals slightly
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 12:01:03 +0000 (13:01 +0100)]
reorder / reorganise reset signals slightly

12 months agofix div tests
Jacob Lifshay [Wed, 7 Oct 2020 04:01:15 +0000 (21:01 -0700)]
fix div tests

12 months agoupdate submodule
Jacob Lifshay [Wed, 7 Oct 2020 03:59:40 +0000 (20:59 -0700)]
update submodule

12 months agoFix forgotten test_pipe_caller changes from e0b4334c7d83dda41d5610239150079f30a2f713
Jacob Lifshay [Wed, 7 Oct 2020 01:36:06 +0000 (18:36 -0700)]
Fix forgotten test_pipe_caller changes from e0b4334c7d83dda41d5610239150079f30a2f713

12 months agoremove redunant signals
Tobias Platen [Tue, 6 Oct 2020 19:31:14 +0000 (21:31 +0200)]
remove redunant signals

12 months agoupdate comments on pimem.py
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 19:18:02 +0000 (20:18 +0100)]
update comments on pimem.py

12 months agotest_mmu_dcache_pi.py
Tobias Platen [Tue, 6 Oct 2020 18:51:34 +0000 (20:51 +0200)]
test_mmu_dcache_pi.py

12 months agocomments
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 17:18:09 +0000 (18:18 +0100)]
comments

12 months agoadd ports function to DummyPLL
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 17:09:48 +0000 (18:09 +0100)]
add ports function to DummyPLL

12 months agouse pdecode2.do not pdecode2.e in test_pipe_caller tests
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 17:08:16 +0000 (18:08 +0100)]
use pdecode2.do not pdecode2.e in test_pipe_caller tests

12 months agoskip Decode2ToOperand from PowerDecodeSubset
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 17:05:42 +0000 (18:05 +0100)]
skip Decode2ToOperand from PowerDecodeSubset

12 months agocomment SRR1 mem.exception
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 16:22:09 +0000 (17:22 +0100)]
comment SRR1 mem.exception

12 months agoadd SRR1 setting for LDST memory exception trap
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 15:58:14 +0000 (16:58 +0100)]
add SRR1 setting for LDST memory exception trap

12 months agopassing LDSTException over to Trap Pipeline
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 15:33:45 +0000 (16:33 +0100)]
passing LDSTException over to Trap Pipeline

12 months agoadd LDSTException decode/handling in PowerDecoder2
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 15:07:32 +0000 (16:07 +0100)]
add LDSTException decode/handling in PowerDecoder2

12 months agomake LDSTException fields added from list of fieldnames
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 15:05:36 +0000 (16:05 +0100)]
make LDSTException fields added from list of fieldnames

12 months agomove LDSTException to mem_types
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 14:48:17 +0000 (15:48 +0100)]
move LDSTException to mem_types

12 months agosubmodule update
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 13:06:36 +0000 (14:06 +0100)]
submodule update

12 months agoadd LDSTException to PortInterface
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 13:03:53 +0000 (14:03 +0100)]
add LDSTException to PortInterface

12 months agoadd sdr bypass routing via JTAG boundary scan
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 12:37:06 +0000 (13:37 +0100)]
add sdr bypass routing via JTAG boundary scan

12 months agoadd divde regression test
Jacob Lifshay [Tue, 6 Oct 2020 02:52:40 +0000 (19:52 -0700)]
add divde regression test

12 months agoupdate submodule
Jacob Lifshay [Tue, 6 Oct 2020 02:52:26 +0000 (19:52 -0700)]
update submodule

12 months agoadd moduw regression test
Jacob Lifshay [Tue, 6 Oct 2020 02:17:24 +0000 (19:17 -0700)]
add moduw regression test

12 months agoupdate submodule
Jacob Lifshay [Tue, 6 Oct 2020 02:16:24 +0000 (19:16 -0700)]
update submodule

12 months agoadd workaround for nmigen bug #502
Jacob Lifshay [Tue, 6 Oct 2020 01:59:39 +0000 (18:59 -0700)]
add workaround for nmigen bug #502

This fixes modsw

12 months agoupdate submodule
Jacob Lifshay [Tue, 6 Oct 2020 01:58:21 +0000 (18:58 -0700)]
update submodule

12 months agoadd modsw regression
Jacob Lifshay [Tue, 6 Oct 2020 01:07:56 +0000 (18:07 -0700)]
add modsw regression

12 months agoadd test case for divweu regression
Jacob Lifshay [Tue, 6 Oct 2020 01:06:51 +0000 (18:06 -0700)]
add test case for divweu regression

12 months agoupdate submodule
Jacob Lifshay [Tue, 6 Oct 2020 01:03:35 +0000 (18:03 -0700)]
update submodule

12 months agoprint regs in hex
Jacob Lifshay [Tue, 6 Oct 2020 00:16:29 +0000 (17:16 -0700)]
print regs in hex

12 months agoadd debug / investigation print statements
Luke Kenneth Casson Leighton [Mon, 5 Oct 2020 23:16:46 +0000 (00:16 +0100)]
add debug / investigation print statements