soc.git
10 months agoBegin to implement the Simple-V loop
Cesar Strauss [Sat, 6 Mar 2021 19:29:34 +0000 (16:29 -0300)]
Begin to implement the Simple-V loop

After returning from executing an instruction, decide whether to return
to Fetch, or go repeat Execute again.

1) If PC or SVSTATE were updated, go directly to Fetch, without updating
   either
2) If there is no vector output, or it's the last VL loop iteration, go
   back to Fetch as well, but update the PC. In the latter case, also
   reset SRCSTEP
3) Otherwise, we are still in the loop, so increment SVSTEP, and go back
   to Execute. But, first, pass through a new state, DECODE_SV, so the new
   register numbers can be decoded.

10 months agoDo not reset pc_changed and sv_changed at instruction end
Cesar Strauss [Sat, 6 Mar 2021 17:12:08 +0000 (14:12 -0300)]
Do not reset pc_changed and sv_changed at instruction end

We need these outputs to hold stable, so the Issue FSM can know whether
it can return to the Simple-V loop, or must return to Fetch. A good place
to reset these is at the start, before any instruction is executed.

10 months agoMake the raw opcode input port of the decoder stay stable
Cesar Strauss [Sat, 6 Mar 2021 16:46:50 +0000 (13:46 -0300)]
Make the raw opcode input port of the decoder stay stable

During a Simple-V loop, the decoder will be reused repeatedly, so its
raw opcode input needs to hold stable. An alternate way would be to
pass the raw opcode and the SVP64 RM field to the issue FSM, so it could
supply these decoder inputs when needed.

10 months agoremove blackbox attribute on SPBlock_512W64B8W
Luke Kenneth Casson Leighton [Sat, 6 Mar 2021 00:31:32 +0000 (00:31 +0000)]
remove blackbox attribute on SPBlock_512W64B8W

10 months agoadd SPBlock_512W64B8W.v blackbox file
Luke Kenneth Casson Leighton [Sat, 6 Mar 2021 00:28:49 +0000 (00:28 +0000)]
add SPBlock_512W64B8W.v blackbox file

10 months agoremove sram4k wishbone bte/cti in litex interconnect
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 23:11:11 +0000 (23:11 +0000)]
remove sram4k wishbone bte/cti in litex interconnect

10 months agolitex expects wishbone "err" signals even if not used
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 21:08:28 +0000 (21:08 +0000)]
litex expects wishbone "err" signals even if not used

10 months agoextend name of sram4k block with _wb suffix
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 19:14:53 +0000 (19:14 +0000)]
extend name of sram4k block with _wb suffix

10 months agounit test: pass bool mmu
Tobias Platen [Fri, 5 Mar 2021 16:47:53 +0000 (17:47 +0100)]
unit test: pass bool mmu

10 months agoadd comments and more stub functions
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 16:33:05 +0000 (16:33 +0000)]
add comments and more stub functions

10 months agoadd segment_check function, plus quick test.
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 16:16:41 +0000 (16:16 +0000)]
add segment_check function, plus quick test.
also fix order because SelectableInt deals in BE

10 months agoadd decode_prte function to RADIX
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 14:20:21 +0000 (14:20 +0000)]
add decode_prte function to RADIX

10 months agoadd trivial LD/ST redirectors into RADIX ISACaller
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 13:53:47 +0000 (13:53 +0000)]
add trivial LD/ST redirectors into RADIX ISACaller

10 months agoMove writing of the PC state register to the issue FSM
Cesar Strauss [Fri, 5 Mar 2021 12:01:34 +0000 (09:01 -0300)]
Move writing of the PC state register to the issue FSM

Before fetch, update the PC state register with the NIA, unless PC was
modified in execute.

10 months agoMove the wait on "core stop" out of fetch, and into issue
Cesar Strauss [Fri, 5 Mar 2021 10:57:01 +0000 (07:57 -0300)]
Move the wait on "core stop" out of fetch, and into issue

During a Simple-V loop, the fetch FSM will sit idle, unable to pause the
execution. A good alternate place to wait on "core stop" release is at
instruction end, before either fetching a new instruction, or going back
to the SV loop.

On system initialization, we need to pause as well, since there was no
instruction which ended previously.

10 months agoremoving --user from make develop
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 21:32:59 +0000 (21:32 +0000)]
removing --user from make develop

10 months agowhitespace
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 21:26:47 +0000 (21:26 +0000)]
whitespace

10 months agoupdate test_caller_radix.py
Tobias Platen [Thu, 4 Mar 2021 19:16:50 +0000 (20:16 +0100)]
update test_caller_radix.py

10 months agoISACaller: add option mmu
Tobias Platen [Thu, 4 Mar 2021 19:05:44 +0000 (20:05 +0100)]
ISACaller: add option mmu

10 months agowhoops microwatt already allocates SPR 720
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 18:15:40 +0000 (18:15 +0000)]
whoops microwatt already allocates SPR 720

10 months agoadd comments from gem5-experimental mmu
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 18:06:57 +0000 (18:06 +0000)]
add comments from gem5-experimental mmu

10 months agoadd cached pgtbl0/3
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 17:47:21 +0000 (17:47 +0000)]
add cached pgtbl0/3

10 months agoadd two functions for checking permissions, to be based on microwatt
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 17:39:53 +0000 (17:39 +0000)]
add two functions for checking permissions, to be based on microwatt

10 months agoadd RADIX skeleton and unit test
Tobias Platen [Wed, 3 Mar 2021 18:23:01 +0000 (19:23 +0100)]
add RADIX skeleton and unit test

10 months agoadd debug strings
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 17:45:55 +0000 (17:45 +0000)]
add debug strings

10 months agoremove singleton pattern
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 17:07:00 +0000 (17:07 +0000)]
remove singleton pattern

10 months agoadd pywriter Makefile entry
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 16:13:43 +0000 (16:13 +0000)]
add pywriter Makefile entry

10 months agocur_state is a global, does not have to be passed as a parameter in TestIssuer
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 14:28:53 +0000 (14:28 +0000)]
cur_state is a global, does not have to be passed as a parameter in TestIssuer

10 months agoset SVSTATE in TestRunner using new TestIssuer.svstate_i
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 14:18:46 +0000 (14:18 +0000)]
set SVSTATE in TestRunner using new TestIssuer.svstate_i

10 months agoadd svstate_i to TestIssuer which mirrors pc_i
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 14:15:18 +0000 (14:15 +0000)]
add svstate_i to TestIssuer which mirrors pc_i

10 months agocomment out changing SPR 720 because 720 is not supported by the MMU pipe
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 16:32:20 +0000 (16:32 +0000)]
comment out changing SPR 720 because 720 is not supported by the MMU pipe

10 months agosort out SPR setting in MMU
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 16:24:50 +0000 (16:24 +0000)]
sort out SPR setting in MMU

10 months agooperating correctly, not directing MMU SPRs to SPR Pipeline,
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 13:55:17 +0000 (13:55 +0000)]
operating correctly, not directing MMU SPRs to SPR Pipeline,
failure with PC likely due to ISACaller not supporting SPR 720

10 months agomust always set ok for writing out data otherwise it never hits regfile
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 12:49:18 +0000 (12:49 +0000)]
must always set ok for writing out data otherwise it never hits regfile
(and causes compunit to fail)

10 months agoRevert "fix Bug 607 - unnecessary code added related to MMU in PowerDecoder2"
Luke Kenneth Casson Leighton [Mon, 1 Mar 2021 19:35:31 +0000 (19:35 +0000)]
Revert "fix Bug 607 - unnecessary code added related to MMU in PowerDecoder2"

This reverts commit 0b31706069567c4124ebac487f238342cc540d79.

10 months agomove SVP64 RM decoder to separate module
Luke Kenneth Casson Leighton [Mon, 1 Mar 2021 15:40:31 +0000 (15:40 +0000)]
move SVP64 RM decoder to separate module

10 months agoadd additional SVP64 RM decode fields
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 18:36:22 +0000 (18:36 +0000)]
add additional SVP64 RM decode fields

10 months agostart on SVP64 RM Mode decoder
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 17:19:18 +0000 (17:19 +0000)]
start on SVP64 RM Mode decoder

10 months agomore SVP64 enums
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 16:29:54 +0000 (16:29 +0000)]
more SVP64 enums

10 months agoadd SVP64 RM sub-field enums
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 16:21:42 +0000 (16:21 +0000)]
add SVP64 RM sub-field enums

10 months agomove SVP64 Extra decoders to separate module
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:47:25 +0000 (14:47 +0000)]
move SVP64 Extra decoders to separate module

10 months agofix syntax error
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:43:09 +0000 (14:43 +0000)]
fix syntax error

10 months agomove SVP64PrefixDecoder to separate module
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:42:35 +0000 (14:42 +0000)]
move SVP64PrefixDecoder to separate module

10 months agoadd PowerDecoder.no_in_vec
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:42:12 +0000 (14:42 +0000)]
add PowerDecoder.no_in_vec

10 months agoadd svp64_instrs to power_svp64
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 12:19:52 +0000 (12:19 +0000)]
add svp64_instrs to power_svp64

10 months agofix Bug 607 - unnecessary code added related to MMU in PowerDecoder2
Tobias Platen [Sun, 28 Feb 2021 11:25:51 +0000 (12:25 +0100)]
fix Bug 607 - unnecessary code added related to MMU in PowerDecoder2

10 months agofix Bug 603 - use SPR names/numbers from sprs.csv
Tobias Platen [Sun, 28 Feb 2021 11:14:31 +0000 (12:14 +0100)]
fix Bug 603 - use SPR names/numbers from sprs.csv

10 months agouse PowerDecoder2.no_out_vec instead of manual vector detection in ISACaller
Luke Kenneth Casson Leighton [Sat, 27 Feb 2021 12:43:35 +0000 (12:43 +0000)]
use PowerDecoder2.no_out_vec instead of manual vector detection in ISACaller

10 months agoadd corresponding VL=0 unit test as from 161b7d67b in svp64_cases.py
Luke Kenneth Casson Leighton [Sat, 27 Feb 2021 12:38:15 +0000 (12:38 +0000)]
add corresponding VL=0 unit test as from 161b7d67b in svp64_cases.py

10 months agoAdd traces for the new FSM
Cesar Strauss [Sat, 27 Feb 2021 09:25:47 +0000 (06:25 -0300)]
Add traces for the new FSM

10 months agoAdd a vector case with VL == 0
Cesar Strauss [Fri, 26 Feb 2021 21:45:18 +0000 (18:45 -0300)]
Add a vector case with VL == 0

This will be useful for testing the fetch <-> issue loop.

10 months agocomment on CoreState
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:50:04 +0000 (13:50 +0000)]
comment on CoreState

10 months agoremove sv_changed input to fetch_fsm, add it to issue_fsm TestIssuer
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:46:22 +0000 (13:46 +0000)]
remove sv_changed input to fetch_fsm, add it to issue_fsm TestIssuer

10 months agomoving new_svstate and update_svstate into issue FSM TestIssuer
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:40:22 +0000 (13:40 +0000)]
moving new_svstate and update_svstate into issue FSM TestIssuer

10 months agomove fetch_insn_o into issue_fsm TestIssuer
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:34:59 +0000 (13:34 +0000)]
move fetch_insn_o into issue_fsm TestIssuer

10 months agoadd comments, missing that VL loop ends after execution if no_out_vec set
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:21:31 +0000 (13:21 +0000)]
add comments, missing that VL loop ends after execution if no_out_vec set
SVP64 TestIssuer

10 months agoImplement a decode/issue FSM between fetch and execute
Cesar Strauss [Fri, 26 Feb 2021 10:47:03 +0000 (07:47 -0300)]
Implement a decode/issue FSM between fetch and execute

The idea is for it to:
* keep looping "fetch" while VL==0 on a vector instruction.
* keep looping "execute" while SRCSTEP != VL-1.
* unless PC/SVSTATE was modified by "execute", in that case do go back
to "fetch".
* update PC and SRCSTEP accordingly.

10 months agowb_get: write outputs to seperate logfile too
Tobias Platen [Wed, 24 Feb 2021 18:43:23 +0000 (19:43 +0100)]
wb_get: write outputs to seperate logfile too

10 months agoupdate mmu testcase
Tobias Platen [Wed, 24 Feb 2021 18:40:53 +0000 (19:40 +0100)]
update mmu testcase

10 months agotest_runner.py: add needed imports
Tobias Platen [Wed, 24 Feb 2021 18:39:59 +0000 (19:39 +0100)]
test_runner.py: add needed imports

10 months agoadd comments explaining split
Luke Kenneth Casson Leighton [Wed, 24 Feb 2021 15:22:20 +0000 (15:22 +0000)]
add comments explaining split
https://bugs.libre-soc.org/show_bug.cgi?id=606

10 months agomove DecodeCROut/In (at last) out of PowerDecoderSubset and into PowerDecoder2
Luke Kenneth Casson Leighton [Wed, 24 Feb 2021 15:19:16 +0000 (15:19 +0000)]
move DecodeCROut/In (at last) out of PowerDecoderSubset and into PowerDecoder2
https://bugs.libre-soc.org/show_bug.cgi?id=606

10 months agostart making write_cr0 independent of DecodeCROut
Luke Kenneth Casson Leighton [Wed, 24 Feb 2021 15:08:32 +0000 (15:08 +0000)]
start making write_cr0 independent of DecodeCROut
https://bugs.libre-soc.org/show_bug.cgi?id=606

11 months agodeduplicate
Tobias Platen [Tue, 23 Feb 2021 18:20:15 +0000 (19:20 +0100)]
deduplicate

11 months agoadd note that SVSTATE has changed, this will allow picking up that
Luke Kenneth Casson Leighton [Tue, 23 Feb 2021 13:43:35 +0000 (13:43 +0000)]
add note that SVSTATE has changed, this will allow picking up that
Trap pipeline has altered SVSTATE

11 months agoFix typo when calculating PowerDecoder2.no_out_vec
Cesar Strauss [Mon, 22 Feb 2021 21:29:11 +0000 (18:29 -0300)]
Fix typo when calculating PowerDecoder2.no_out_vec

11 months agomove setting of NIA into fetch FSM in TestIssuer
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 16:21:26 +0000 (16:21 +0000)]
move setting of NIA into fetch FSM in TestIssuer

11 months agowhoops
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 16:00:24 +0000 (16:00 +0000)]
whoops

11 months agomoving PC-setting (NIA) out of execute_fsm in TestIssuer
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 15:59:33 +0000 (15:59 +0000)]
moving PC-setting (NIA) out of execute_fsm in TestIssuer

11 months agorename inter-FSM handshake signals in TestIssuer
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 14:48:46 +0000 (14:48 +0000)]
rename inter-FSM handshake signals in TestIssuer

11 months agoerr trying to put in some FSM handshake signals, getting confused
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 19:27:06 +0000 (19:27 +0000)]
err trying to put in some FSM handshake signals, getting confused

11 months agocomment for where SVSTATE FSM should go
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 19:20:38 +0000 (19:20 +0000)]
comment for where SVSTATE FSM should go

11 months agoadd CR out vector detection to PowerDecoder2 no_out_vec
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 19:20:17 +0000 (19:20 +0000)]
add CR out vector detection to PowerDecoder2 no_out_vec

11 months agoThe field selection function was moved to nmutil.util
Cesar Strauss [Sun, 21 Feb 2021 17:21:54 +0000 (14:21 -0300)]
The field selection function was moved to nmutil.util

All previous users were updated.

11 months agoHide the register augmentation traces by default
Cesar Strauss [Sun, 21 Feb 2021 17:18:15 +0000 (14:18 -0300)]
Hide the register augmentation traces by default

This saves some vertical space if you are not interested in seeing this
level of detail, but it is still there if you need it.
Needs the latest nmutil version for it to work.

11 months agomove execute_fsm to separate function in TestIssuer
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 15:50:31 +0000 (15:50 +0000)]
move execute_fsm to separate function in TestIssuer

11 months agomove fetch_fsm to separate function in TestIssuer
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 15:41:08 +0000 (15:41 +0000)]
move fetch_fsm to separate function in TestIssuer

11 months agoadd JTAG enable/disable of 4k SRAMs
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 15:22:28 +0000 (15:22 +0000)]
add JTAG enable/disable of 4k SRAMs

11 months agoThe new version of "sel" is smart enough to find a suitable Signal name
Cesar Strauss [Sun, 21 Feb 2021 14:50:21 +0000 (11:50 -0300)]
The new version of "sel" is smart enough to find a suitable Signal name

An up-to-date version of nmutil is required for this.

11 months agoadd comments for Mode field in SVP64Asm
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 13:08:32 +0000 (13:08 +0000)]
add comments for Mode field in SVP64Asm

11 months agocomments in SVP64RMFields
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 12:58:19 +0000 (12:58 +0000)]
comments in SVP64RMFields

11 months agoUse the new selection field function from nmutil
Cesar Strauss [Sun, 21 Feb 2021 12:54:20 +0000 (09:54 -0300)]
Use the new selection field function from nmutil

Note that the new function accepts a Module on which it to generate its
wires, and returns a Signal of the appropriate size.

Be sure to update nmutil to get the new function.

11 months agoUse symbolic values as field sizes
Cesar Strauss [Sun, 21 Feb 2021 09:58:54 +0000 (06:58 -0300)]
Use symbolic values as field sizes

11 months agoReplace all hardcoded shifts into RM by usage of SVP64RMFields
Cesar Strauss [Sat, 20 Feb 2021 23:00:02 +0000 (20:00 -0300)]
Replace all hardcoded shifts into RM by usage of SVP64RMFields

11 months agocreate SVP64CROffs consts for when SVP64 Vector-of-CRs is active (Rc=1)
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 01:04:50 +0000 (01:04 +0000)]
create SVP64CROffs consts for when SVP64 Vector-of-CRs is active (Rc=1)

11 months agocomments on sv.add. Rc=1 unit test
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 23:38:17 +0000 (23:38 +0000)]
comments on sv.add. Rc=1 unit test

11 months agoadd in Vectorised CRs when Rc=1 into ISACaller
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 23:32:50 +0000 (23:32 +0000)]
add in Vectorised CRs when Rc=1 into ISACaller

11 months agoadd CR1 to DecodeCRIn/Out
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 23:15:06 +0000 (23:15 +0000)]
add CR1 to DecodeCRIn/Out

11 months agoadd some debug checking to get_pdecode_cr_out
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 22:13:20 +0000 (22:13 +0000)]
add some debug checking to get_pdecode_cr_out

11 months agoadd crossreference to bug #603
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 21:55:57 +0000 (21:55 +0000)]
add crossreference to bug #603

11 months agoadd more debug output to get_pdecode_cr_out
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 21:44:48 +0000 (21:44 +0000)]
add more debug output to get_pdecode_cr_out

11 months agoActually forward the field width to field_slice()
Cesar Strauss [Sat, 20 Feb 2021 21:12:03 +0000 (18:12 -0300)]
Actually forward the field width to field_slice()

This means that field extraction of multi-bit subfields, for field sizes
other than 64 bits, was buggy up to now.

Fortunately, there were no users of non-default field sizes so far.

11 months agoAssemble the SV64 prefix from its subfields using SVP64PrefixFields
Cesar Strauss [Sat, 20 Feb 2021 20:09:42 +0000 (17:09 -0300)]
Assemble the SV64 prefix from its subfields using SVP64PrefixFields

11 months agostart on CRs in SVP64 mode
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 20:49:26 +0000 (20:49 +0000)]
start on CRs in SVP64 mode

11 months agofix SVP64Asm Rc=1 assembly
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 20:49:00 +0000 (20:49 +0000)]
fix SVP64Asm Rc=1 assembly

11 months agoadd black-box attribute to 4k SRAM cell
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 20:47:48 +0000 (20:47 +0000)]
add black-box attribute to 4k SRAM cell

11 months agoFix more MSB0 issues in comments
Cesar Strauss [Sat, 20 Feb 2021 18:39:41 +0000 (15:39 -0300)]
Fix more MSB0 issues in comments

11 months agoReplace more hardcoded constants with symbolic field numbers
Cesar Strauss [Sat, 20 Feb 2021 18:31:55 +0000 (15:31 -0300)]
Replace more hardcoded constants with symbolic field numbers

11 months agoincrement CRs based on srcstep, see what happens
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 16:40:41 +0000 (16:40 +0000)]
increment CRs based on srcstep, see what happens

11 months agoadd litex wishbone interconnect to 4x 4k SRAMs
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 15:22:18 +0000 (15:22 +0000)]
add litex wishbone interconnect to 4x 4k SRAMs
also had to add one more of the massive DFF 512 byte SRAMs in order to cover
all the exception areas (0x900) without going into 4k SRAM area,
which litex demands to be on an aligned boundary