soc.git
18 months agoadd readonly option to TestMemory
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 19:19:14 +0000 (20:19 +0100)]
add readonly option to TestMemory

18 months agoexpand instruction bus width to 64 bit, start on a mini-cache
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 17:23:08 +0000 (18:23 +0100)]
expand instruction bus width to 64 bit, start on a mini-cache
for instructions (one line)

18 months agoparameterise minerva i-cache
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 16:20:15 +0000 (17:20 +0100)]
parameterise minerva i-cache

18 months agogot Pi2LSUI FSM working
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 14:39:10 +0000 (15:39 +0100)]
got Pi2LSUI FSM working

18 months agosram address do not cut by LSBs
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 12:17:09 +0000 (13:17 +0100)]
sram address do not cut by LSBs

18 months agonew Pi2LSUI working, using PortInterfaceBase
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 11:03:24 +0000 (12:03 +0100)]
new Pi2LSUI working, using PortInterfaceBase

18 months agostart new version of Pi2LSUI based on PortInterfaceBase
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 10:43:17 +0000 (11:43 +0100)]
start new version of Pi2LSUI based on PortInterfaceBase

18 months agopass addr/mask through to PortInterfaceBase rd/wr addr
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 10:24:30 +0000 (11:24 +0100)]
pass addr/mask through to PortInterfaceBase rd/wr addr

18 months agocleanup (remove unneeded imports)
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 10:19:03 +0000 (11:19 +0100)]
cleanup (remove unneeded imports)

18 months agomore code-shuffle for TestMemoryPortInterface
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 10:16:48 +0000 (11:16 +0100)]
more code-shuffle for TestMemoryPortInterface

18 months agomore code-shuffle for TestMemoryPortInterface
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 10:13:24 +0000 (11:13 +0100)]
more code-shuffle for TestMemoryPortInterface

18 months agominor cleanup, put get/set rdport/wrport into function
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 09:38:17 +0000 (10:38 +0100)]
minor cleanup, put get/set rdport/wrport into function

18 months agomerge LDSTPort into TestMemoryPortInterface
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 09:23:31 +0000 (10:23 +0100)]
merge LDSTPort into TestMemoryPortInterface

18 months agouse PortInterface connect_port
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 09:21:19 +0000 (10:21 +0100)]
use PortInterface connect_port

18 months agouse PortInterface connect_port
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 09:18:57 +0000 (10:18 +0100)]
use PortInterface connect_port

18 months agoattempt to get Pi2LSUI FSM working
Luke Kenneth Casson Leighton [Sun, 28 Jun 2020 09:14:36 +0000 (10:14 +0100)]
attempt to get Pi2LSUI FSM working

18 months agoonly activate ld_in_progress if addr is ok
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 20:35:27 +0000 (21:35 +0100)]
only activate ld_in_progress if addr is ok

18 months agomake Memory accessible via TestSRAMBareLoadStoreUnit
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 19:21:12 +0000 (20:21 +0100)]
make Memory accessible via TestSRAMBareLoadStoreUnit

18 months agoincrease (double) address width in TstL0CacheBuffer
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 19:12:55 +0000 (20:12 +0100)]
increase (double) address width in TstL0CacheBuffer

18 months agoincrease (double) address width in TstL0CacheBuffer
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 19:12:02 +0000 (20:12 +0100)]
increase (double) address width in TstL0CacheBuffer

18 months agounit test in l0_cache to connect to testpi and test_bare_wb
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 19:05:26 +0000 (20:05 +0100)]
unit test in l0_cache to connect to testpi and test_bare_wb

18 months agomake PortInterface modules consistent with same API
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 18:43:00 +0000 (19:43 +0100)]
make PortInterface modules consistent with same API

18 months agouse ConfigMemoryPortInterface in TstL0CacheBuffer
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 18:24:34 +0000 (19:24 +0100)]
use ConfigMemoryPortInterface in TstL0CacheBuffer

18 months agofix TestMemLoadStoreUnit, it required a FSM to monitor write
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 16:50:07 +0000 (17:50 +0100)]
fix TestMemLoadStoreUnit, it required a FSM to monitor write
and also needed to honour the "busy_o" signal

18 months agoadd wishbone Pi2LSUI test
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 14:20:24 +0000 (15:20 +0100)]
add wishbone Pi2LSUI test

18 months agoreconfigureable PortInterface testing now possible
Luke Kenneth Casson Leighton [Sat, 27 Jun 2020 12:34:57 +0000 (13:34 +0100)]
reconfigureable PortInterface testing now possible

18 months agoname issue in Pi2LSUI
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 23:29:36 +0000 (00:29 +0100)]
name issue in Pi2LSUI

18 months agowhitespace and imports
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 23:26:58 +0000 (00:26 +0100)]
whitespace and imports

18 months agowhitespace
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 23:25:17 +0000 (00:25 +0100)]
whitespace

18 months agoslight reorg on test_pi2ls.py
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 22:40:08 +0000 (23:40 +0100)]
slight reorg on test_pi2ls.py

18 months agocorrect address in pi2ls
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 22:38:37 +0000 (23:38 +0100)]
correct address in pi2ls

18 months agooops forgot to initialise base class of TestMemLoadStoreUnit
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 22:22:37 +0000 (23:22 +0100)]
oops forgot to initialise base class of TestMemLoadStoreUnit

18 months agoadd in LenExpand shift/mask
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 21:06:32 +0000 (22:06 +0100)]
add in LenExpand shift/mask

18 months agoadd quick test showing Pi2LSUI not quite reading/writing to
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 19:47:16 +0000 (20:47 +0100)]
add quick test showing Pi2LSUI not quite reading/writing to
correct addresses

18 months agoremove extraneous yields
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 19:40:52 +0000 (20:40 +0100)]
remove extraneous yields

18 months agoModify pi2ls so it passes the portinterface unit tests
Michael Nolan [Fri, 26 Jun 2020 19:36:41 +0000 (15:36 -0400)]
Modify pi2ls so it passes the portinterface unit tests

18 months agoset address ok and fix unit test to check it properly
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 19:37:46 +0000 (20:37 +0100)]
set address ok and fix unit test to check it properly

18 months agoadd pi.busy_o connection, increase to 64 bit
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 19:30:18 +0000 (20:30 +0100)]
add pi.busy_o connection, increase to 64 bit

18 months agounit test broken is ok :)
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 19:12:30 +0000 (20:12 +0100)]
unit test broken is ok :)

18 months agoset pi.ld.ok to 1 if pi.is_ld_i is set
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 19:09:57 +0000 (20:09 +0100)]
set pi.ld.ok to 1 if pi.is_ld_i is set

18 months agoMove tests for pimem to new file, add ability to test pi2ls.py
Michael Nolan [Fri, 26 Jun 2020 18:58:54 +0000 (14:58 -0400)]
Move tests for pimem to new file, add ability to test pi2ls.py

18 months agoload/store unit test needed to wait for busy_o
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 18:00:07 +0000 (19:00 +0100)]
load/store unit test needed to wait for busy_o
otherwise, the bus was still processing the previous transaction

18 months agowhitespace
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 17:58:38 +0000 (18:58 +0100)]
whitespace

18 months agoclean up output from BareLoadStoreUnit
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 17:58:28 +0000 (18:58 +0100)]
clean up output from BareLoadStoreUnit

18 months agohalve the test memory size again
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 16:20:20 +0000 (17:20 +0100)]
halve the test memory size again

18 months agoshrink test memory size down to only 64 words
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 16:17:44 +0000 (17:17 +0100)]
shrink test memory size down to only 64 words

18 months agoinvestigating why write-enable not getting passed through
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 15:52:34 +0000 (16:52 +0100)]
investigating why write-enable not getting passed through
on nmigen_soc sram

18 months agowhoops forgot to call parent elaborate
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 13:35:23 +0000 (14:35 +0100)]
whoops forgot to call parent elaborate

18 months agoadd test of SRAM through wishbone bus
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 13:24:51 +0000 (14:24 +0100)]
add test of SRAM through wishbone bus

18 months agocode-morph which redirects lsmem unit test through new ConfigLoadStoreUnit
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 12:14:47 +0000 (13:14 +0100)]
code-morph which redirects lsmem unit test through new ConfigLoadStoreUnit
this to allow wishbone-SRAM test version to be tested with the same
unit test

18 months agoadd a test SRAM that lives behind a minerva LoadStoreUnitInterface
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 11:44:23 +0000 (12:44 +0100)]
add a test SRAM that lives behind a minerva LoadStoreUnitInterface

18 months agodynamically specify wishbone layout (no longer hardcoded addr/data)
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 11:16:20 +0000 (12:16 +0100)]
dynamically specify wishbone layout (no longer hardcoded addr/data)

18 months agoadd reconfigureable Load/Store class
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 10:36:34 +0000 (11:36 +0100)]
add reconfigureable Load/Store class

18 months agoextra parameterification of minerva LoadStoreUnits
Luke Kenneth Casson Leighton [Fri, 26 Jun 2020 08:53:26 +0000 (09:53 +0100)]
extra parameterification of minerva LoadStoreUnits

18 months agoallow Pi2LSUI to accept incoming PortInterface and LoadStoreUnitInterface
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 21:12:47 +0000 (22:12 +0100)]
allow Pi2LSUI to accept incoming PortInterface and LoadStoreUnitInterface

18 months agoadd extra parameter, mask_wid, to TestMemLoadStoreUnit
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 20:59:39 +0000 (21:59 +0100)]
add extra parameter, mask_wid, to TestMemLoadStoreUnit

18 months agostart connecting up Pi2LSUI
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 19:41:35 +0000 (20:41 +0100)]
start connecting up Pi2LSUI

18 months agoadd LenExpand module, tidyup on docstring
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 19:29:25 +0000 (20:29 +0100)]
add LenExpand module, tidyup on docstring

18 months agoadd beginnings of Pi2LSUI
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 19:25:13 +0000 (20:25 +0100)]
add beginnings of Pi2LSUI

19 months agoadd nmigen-soc to dependencies
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 11:53:27 +0000 (12:53 +0100)]
add nmigen-soc to dependencies

19 months agoadd attempt at mapping between PortInterface and LoadStoreUnitInterface
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 09:56:35 +0000 (10:56 +0100)]
add attempt at mapping between PortInterface and LoadStoreUnitInterface

19 months agorename LoadStoreInterface signals to include _i and _o suffixes
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 09:43:42 +0000 (10:43 +0100)]
rename LoadStoreInterface signals to include _i and _o suffixes
got fed up of not knowing which Signal was which direction

19 months agowhitespace
Luke Kenneth Casson Leighton [Thu, 25 Jun 2020 09:34:03 +0000 (10:34 +0100)]
whitespace

19 months agoRevert "modify PortInterface so subfields include the port's name"
Michael Nolan [Wed, 24 Jun 2020 19:43:29 +0000 (15:43 -0400)]
Revert "modify PortInterface so subfields include the port's name"

No longer necessary with changes to nmutil f61e3beee

This reverts commit 8c63d6dfe17825ca984854e33e20589df6c5bdb6.

19 months agoUpdate comments for LoadStoreUnitInterface
Michael Nolan [Wed, 24 Jun 2020 18:20:49 +0000 (14:20 -0400)]
Update comments for LoadStoreUnitInterface

19 months agoHave lsmem handle stall and valid signals correctly
Michael Nolan [Wed, 24 Jun 2020 18:18:42 +0000 (14:18 -0400)]
Have lsmem handle stall and valid signals correctly

19 months agoUpdate comments on LoadStoreUnitInterface again
Michael Nolan [Wed, 24 Jun 2020 18:03:12 +0000 (14:03 -0400)]
Update comments on LoadStoreUnitInterface again

19 months agoUpdate comments on LoadStoreUnitInterface
Michael Nolan [Wed, 24 Jun 2020 17:46:20 +0000 (13:46 -0400)]
Update comments on LoadStoreUnitInterface

19 months agoAdd handling of byte reads and writes
Michael Nolan [Wed, 24 Jun 2020 17:16:13 +0000 (13:16 -0400)]
Add handling of byte reads and writes

19 months agoAdd more complete testbench for lsmem.py
Michael Nolan [Wed, 24 Jun 2020 17:09:10 +0000 (13:09 -0400)]
Add more complete testbench for lsmem.py

19 months agoSuper basic first try of testmem with load store unit interface
Michael Nolan [Wed, 24 Jun 2020 16:59:40 +0000 (12:59 -0400)]
Super basic first try of testmem with load store unit interface

19 months agomove comments to minerva LoadStoreInterface
Luke Kenneth Casson Leighton [Wed, 24 Jun 2020 15:53:13 +0000 (16:53 +0100)]
move comments to minerva LoadStoreInterface

19 months agoimport minerva and use LoadStoreUnitInterface
Luke Kenneth Casson Leighton [Wed, 24 Jun 2020 15:40:08 +0000 (16:40 +0100)]
import minerva and use LoadStoreUnitInterface

19 months agoAdd specification for load store interface
Michael Nolan [Wed, 24 Jun 2020 15:28:11 +0000 (11:28 -0400)]
Add specification for load store interface

19 months agomodify PortInterface so subfields include the port's name
Michael Nolan [Tue, 23 Jun 2020 17:47:17 +0000 (13:47 -0400)]
modify PortInterface so subfields include the port's name

19 months agoannoying error in latest nmigen
Luke Kenneth Casson Leighton [Tue, 23 Jun 2020 16:10:44 +0000 (17:10 +0100)]
annoying error in latest nmigen

19 months agoTstL0CacheBuffer returns array of ports differently now
Luke Kenneth Casson Leighton [Tue, 23 Jun 2020 15:47:54 +0000 (16:47 +0100)]
TstL0CacheBuffer returns array of ports differently now

19 months agoremove unused module
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 19:34:20 +0000 (20:34 +0100)]
remove unused module

19 months agosimplified L0CacheBuffer down to a "PortInterface Arbiter"
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 19:24:02 +0000 (20:24 +0100)]
simplified L0CacheBuffer down to a "PortInterface Arbiter"

19 months agoadd TestMemoryPortInterface class which is designed to replace L0CacheBuffer in
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 12:45:11 +0000 (13:45 +0100)]
add TestMemoryPortInterface class which is designed to replace L0CacheBuffer in
unit tests, allowing L0CacheBuffer to be developed on its own terms

19 months agocomments for LDST CompUnit test
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 12:06:34 +0000 (13:06 +0100)]
comments for LDST CompUnit test

19 months agoenable byte-reverse in CompLDSTUnit test
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 12:02:07 +0000 (13:02 +0100)]
enable byte-reverse in CompLDSTUnit test

19 months agoremove CompLDSTOpSubset, replace with just data_len.
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 11:12:10 +0000 (12:12 +0100)]
remove CompLDSTOpSubset, replace with just data_len.

19 months agomove BE/LE byte-reverse into LDSTCompUnit
Luke Kenneth Casson Leighton [Mon, 22 Jun 2020 10:49:41 +0000 (11:49 +0100)]
move BE/LE byte-reverse into LDSTCompUnit

19 months agoexpand Memory width to 64 and granularity to 16 in SRAM test
Luke Kenneth Casson Leighton [Sat, 20 Jun 2020 12:28:35 +0000 (13:28 +0100)]
expand Memory width to 64 and granularity to 16 in SRAM test

19 months agoadd asserts to check data output is correct
Luke Kenneth Casson Leighton [Sat, 20 Jun 2020 12:16:00 +0000 (13:16 +0100)]
add asserts to check data output is correct

19 months agoadd test_sram_wishbone.py
Luke Kenneth Casson Leighton [Sat, 20 Jun 2020 11:55:26 +0000 (12:55 +0100)]
add test_sram_wishbone.py
https://bugs.libre-soc.org/show_bug.cgi?id=382

19 months agoAdd code, commented-out, for TRAP so as to not break test_caller.py
colepoirier [Sat, 20 Jun 2020 01:30:54 +0000 (18:30 -0700)]
Add code, commented-out, for TRAP so as to not break test_caller.py

19 months agowhitespace update
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 21:30:01 +0000 (22:30 +0100)]
whitespace update

19 months agomove trunc_div and trunc_rem to nmutil
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 21:16:55 +0000 (22:16 +0100)]
move trunc_div and trunc_rem to nmutil

19 months agoadd comments on trunc_div and trunc_rem
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 20:29:30 +0000 (21:29 +0100)]
add comments on trunc_div and trunc_rem

19 months agoadd divide-by-zero test to test_div_sim.py
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 16:49:32 +0000 (17:49 +0100)]
add divide-by-zero test to test_div_sim.py

19 months agoadd docstring comment for SelectableInt
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:39:04 +0000 (15:39 +0100)]
add docstring comment for SelectableInt

19 months agoadd test_0_moduw and correct name to trunc_rem
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:30:45 +0000 (15:30 +0100)]
add test_0_moduw and correct name to trunc_rem

19 months agoadd abs SelectableInt unit test (very quick)
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:27:25 +0000 (15:27 +0100)]
add abs SelectableInt unit test (very quick)

19 months agoadd SelectableInt.abs
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:25:04 +0000 (15:25 +0100)]
add SelectableInt.abs
https://bugs.libre-soc.org/show_bug.cgi?id=324#c19

19 months agoadd another bad hack in parser.py which identifies "undefined" slice assignment
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:21:15 +0000 (15:21 +0100)]
add another bad hack in parser.py which identifies "undefined" slice assignment

19 months agoadd in really bad hack which calls trunc_div or trunc_mod
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:14:37 +0000 (15:14 +0100)]
add in really bad hack which calls trunc_div or trunc_mod
https://bugs.libre-soc.org/show_bug.cgi?id=324#c16

19 months agoadd trunc_div and trunch_rem to decoder helpers
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 14:03:28 +0000 (15:03 +0100)]
add trunc_div and trunch_rem to decoder helpers
https://bugs.libre-soc.org/show_bug.cgi?id=324

19 months agoauto-assign needs to use concat / selectconcat
Luke Kenneth Casson Leighton [Fri, 19 Jun 2020 13:01:39 +0000 (14:01 +0100)]
auto-assign needs to use concat / selectconcat