soc.git
3 hours agomove pc_i and svstate_i inside if self.run_hdl master
Luke Kenneth Casson Leighton [Thu, 23 Sep 2021 22:55:35 +0000 (23:55 +0100)]
move pc_i and svstate_i inside if self.run_hdl

3 hours agomore comments
Luke Kenneth Casson Leighton [Thu, 23 Sep 2021 22:49:57 +0000 (23:49 +0100)]
more comments

3 hours agoadd in a stack of comments for identifying match-points with StateRunner
Luke Kenneth Casson Leighton [Thu, 23 Sep 2021 22:47:32 +0000 (23:47 +0100)]
add in a stack of comments for identifying match-points with StateRunner

4 hours agoadd option to run ISACaller Sim (or not)
Luke Kenneth Casson Leighton [Thu, 23 Sep 2021 22:40:04 +0000 (23:40 +0100)]
add option to run ISACaller Sim (or not)

4 hours agoadd a new run_hdl parameter to TestRunner
Luke Kenneth Casson Leighton [Thu, 23 Sep 2021 22:31:41 +0000 (23:31 +0100)]
add a new run_hdl parameter to TestRunner

29 hours agocompletely borked python segfault, workaround to copy last sim state
Luke Kenneth Casson Leighton [Wed, 22 Sep 2021 20:52:26 +0000 (21:52 +0100)]
completely borked python segfault, workaround to copy last sim state

30 hours agoadd test of expected results against last sim state
Luke Kenneth Casson Leighton [Wed, 22 Sep 2021 20:35:14 +0000 (21:35 +0100)]
add test of expected results against last sim state

30 hours agowhoops broken run_sim_state function
Luke Kenneth Casson Leighton [Wed, 22 Sep 2021 20:34:52 +0000 (21:34 +0100)]
whoops broken run_sim_state function

31 hours agosplit out HDL from Simulator into separate functions
Luke Kenneth Casson Leighton [Wed, 22 Sep 2021 19:18:53 +0000 (20:18 +0100)]
split out HDL from Simulator into separate functions

32 hours agosplit out HDL test from Simulator test,
Luke Kenneth Casson Leighton [Wed, 22 Sep 2021 18:40:30 +0000 (19:40 +0100)]
split out HDL test from Simulator test,
save two separate lists of TestStates
compare them *after* the two simulations have been run
should be possible to completely separate out, now

32 hours agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Wed, 22 Sep 2021 18:02:05 +0000 (20:02 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

32 hours agocompldst_multi: add op_is_dcbz signal
Tobias Platen [Wed, 22 Sep 2021 18:00:58 +0000 (20:00 +0200)]
compldst_multi: add op_is_dcbz signal

32 hours agofix mul fu test helper.py not passing immediate to pia for mulli
Jacob Lifshay [Wed, 22 Sep 2021 17:58:58 +0000 (10:58 -0700)]
fix mul fu test helper.py not passing immediate to pia for mulli

34 hours agowhitespace cleanup
Tobias Platen [Wed, 22 Sep 2021 16:45:59 +0000 (18:45 +0200)]
whitespace cleanup

34 hours agoalter setup_tst_memory to take a test.mem rather than take a Sim object
Luke Kenneth Casson Leighton [Wed, 22 Sep 2021 15:56:09 +0000 (16:56 +0100)]
alter setup_tst_memory to take a test.mem rather than take a Sim object
*containing* a Mem

35 hours agowhoops forgot to do with self.subTest()
Luke Kenneth Casson Leighton [Wed, 22 Sep 2021 15:38:40 +0000 (16:38 +0100)]
whoops forgot to do with self.subTest()

2 days agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Tue, 21 Sep 2021 18:48:27 +0000 (20:48 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

2 days agotestcase: add mmu, link mmu and dcache together
Tobias Platen [Tue, 21 Sep 2021 18:47:33 +0000 (20:47 +0200)]
testcase: add mmu, link mmu and dcache together

2 days agochanged test_runner to use state mem compare
klehman [Tue, 21 Sep 2021 18:20:31 +0000 (14:20 -0400)]
changed test_runner to use state mem compare

2 days agochanged over to use state mem compare
klehman [Tue, 21 Sep 2021 18:19:10 +0000 (14:19 -0400)]
changed over to use state mem compare

2 days agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Tue, 21 Sep 2021 17:49:19 +0000 (19:49 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

2 days agocomment out lines that cause test_compldst_multi_mmu.py to hang
Tobias Platen [Tue, 21 Sep 2021 17:49:01 +0000 (19:49 +0200)]
comment out lines that cause test_compldst_multi_mmu.py to hang

2 days agoconvert HDLState.get_mem() to a dictionary of memory state results
Luke Kenneth Casson Leighton [Tue, 21 Sep 2021 14:46:16 +0000 (15:46 +0100)]
convert HDLState.get_mem() to a dictionary of memory state results

3 days agoupdate test_compldst_multi_mmu.py
Tobias Platen [Mon, 20 Sep 2021 18:34:31 +0000 (20:34 +0200)]
update test_compldst_multi_mmu.py

3 days agouse get_l0_mem in HDLState to get memory data
Luke Kenneth Casson Leighton [Mon, 20 Sep 2021 17:33:38 +0000 (18:33 +0100)]
use get_l0_mem in HDLState to get memory data

4 days agoFix rel_o/go_i signal names
Cesar Strauss [Sun, 19 Sep 2021 20:13:18 +0000 (17:13 -0300)]
Fix rel_o/go_i signal names

4 days agoReplace "Display" with "print" on simulation process
Cesar Strauss [Sun, 19 Sep 2021 20:03:48 +0000 (17:03 -0300)]
Replace "Display" with "print" on simulation process

The fallback on nmutil doesn't work with "yield Display".

4 days agoFix import
Cesar Strauss [Sun, 19 Sep 2021 13:38:46 +0000 (10:38 -0300)]
Fix import

5 days agoUse a pre-compiled version of maturin
Cesar Strauss [Sat, 18 Sep 2021 20:56:41 +0000 (17:56 -0300)]
Use a pre-compiled version of maturin

Should save compile time on the Gitlab CI runner.

5 days agoallow individual unit tests to be named in test_issuer.py
Luke Kenneth Casson Leighton [Sat, 18 Sep 2021 15:35:59 +0000 (16:35 +0100)]
allow individual unit tests to be named in test_issuer.py

5 days agoalways store full memory state (including zeros)
Luke Kenneth Casson Leighton [Sat, 18 Sep 2021 15:05:09 +0000 (16:05 +0100)]
always store full memory state (including zeros)

5 days agoadded get_mem
klehman [Sat, 18 Sep 2021 11:44:01 +0000 (07:44 -0400)]
added get_mem

6 days agoupdate comments
Luke Kenneth Casson Leighton [Fri, 17 Sep 2021 15:13:15 +0000 (16:13 +0100)]
update comments
https://bugs.libre-soc.org/show_bug.cgi?id=686#c51

7 days agomoving teststate_check_regs written by klehman into openpower-isa
Luke Kenneth Casson Leighton [Thu, 16 Sep 2021 16:06:18 +0000 (17:06 +0100)]
moving teststate_check_regs written by klehman into openpower-isa

8 days agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
isengaara [Wed, 15 Sep 2021 17:56:35 +0000 (19:56 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

8 days agoadd new testcase for ompldst_multi using mmu
isengaara [Wed, 15 Sep 2021 17:55:52 +0000 (19:55 +0200)]
add new testcase for ompldst_multi using mmu

9 days agoconvert to using TestState and State after moving to openpower-isa
Luke Kenneth Casson Leighton [Tue, 14 Sep 2021 17:38:58 +0000 (18:38 +0100)]
convert to using TestState and State after moving to openpower-isa

9 days agofactory add and intro doc string
klehman [Tue, 14 Sep 2021 15:43:10 +0000 (11:43 -0400)]
factory add and intro doc string

10 days agoSave Gitlab runner cache, even on a failed test
Cesar Strauss [Mon, 13 Sep 2021 09:22:43 +0000 (06:22 -0300)]
Save Gitlab runner cache, even on a failed test

Since our tests currently fail, the cache was never saved, not even once.

11 days agouse log instead of print
Luke Kenneth Casson Leighton [Sun, 12 Sep 2021 13:36:41 +0000 (14:36 +0100)]
use log instead of print

11 days agocode comments
Luke Kenneth Casson Leighton [Sun, 12 Sep 2021 13:24:00 +0000 (14:24 +0100)]
code comments

11 days agocreate new function teststate_check_regs which is called by check_regs
Luke Kenneth Casson Leighton [Sun, 12 Sep 2021 13:21:23 +0000 (14:21 +0100)]
create new function teststate_check_regs which is called by check_regs
teststate_checkregs does not care how many pieces of state it is asked
to compare. could be 2, could be 3, could be 30

11 days agochanges to utilize full teststate class
klehman [Sun, 12 Sep 2021 12:59:09 +0000 (08:59 -0400)]
changes to utilize full teststate class

11 days agoadded compare function
klehman [Sun, 12 Sep 2021 03:56:11 +0000 (23:56 -0400)]
added compare function

12 days agoadded factory function for test class creation
klehman [Sun, 12 Sep 2021 00:53:31 +0000 (20:53 -0400)]
added factory function for test class creation

13 days agoimplement base class in state class
klehman [Fri, 10 Sep 2021 20:58:15 +0000 (16:58 -0400)]
implement base class in state class

13 days agochanges made to utilize teststate class
klehman [Fri, 10 Sep 2021 15:08:12 +0000 (11:08 -0400)]
changes made to utilize teststate class

13 days agoupdate explanatory comments on LD/ST exception handling
Luke Kenneth Casson Leighton [Fri, 10 Sep 2021 10:19:47 +0000 (11:19 +0100)]
update explanatory comments on LD/ST exception handling

2 weeks agomade sim into generators and some uniformity changes
klehman [Thu, 9 Sep 2021 21:31:31 +0000 (17:31 -0400)]
made sim into generators and some uniformity changes

2 weeks agofinished remaining hdl items
klehman [Thu, 9 Sep 2021 16:33:01 +0000 (12:33 -0400)]
finished remaining hdl items

2 weeks agoHDL int reg added
klehman [Thu, 9 Sep 2021 13:01:50 +0000 (09:01 -0400)]
HDL int reg added

2 weeks agomore sim class registers add
klehman [Thu, 9 Sep 2021 12:04:23 +0000 (08:04 -0400)]
more sim class registers add

2 weeks agoMonitor exceptions, re-decoding the instruction in this case
Cesar Strauss [Wed, 8 Sep 2021 16:42:50 +0000 (13:42 -0300)]
Monitor exceptions, re-decoding the instruction in this case

The misaligned load test-case now passes.

Whenever an exception is reported during Execution, it is forwarded to
PowerDecode2. After Execution finishes, Issue notices this, and returns
directly to Decode, without updating PC, SVSTATE, etc. The exception
condition is always cleared after a Decode, to prepare the stage for
a new Execution.

2 weeks agoinitial commit of sim state class
klehman [Wed, 8 Sep 2021 13:03:13 +0000 (09:03 -0400)]
initial commit of sim state class

2 weeks agoMonitor the exception input to PowerDecoder2
Cesar Strauss [Wed, 8 Sep 2021 09:26:15 +0000 (06:26 -0300)]
Monitor the exception input to PowerDecoder2

2 weeks agoRemove default argument for dict.get()
Cesar Strauss [Wed, 8 Sep 2021 09:25:18 +0000 (06:25 -0300)]
Remove default argument for dict.get()

1) The default is already None.
2) It really doesn't accept keyword arguments

2 weeks agofun fixing of get_core_hdl_regs, "yield from"
Luke Kenneth Casson Leighton [Tue, 7 Sep 2021 21:37:06 +0000 (22:37 +0100)]
fun fixing of get_core_hdl_regs, "yield from"

2 weeks agomove functions to above where they are called
Luke Kenneth Casson Leighton [Tue, 7 Sep 2021 21:31:28 +0000 (22:31 +0100)]
move functions to above where they are called

2 weeks agobreakout of register collection and compare
klehman [Tue, 7 Sep 2021 21:15:42 +0000 (17:15 -0400)]
breakout of register collection and compare

2 weeks agoFix typo.
Cesar Strauss [Tue, 7 Sep 2021 19:11:15 +0000 (16:11 -0300)]
Fix typo.

2 weeks agoadd TODO code-comments
Luke Kenneth Casson Leighton [Tue, 7 Sep 2021 13:44:05 +0000 (14:44 +0100)]
add TODO code-comments
related to https://bugs.libre-soc.org/show_bug.cgi?id=686

2 weeks agowhitespace, add bug ref number to test API
Luke Kenneth Casson Leighton [Tue, 7 Sep 2021 13:40:39 +0000 (14:40 +0100)]
whitespace, add bug ref number to test API

2 weeks agoanother batch of ready/valid i/o prefix-suffix swaps
Luke Kenneth Casson Leighton [Fri, 3 Sep 2021 07:13:14 +0000 (08:13 +0100)]
another batch of ready/valid i/o prefix-suffix swaps

3 weeks agoanooother valid_o to convert to o_valid
Luke Kenneth Casson Leighton [Tue, 31 Aug 2021 20:27:08 +0000 (21:27 +0100)]
anooother valid_o to convert to o_valid

3 weeks agoupdate ready/valid in shift_rot test_pipe_caller
Luke Kenneth Casson Leighton [Tue, 31 Aug 2021 20:20:02 +0000 (21:20 +0100)]
update ready/valid in shift_rot test_pipe_caller

3 weeks agofix test_all_values_covered, missed import when moving test cases to openpower.git
Jacob Lifshay [Tue, 31 Aug 2021 04:54:04 +0000 (21:54 -0700)]
fix test_all_values_covered, missed import when moving test cases to openpower.git

3 weeks agoupdate ready/valid i/o_ prefix in div test helper.py
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 16:38:31 +0000 (17:38 +0100)]
update ready/valid i/o_ prefix in div test helper.py

3 weeks agofix ready/valid i/o prefix in ALU test
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 14:33:41 +0000 (15:33 +0100)]
fix ready/valid i/o prefix in ALU test

3 weeks agofix CR tests valid/ready naming
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 12:26:49 +0000 (13:26 +0100)]
fix CR tests valid/ready naming

3 weeks agomissed valid/ready_i/o to o/i_ conversion
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 11:39:26 +0000 (12:39 +0100)]
missed valid/ready_i/o to o/i_ conversion

3 weeks agomissed valid/ready_i/o to o/i_ conversion
Luke Kenneth Casson Leighton [Mon, 30 Aug 2021 11:36:54 +0000 (12:36 +0100)]
missed valid/ready_i/o to o/i_ conversion

3 weeks agounnecessary signal rename ivalid_i to ii_valid (reverting)
Luke Kenneth Casson Leighton [Sun, 29 Aug 2021 21:00:59 +0000 (22:00 +0100)]
unnecessary signal rename ivalid_i to ii_valid (reverting)

4 weeks agoreplace data_o with o_data and data_i with i_data as well
Luke Kenneth Casson Leighton [Tue, 24 Aug 2021 11:53:06 +0000 (12:53 +0100)]
replace data_o with o_data and data_i with i_data as well
a little more care involved here due to names such as st_data_o
and others

4 weeks agobig rename, global/search/replace of ready_o with o_ready and the other
Luke Kenneth Casson Leighton [Tue, 24 Aug 2021 10:22:14 +0000 (11:22 +0100)]
big rename, global/search/replace of ready_o with o_ready and the other
> 4 signals as well, valid_i -> i_valid
> https://libera.irclog.whitequark.org/nmigen/2021-08-24#30728292;
> to be consistent with nmigen standards

4 weeks agoremove svanalysis from Makefile, it is now part of openpower-isa
Luke Kenneth Casson Leighton [Sun, 22 Aug 2021 09:43:26 +0000 (10:43 +0100)]
remove svanalysis from Makefile, it is now part of openpower-isa

5 weeks agofix "link addr-go direct to rel"
Tobias Platen [Tue, 17 Aug 2021 18:06:10 +0000 (20:06 +0200)]
fix "link addr-go direct to rel"

5 weeks agoEnable LD/ST exception test case
Cesar Strauss [Tue, 17 Aug 2021 11:37:47 +0000 (08:37 -0300)]
Enable LD/ST exception test case

It helps for implementing exception handling in TestIssuer

5 weeks agoClear operand latch on a terminating condition
Cesar Strauss [Tue, 17 Aug 2021 11:11:19 +0000 (08:11 -0300)]
Clear operand latch on a terminating condition

5 weeks agoAdd exc_o.happened to the conditions for terminating the CompUnit FSM
Cesar Strauss [Tue, 17 Aug 2021 10:18:00 +0000 (07:18 -0300)]
Add exc_o.happened to the conditions for terminating the CompUnit FSM

Otherwise, a failed load will hang indefinitely, waiting for data that
never comes.

5 weeks agoFix activation of cancel signal
Cesar Strauss [Tue, 17 Aug 2021 10:13:04 +0000 (07:13 -0300)]
Fix activation of cancel signal

As an active low signal, the conditions to cancel must be ANDed together.
Being active high, exc_o.happened must be inverted.

5 weeks agoAdjust PortInterface traces according to MMU option
Cesar Strauss [Mon, 16 Aug 2021 21:39:39 +0000 (18:39 -0300)]
Adjust PortInterface traces according to MMU option

The hierarchy of PortInterface changes when the MMU is present. Set the
correct module path, so the traces don't vanish in the GTKWave document.

5 weeks agofix renamed symbols
Tobias Platen [Mon, 16 Aug 2021 18:25:14 +0000 (20:25 +0200)]
fix renamed symbols

5 weeks agoadd WIP DCBZTestCase
Tobias Platen [Mon, 16 Aug 2021 18:02:06 +0000 (20:02 +0200)]
add WIP DCBZTestCase

6 weeks agoGitLab-CI: Only run tests in src/
Jonathan Neuschäfer [Wed, 11 Aug 2021 07:46:11 +0000 (09:46 +0200)]
GitLab-CI: Only run tests in src/

Specifically, the tests in unused_please_ignore_completely/ should not
be run. Some of them would fail, but it doesn't matter.

7 weeks agomove unused directory out of src, to indicate "ignore completely"
Luke Kenneth Casson Leighton [Sun, 1 Aug 2021 17:46:55 +0000 (18:46 +0100)]
move unused directory out of src, to indicate "ignore completely"

7 weeks agoimport setup_i_memory from soc.simple.test.test_runner
Jonathan Neuschäfer [Sat, 31 Jul 2021 22:25:34 +0000 (00:25 +0200)]
import setup_i_memory from soc.simple.test.test_runner

This function was moved in commit 8482a3ed
("split out TestRunner into separate module").

7 weeks agosoc.simple.test: Rename setup_test_memory to avoid nosetest calling it
Jonathan Neuschäfer [Sun, 1 Aug 2021 17:08:50 +0000 (19:08 +0200)]
soc.simple.test: Rename setup_test_memory to avoid nosetest calling it

7 weeks agoRename test_dcache, which can't be invoked by test runners
Jonathan Neuschäfer [Sat, 31 Jul 2021 22:43:26 +0000 (00:43 +0200)]
Rename test_dcache, which can't be invoked by test runners

Functions named *test_* are invoked by test runners, such as nosetests,
but test_dcache was not written with this behavior in mind. Rename it to
avoid invocation.

Maybe the main block at the end of a file should now be converted into a
test that *is* invoked by test runners.

7 weeks agosimulator/test_sim.py should not have been added
Luke Kenneth Casson Leighton [Sun, 1 Aug 2021 17:39:27 +0000 (18:39 +0100)]
simulator/test_sim.py should not have been added

7 weeks agopartial fix for src/soc/experiment/compldst_multi.py
Tobias Platen [Sat, 31 Jul 2021 16:49:45 +0000 (18:49 +0200)]
partial fix for src/soc/experiment/compldst_multi.py

7 weeks agopartially fix unit test in compldst_multi.py
Tobias Platen [Fri, 30 Jul 2021 18:59:24 +0000 (20:59 +0200)]
partially fix unit test in compldst_multi.py

8 weeks agocompldst_multi: add debug output for dcbz
Tobias Platen [Mon, 26 Jul 2021 18:42:21 +0000 (20:42 +0200)]
compldst_multi: add debug output for dcbz

2 months agoadd test_issuer_dcache.py
Tobias Platen [Sat, 24 Jul 2021 11:25:49 +0000 (13:25 +0200)]
add test_issuer_dcache.py

2 months agoldst: cleanup debug outputs
Tobias Platen [Fri, 23 Jul 2021 18:49:52 +0000 (20:49 +0200)]
ldst: cleanup debug outputs

2 months agotest_dcbz_pi.py: dcbz now working
Tobias Platen [Fri, 23 Jul 2021 18:48:37 +0000 (20:48 +0200)]
test_dcbz_pi.py: dcbz now working

2 months agorevert accidential delete in test_pi2ls.py causing tests to break
Tobias Platen [Wed, 21 Jul 2021 19:04:24 +0000 (21:04 +0200)]
revert accidential delete in test_pi2ls.py causing tests to break

2 months agotest_dcbz_pi.py: do not use problem state
Tobias Platen [Wed, 21 Jul 2021 18:02:48 +0000 (20:02 +0200)]
test_dcbz_pi.py: do not use problem state

2 months agoupdate pi_dcbz function
Tobias Platen [Wed, 21 Jul 2021 17:57:55 +0000 (19:57 +0200)]
update pi_dcbz function

2 months agosrc/soc/config/test/test_pi2ls.py: add more debug outputs
Tobias Platen [Mon, 19 Jul 2021 19:01:38 +0000 (21:01 +0200)]
src/soc/config/test/test_pi2ls.py: add more debug outputs

2 months agotest_dcbz_pi.py: more work on unit test
Tobias Platen [Mon, 19 Jul 2021 18:38:05 +0000 (20:38 +0200)]
test_dcbz_pi.py: more work on unit test