soc.git
8 months agostart to read RM CSV files
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 15:02:59 +0000 (15:02 +0000)]
start to read RM CSV files

8 months agoadd beginnings of svp64 assembly translator
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 13:23:58 +0000 (13:23 +0000)]
add beginnings of svp64 assembly translator

8 months agoadd example on how to access regs list for cmp
Luke Kenneth Casson Leighton [Fri, 22 Jan 2021 20:04:31 +0000 (20:04 +0000)]
add example on how to access regs list for cmp

9 months agotest_issuer_mmu_data_path.py: test both ld and st instructions
Tobias Platen [Tue, 19 Jan 2021 18:54:45 +0000 (19:54 +0100)]
test_issuer_mmu_data_path.py: test both ld and st instructions

9 months agoconnect LDSTException to MMU and DCache
Tobias Platen [Tue, 19 Jan 2021 18:40:07 +0000 (19:40 +0100)]
connect LDSTException to MMU and DCache

9 months agoconnect wishbone bus to test memory
Tobias Platen [Tue, 19 Jan 2021 17:21:50 +0000 (18:21 +0100)]
connect wishbone bus to test memory

9 months agouncomment #FIXME in unit_test
Tobias Platen [Mon, 18 Jan 2021 19:51:59 +0000 (20:51 +0100)]
uncomment #FIXME in unit_test

9 months agofu/mmu/fsm.py: connect valid and load signals
Tobias Platen [Mon, 18 Jan 2021 17:25:13 +0000 (18:25 +0100)]
fu/mmu/fsm.py: connect valid and load signals

9 months agoadd test memory for simulation
Tobias Platen [Sun, 17 Jan 2021 16:48:26 +0000 (17:48 +0100)]
add test memory for simulation

9 months agocleanup test_issuer_mmu_data_path.py
Tobias Platen [Sun, 17 Jan 2021 15:59:22 +0000 (16:59 +0100)]
cleanup test_issuer_mmu_data_path.py

9 months agoclean up test case for tlbie and dcbz
Tobias Platen [Sat, 16 Jan 2021 17:31:48 +0000 (18:31 +0100)]
clean up test case for tlbie and dcbz

9 months agomove microwatt_mmu bool variable to pspec
Tobias Platen [Sat, 16 Jan 2021 16:43:46 +0000 (17:43 +0100)]
move microwatt_mmu bool variable to pspec

9 months agoadd new unittest: test_issuer_mmu_data_path.py
Tobias Platen [Sat, 16 Jan 2021 10:00:07 +0000 (11:00 +0100)]
add new unittest: test_issuer_mmu_data_path.py

9 months agocleanup test_non_production_core.py
Tobias Platen [Fri, 15 Jan 2021 18:16:57 +0000 (19:16 +0100)]
cleanup test_non_production_core.py

9 months agoadd microwatt_mmu boolean variable to core and compunits
Tobias Platen [Fri, 15 Jan 2021 18:05:36 +0000 (19:05 +0100)]
add microwatt_mmu boolean variable to core and compunits

9 months agotest_non_production_core.py: fix hanging test
Tobias Platen [Fri, 15 Jan 2021 17:56:18 +0000 (18:56 +0100)]
test_non_production_core.py: fix hanging test

9 months agotest_non_production_core.py: wire instruction decoder to core
Tobias Platen [Fri, 15 Jan 2021 16:50:16 +0000 (17:50 +0100)]
test_non_production_core.py: wire instruction decoder to core

9 months agoadd test case for mmu+NonProductionCore
Tobias Platen [Thu, 14 Jan 2021 20:06:55 +0000 (21:06 +0100)]
add test case for mmu+NonProductionCore

9 months agoadd microwatt mmu config option to compunits.py
Tobias Platen [Sun, 10 Jan 2021 13:05:03 +0000 (14:05 +0100)]
add microwatt mmu config option to compunits.py

9 months agofix broken testcase for simple core
Tobias Platen [Fri, 8 Jan 2021 20:11:06 +0000 (21:11 +0100)]
fix broken testcase for simple core

9 months agoset initial_sprs, cleanup mfspr testprog
Tobias Platen [Thu, 7 Jan 2021 17:25:48 +0000 (18:25 +0100)]
set initial_sprs, cleanup mfspr testprog

9 months agomfspr is RT, SPR
Tobias Platen [Thu, 7 Jan 2021 16:50:28 +0000 (17:50 +0100)]
mfspr is RT, SPR

9 months agofirst testcase for mmu: case_mfspr_after_invalid_load
Tobias Platen [Wed, 6 Jan 2021 18:49:36 +0000 (19:49 +0100)]
first testcase for mmu: case_mfspr_after_invalid_load

9 months agofu/mmu/fsm.py: mfspr!=mtspr
Tobias Platen [Wed, 6 Jan 2021 18:26:52 +0000 (19:26 +0100)]
fu/mmu/fsm.py: mfspr!=mtspr

9 months agotest_countzero.py: rename output files
Tobias Platen [Mon, 4 Jan 2021 17:58:31 +0000 (18:58 +0100)]
test_countzero.py: rename output files

9 months agoAdd zero CR test case and fix comments
Cesar Strauss [Fri, 1 Jan 2021 21:05:38 +0000 (18:05 -0300)]
Add zero CR test case and fix comments

9 months agoAdd test cases with rc=1
Cesar Strauss [Fri, 1 Jan 2021 20:58:07 +0000 (17:58 -0300)]
Add test cases with rc=1

Checks that the CR port produces results.

9 months agoMake all ports the same size, on the test ALU
Cesar Strauss [Fri, 1 Jan 2021 20:38:57 +0000 (17:38 -0300)]
Make all ports the same size, on the test ALU

The old regspec API can't cope with different port sizes.
The CR port is now changed from 3 to "width" bits (16).
The problem was that cr.ok went into the fourth bit, messing with
the results.

9 months agoAdd CR output port to test cases
Cesar Strauss [Fri, 1 Jan 2021 18:34:24 +0000 (15:34 -0300)]
Add CR output port to test cases

Test cases can now set rc=1, and expect results in the CR port.
wrmask and dest_delay arrays have incremented their length accordingly.

9 months agoAdd CR to the output data port
Cesar Strauss [Fri, 1 Jan 2021 17:46:35 +0000 (14:46 -0300)]
Add CR to the output data port

9 months agoMake output write enables independent of valid_o
Cesar Strauss [Fri, 1 Jan 2021 15:06:48 +0000 (12:06 -0300)]
Make output write enables independent of valid_o

Just combinatiorally decode the operation.
This is because MultiCompUnit depends on *_ok being kept valid.

9 months agoMove NOP test case earlier
Cesar Strauss [Fri, 1 Jan 2021 14:11:24 +0000 (11:11 -0300)]
Move NOP test case earlier

Better way to see alu_o_ok being disabled during the instruction.

9 months agoDisable data value output on NOP
Cesar Strauss [Fri, 1 Jan 2021 12:59:49 +0000 (09:59 -0300)]
Disable data value output on NOP

9 months agoAdd condition register (CR) output
Cesar Strauss [Fri, 1 Jan 2021 12:54:45 +0000 (09:54 -0300)]
Add condition register (CR) output

9 months agoImplement and test NOP in the test ALU
Cesar Strauss [Thu, 31 Dec 2020 21:41:18 +0000 (18:41 -0300)]
Implement and test NOP in the test ALU

Change the output port from Signal to Data, to allow for the output to be
masked-out.

Specify a masked-out output in the NOP test case.

9 months agoDon't use OP_NOP for zero-delay subtraction
Cesar Strauss [Thu, 31 Dec 2020 20:43:34 +0000 (17:43 -0300)]
Don't use OP_NOP for zero-delay subtraction

We are going to implement an actual NOP

9 months agoTest first input port being masked out
Cesar Strauss [Thu, 31 Dec 2020 20:31:41 +0000 (17:31 -0300)]
Test first input port being masked out

9 months agoSign extend the second input port
Cesar Strauss [Thu, 31 Dec 2020 20:28:05 +0000 (17:28 -0300)]
Sign extend the second input port

9 months agoTest masked-out second input port
Cesar Strauss [Thu, 31 Dec 2020 20:06:56 +0000 (17:06 -0300)]
Test masked-out second input port

Sign extend uses only the first port.

9 months agoAdd sign extend to the Test ALU
Cesar Strauss [Thu, 31 Dec 2020 19:51:03 +0000 (16:51 -0300)]
Add sign extend to the Test ALU

9 months agoShow rdmaskn and wrmask in GTKWave
Cesar Strauss [Thu, 31 Dec 2020 13:36:58 +0000 (10:36 -0300)]
Show rdmaskn and wrmask in GTKWave

9 months agoUse the increment operator
Cesar Strauss [Thu, 31 Dec 2020 13:08:41 +0000 (10:08 -0300)]
Use the increment operator

9 months agoAdd support for masked write operations
Cesar Strauss [Thu, 31 Dec 2020 13:04:05 +0000 (10:04 -0300)]
Add support for masked write operations

Note that the test ALU currently does not have any masked writes.

9 months agoClarify reason for holding rdmaskn valid during the entire cycle
Cesar Strauss [Thu, 31 Dec 2020 12:20:13 +0000 (12:20 +0000)]
Clarify reason for holding rdmaskn valid during the entire cycle

9 months agoRemove previous version of the CompUnit parallel unit test
Cesar Strauss [Thu, 31 Dec 2020 10:42:27 +0000 (10:42 +0000)]
Remove previous version of the CompUnit parallel unit test

It was too detailed, modeling properties which are better checked by
formal verification.

Other than that, the new version has reached feature parity, so the old
code can finally be removed.

9 months agoOnly hold the decoder signals for one cycle, along with issue_i
Cesar Strauss [Thu, 31 Dec 2020 10:22:04 +0000 (10:22 +0000)]
Only hold the decoder signals for one cycle, along with issue_i

The exception is rdmaskn, which is not latched, and must be held valid
for the entire instrucion cycle.

9 months agoTest the rdmaskn control signal
Cesar Strauss [Wed, 30 Dec 2020 21:00:38 +0000 (21:00 +0000)]
Test the rdmaskn control signal

The operation issuer now can drive the rdmaskn signals, and check
that the operand fetch on any masked ports is supressed.

9 months agoRemove left-over comments.
Cesar Strauss [Tue, 29 Dec 2020 11:26:29 +0000 (11:26 +0000)]
Remove left-over comments.

The debug signals were removed in a previous commit, but the comment
lines remained.

9 months agoadd CR1 to power_enums
Luke Kenneth Casson Leighton [Mon, 28 Dec 2020 20:30:34 +0000 (20:30 +0000)]
add CR1 to power_enums

10 months agoAdd support for CXXSim simulation
Cesar Strauss [Sun, 20 Dec 2020 14:18:34 +0000 (11:18 -0300)]
Add support for CXXSim simulation

10 months agoIgnore formal verification output in the source directory
Cesar Strauss [Sun, 13 Dec 2020 18:16:29 +0000 (15:16 -0300)]
Ignore formal verification output in the source directory

This is similarly done in other sister directories.

10 months agoAllow more test cases to be run with CXXSim
Cesar Strauss [Sun, 13 Dec 2020 18:03:59 +0000 (15:03 -0300)]
Allow more test cases to be run with CXXSim

10 months agoskip madd, not implemented
Luke Kenneth Casson Leighton [Sat, 12 Dec 2020 16:37:49 +0000 (16:37 +0000)]
skip madd, not implemented

10 months agoupdate submodules
Luke Kenneth Casson Leighton [Wed, 9 Dec 2020 18:13:28 +0000 (18:13 +0000)]
update submodules

10 months agoupdate submodules
Luke Kenneth Casson Leighton [Wed, 9 Dec 2020 18:10:48 +0000 (18:10 +0000)]
update submodules

10 months agoDisplay the instruction type as a vector on cxxsim
Cesar Strauss [Mon, 7 Dec 2020 21:44:40 +0000 (18:44 -0300)]
Display the instruction type as a vector on cxxsim

It doesn't support enums traces yet.

10 months agoattempt to split into two separate GPIO banks due to a coriolis2 compile error
Luke Kenneth Casson Leighton [Sun, 6 Dec 2020 19:35:57 +0000 (19:35 +0000)]
attempt to split into two separate GPIO banks due to a coriolis2 compile error

10 months agoWhitespace
Cesar Strauss [Sun, 6 Dec 2020 12:31:31 +0000 (09:31 -0300)]
Whitespace

10 months agoUpdate GTKWave documents to work with latest cxxsim
Cesar Strauss [Sun, 6 Dec 2020 11:34:35 +0000 (08:34 -0300)]
Update GTKWave documents to work with latest cxxsim

* Hierarchy begins at "top", just like pysim
* Avoid intermediate signals, that work differently on both
* Use the new "submodule" style in write_gtkw

10 months agoWrite a GTKWave document to investigate why the proof fails
Cesar Strauss [Sat, 5 Dec 2020 12:40:20 +0000 (09:40 -0300)]
Write a GTKWave document to investigate why the proof fails

10 months agoUse the DummyALU regspec and its corresponding OpSubset
Cesar Strauss [Sat, 5 Dec 2020 12:37:18 +0000 (09:37 -0300)]
Use the DummyALU regspec and its corresponding OpSubset

10 months agoput ls180 litex bus width back to 32 bit temporarily
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 16:52:09 +0000 (16:52 +0000)]
put ls180 litex bus width back to 32 bit temporarily

10 months agoargh issue with yosys ABC
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 15:51:56 +0000 (15:51 +0000)]
argh issue with yosys ABC

10 months agoadd 3 more 4k SRAMs, change WB bus width to 64 in ls180 litex
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 15:34:33 +0000 (15:34 +0000)]
add 3 more 4k SRAMs, change WB bus width to 64 in ls180 litex

10 months agoFix signal names: go/rel -> go_i/rel_o
Cesar Strauss [Sat, 28 Nov 2020 17:59:30 +0000 (14:59 -0300)]
Fix signal names: go/rel -> go_i/rel_o

10 months agoFix some typos and whitespace
Cesar Strauss [Tue, 24 Nov 2020 11:06:30 +0000 (08:06 -0300)]
Fix some typos and whitespace

10 months agoPort the DummyALU test case to the new parallel issuer
Cesar Strauss [Tue, 24 Nov 2020 10:53:14 +0000 (07:53 -0300)]
Port the DummyALU test case to the new parallel issuer

In the process, fix its OpSubset to be consistent with the one which is
really used by this ALU.

This required adapting the issuer, to cope with the absence of some fields
in the OpSubset.

10 months agoResults are now a list, so "expected" should follow suit
Cesar Strauss [Mon, 23 Nov 2020 10:59:42 +0000 (07:59 -0300)]
Results are now a list, so "expected" should follow suit

10 months agoParameterize the issuer on the number of operands and results
Cesar Strauss [Mon, 23 Nov 2020 10:40:04 +0000 (07:40 -0300)]
Parameterize the issuer on the number of operands and results

This allows reuse for the DummyALU, which has three operands, but is
otherwise similar to the ALU in terms of operations.

Also, the issuer now creates the producers and consumers.

10 months agoRefactor the ALU operation issuer into a class
Cesar Strauss [Sun, 22 Nov 2020 22:07:32 +0000 (19:07 -0300)]
Refactor the ALU operation issuer into a class

This allows sharing its code with other similar test cases.

10 months agoPort the ALU test case to the new parallel test style
Cesar Strauss [Sun, 22 Nov 2020 19:05:15 +0000 (16:05 -0300)]
Port the ALU test case to the new parallel test style

Mostly copy & paste from the Shifter, but using the operation spec
for the ALU.

The producers transaction count will fall behind on zero_a and imm_ok
executions, so these counters were added to the invariant check.

10 months agoAdd a GTKWave document to the ALU test case
Cesar Strauss [Sun, 22 Nov 2020 17:12:19 +0000 (14:12 -0300)]
Add a GTKWave document to the ALU test case

10 months agosimplify litex-core wishbone interfaces
Luke Kenneth Casson Leighton [Sat, 14 Nov 2020 18:41:29 +0000 (18:41 +0000)]
simplify litex-core wishbone interfaces

11 months agoSeparate input and output ports by color
Cesar Strauss [Thu, 19 Nov 2020 10:52:05 +0000 (07:52 -0300)]
Separate input and output ports by color

11 months agoExplain the test cases
Cesar Strauss [Thu, 19 Nov 2020 10:38:11 +0000 (07:38 -0300)]
Explain the test cases

11 months agoSeparate individual traces for each rel_o/go_i port
Cesar Strauss [Wed, 18 Nov 2020 10:59:15 +0000 (07:59 -0300)]
Separate individual traces for each rel_o/go_i port

Use the new "bit" attribute to select individual bits from the
wide rel_o/go_i signals.

11 months agotestcase for dcbz
Tobias Platen [Tue, 17 Nov 2020 19:20:16 +0000 (20:20 +0100)]
testcase for dcbz

11 months agoAdd a transaction counter to producers and consumers
Cesar Strauss [Mon, 16 Nov 2020 22:17:19 +0000 (19:17 -0300)]
Add a transaction counter to producers and consumers

By comparing counts, we assure no data is duplicated or dropped.

11 months agoadd class LoadStore1(PortInterfaceBase)
Tobias Platen [Mon, 16 Nov 2020 19:02:05 +0000 (20:02 +0100)]
add class LoadStore1(PortInterfaceBase)

11 months agoImplement ResultConsumer and port the Shifter unit tests to it.
Cesar Strauss [Sun, 15 Nov 2020 20:20:19 +0000 (17:20 -0300)]
Implement ResultConsumer and port the Shifter unit tests to it.

11 months agoMove the DUT driver to within the test case process
Cesar Strauss [Sat, 14 Nov 2020 22:29:05 +0000 (19:29 -0300)]
Move the DUT driver to within the test case process

This reduces verbosity, as parameters are replaced by local variables in
the external scope.
Another way would be to save the parameters in a class, and transform the
function into a method.

11 months agoFix and enable the regspec test for the Shifter
Cesar Strauss [Sat, 14 Nov 2020 18:15:44 +0000 (15:15 -0300)]
Fix and enable the regspec test for the Shifter

1) use correct names for the Shifter ports in the regspec
2) migrate to the new OperandProducer
3) add the test on __main__

11 months agosigh, direction wrong in IOtypes litex core
Luke Kenneth Casson Leighton [Sat, 14 Nov 2020 14:29:26 +0000 (14:29 +0000)]
sigh, direction wrong in IOtypes litex core

11 months agoreduce number of nc in ls180 to 24
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 17:51:13 +0000 (17:51 +0000)]
reduce number of nc in ls180 to 24

11 months agoreduce clkcsel ls180 width (2 pins), rename pll_18 signal
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 17:47:46 +0000 (17:47 +0000)]
reduce clkcsel ls180 width (2 pins), rename pll_18 signal

11 months agorename and add pll lock signal to ls180
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 16:10:42 +0000 (16:10 +0000)]
rename and add pll lock signal to ls180

11 months agorename ls180 litex pll_48 output to pll_18
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 16:04:15 +0000 (16:04 +0000)]
rename ls180 litex pll_48 output to pll_18

11 months agoadd enable/disable arguments (not ideal but it works) to issuer_verilog.py
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 15:48:21 +0000 (15:48 +0000)]
add enable/disable arguments (not ideal but it works) to issuer_verilog.py

11 months agoremove io_in/out now it is not needed for niolib
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 15:45:51 +0000 (15:45 +0000)]
remove io_in/out now it is not needed for niolib

11 months agodcbz and tlbie first test, still incomplete
Tobias Platen [Wed, 11 Nov 2020 18:51:41 +0000 (19:51 +0100)]
dcbz and tlbie first test, still incomplete

11 months agofu/mmu/test/test_pipe_caller.py test case for mfspr
Tobias Platen [Wed, 11 Nov 2020 18:09:52 +0000 (19:09 +0100)]
fu/mmu/test/test_pipe_caller.py test case for mfspr

11 months agoadd build commands to Makefile for versa ecp5
Luke Kenneth Casson Leighton [Tue, 10 Nov 2020 19:44:09 +0000 (19:44 +0000)]
add build commands to Makefile for versa ecp5

11 months agosubmodule update
Luke Kenneth Casson Leighton [Tue, 10 Nov 2020 19:37:49 +0000 (19:37 +0000)]
submodule update

11 months agoremove ClockSelect module, use DummyPLL
Luke Kenneth Casson Leighton [Tue, 10 Nov 2020 16:40:33 +0000 (16:40 +0000)]
remove ClockSelect module, use DummyPLL

11 months agoadd separate DummyPLL module, according to API discussed at
Luke Kenneth Casson Leighton [Tue, 10 Nov 2020 15:49:56 +0000 (15:49 +0000)]
add separate DummyPLL module, according to API discussed at
https://bugs.libre-soc.org/show_bug.cgi?id=155#c21
;

11 months agommu fsm testcase: add check_fsm_outputs based on function from soc/fu/div/test/helper.py
Tobias Platen [Sun, 8 Nov 2020 12:05:36 +0000 (13:05 +0100)]
mmu fsm testcase: add check_fsm_outputs based on function from soc/fu/div/test/helper.py

11 months agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Sun, 8 Nov 2020 09:31:11 +0000 (10:31 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

11 months agommu/fsm: test case for mtspr
Tobias Platen [Sun, 8 Nov 2020 09:30:08 +0000 (10:30 +0100)]
mmu/fsm: test case for mtspr

11 months agoupdate submodule
Luke Kenneth Casson Leighton [Sat, 7 Nov 2020 22:27:38 +0000 (22:27 +0000)]
update submodule

11 months agofixed a bug in src/soc/fu/mmu/fsm.py
Tobias Platen [Sat, 7 Nov 2020 14:43:07 +0000 (15:43 +0100)]
fixed a bug in src/soc/fu/mmu/fsm.py