soc.git
15 months agonope. put it back and connect to platform pads in LS180Platform
Luke Kenneth Casson Leighton [Sat, 3 Oct 2020 19:27:23 +0000 (20:27 +0100)]
nope.  put it back and connect to platform pads in LS180Platform

15 months agomove iopad litex creation to ls180soc.py
Luke Kenneth Casson Leighton [Sat, 3 Oct 2020 19:14:20 +0000 (20:14 +0100)]
move iopad litex creation to ls180soc.py

15 months agominor reorg on JTAG, allow alternative pinset dict to be passed in
Luke Kenneth Casson Leighton [Sat, 3 Oct 2020 13:20:19 +0000 (14:20 +0100)]
minor reorg on JTAG, allow alternative pinset dict to be passed in

15 months agoadd regression testcase
Jacob Lifshay [Sat, 3 Oct 2020 01:04:39 +0000 (18:04 -0700)]
add regression testcase

15 months agoupdate submodule
Jacob Lifshay [Sat, 3 Oct 2020 01:04:17 +0000 (18:04 -0700)]
update submodule

15 months agoicache.py add req_hit_way as arg to icache_comb, actually ran file this
Cole Poirier [Fri, 2 Oct 2020 21:18:28 +0000 (14:18 -0700)]
icache.py add req_hit_way as arg to icache_comb, actually ran file this
time to make sure it's correct, fixes https://bugs.libre-soc.org/show_bug.cgi?id=485#c37

15 months agoadd pinmux generator to create litex pinmap
Luke Kenneth Casson Leighton [Fri, 2 Oct 2020 18:54:22 +0000 (19:54 +0100)]
add pinmux generator to create litex pinmap

15 months agoadd pinmux as submodule
Luke Kenneth Casson Leighton [Fri, 2 Oct 2020 18:35:49 +0000 (19:35 +0100)]
add pinmux as submodule

15 months agoicache.py add missing comb signal assignments per https://bugs.libre-soc.org/show_bug...
Cole Poirier [Thu, 1 Oct 2020 23:17:57 +0000 (16:17 -0700)]
icache.py add missing comb signal assignments per https://bugs.libre-soc.org/show_bug.cgi?id=485#c32

15 months agoarg CacheRam read output needs delay by 1 cycle
Luke Kenneth Casson Leighton [Thu, 1 Oct 2020 17:39:58 +0000 (18:39 +0100)]
arg CacheRam read output needs delay by 1 cycle

15 months agodo not pass cache row array around, just the current row
Luke Kenneth Casson Leighton [Thu, 1 Oct 2020 17:35:58 +0000 (18:35 +0100)]
do not pass cache row array around, just the current row

15 months agorevert bug in icache wishbone ack
Luke Kenneth Casson Leighton [Thu, 1 Oct 2020 17:16:27 +0000 (18:16 +0100)]
revert bug in icache wishbone ack

15 months agoadd clksel, pll to ls180
Luke Kenneth Casson Leighton [Thu, 1 Oct 2020 17:10:26 +0000 (18:10 +0100)]
add clksel, pll to ls180

15 months agocreate dummy PLL block, connect up to core and clock-selector
Luke Kenneth Casson Leighton [Thu, 1 Oct 2020 13:28:54 +0000 (14:28 +0100)]
create dummy PLL block, connect up to core and clock-selector

15 months agoAdd GTKWave document to test_compunit_fsm
Cesar Strauss [Thu, 1 Oct 2020 10:44:25 +0000 (07:44 -0300)]
Add GTKWave document to test_compunit_fsm

15 months agoadd I2C into ls180
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 21:33:25 +0000 (22:33 +0100)]
add I2C into ls180

15 months agoadd ASIC version of I2C Master
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 21:30:44 +0000 (22:30 +0100)]
add ASIC version of I2C Master

15 months agoclean up row store and wb adr in icache
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 12:52:17 +0000 (13:52 +0100)]
clean up row store and wb adr in icache

15 months agohmm only set wishbone address if ack is actually received
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 12:23:08 +0000 (13:23 +0100)]
hmm only set wishbone address if ack is actually received

15 months agoadd more debug prints in icache
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 11:47:37 +0000 (12:47 +0100)]
add more debug prints in icache

15 months agoremove more reviewed comments
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:53:10 +0000 (10:53 +0100)]
remove more reviewed comments

15 months agoremove reviewed comments
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:45:50 +0000 (10:45 +0100)]
remove reviewed comments

15 months agocomb on wr_index not sync
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:30:41 +0000 (10:30 +0100)]
comb on wr_index not sync

15 months agostart removing reviewed comments
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:30:12 +0000 (10:30 +0100)]
start removing reviewed comments

15 months agouse same constant name (confusing otherwise)
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:22:29 +0000 (10:22 +0100)]
use same constant name (confusing otherwise)

15 months agoneed asserts
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:22:08 +0000 (10:22 +0100)]
need asserts

15 months agohalve the number of icache lines for now
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:19:00 +0000 (10:19 +0100)]
halve the number of icache lines for now

15 months agouse Repl rather than for-loop to copy bit
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:17:38 +0000 (10:17 +0100)]
use Repl rather than for-loop to copy bit

15 months agomove loop invariant test out of loop
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:09:02 +0000 (10:09 +0100)]
move loop invariant test out of loop

15 months agoreduce size of ilang file by a factor of FIVE
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 09:03:34 +0000 (10:03 +0100)]
reduce size of ilang file by a factor of FIVE

15 months agostore tag in temp signal
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 08:55:58 +0000 (09:55 +0100)]
store tag in temp signal

15 months agoreduce gate usage by getting cache row only not entire cache array
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 08:51:14 +0000 (09:51 +0100)]
reduce gate usage by getting cache row only not entire cache array

15 months agofix read_tag to use word_select correctly
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 08:45:56 +0000 (09:45 +0100)]
fix read_tag to use word_select correctly

15 months agoforgot to add PLRUs as submodules
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 08:43:40 +0000 (09:43 +0100)]
forgot to add PLRUs as submodules

15 months agoicache.py fix combinatorial loop with by testing temp stbs_zero and
Cole Poirier [Tue, 29 Sep 2020 18:57:28 +0000 (11:57 -0700)]
icache.py fix combinatorial loop with by testing temp stbs_zero and
setting Signal stbs_done

15 months agoicache.py fix is_last_row_addr, get_next_row_addr
Cole Poirier [Tue, 29 Sep 2020 18:45:18 +0000 (11:45 -0700)]
icache.py fix is_last_row_addr, get_next_row_addr

15 months agoicache.py trying to sort out test failure, added r field req_adr to
Cole Poirier [Tue, 29 Sep 2020 18:27:36 +0000 (11:27 -0700)]
icache.py trying to sort out test failure, added r field req_adr to
properly implement WB spec compliant adressing

15 months agoicache.py fix test stbs_done signal, not stbs_zero temp signal
Cole Poirier [Tue, 29 Sep 2020 18:00:28 +0000 (11:00 -0700)]
icache.py fix test stbs_done signal, not stbs_zero temp signal

15 months agoicache.py fix rarange
Cole Poirier [Tue, 29 Sep 2020 17:55:49 +0000 (10:55 -0700)]
icache.py fix rarange

15 months agoicache.py fixed numerous bugs as specified by lkcl on bugzilla, now
Cole Poirier [Tue, 29 Sep 2020 17:37:20 +0000 (10:37 -0700)]
icache.py fixed numerous bugs as specified by lkcl on bugzilla, now
passes first unit test!

16 months agoicache.py use d_out as input to assignment instead of as assignee, now
Cole Poirier [Mon, 28 Sep 2020 23:07:11 +0000 (16:07 -0700)]
icache.py use d_out as input to assignment instead of as assignee, now
the right stuff is connected and the test fails in an interesting way,
add signal names

16 months agoreduce not-connected IO pins
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 15:58:48 +0000 (16:58 +0100)]
reduce not-connected IO pins

16 months agomissing pspec
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 15:58:29 +0000 (16:58 +0100)]
missing pspec

16 months agoconnect SDRAM dqm to wrdata_mask
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 15:53:23 +0000 (16:53 +0100)]
connect SDRAM dqm to wrdata_mask

16 months agolots of sorting out iopads
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 11:33:33 +0000 (12:33 +0100)]
lots of sorting out iopads
* add sdram clock
* rename serial to uart
* disable I2C for now (needs bi-directional pads)
* make sdram and sd0 "en" only one pin (sort out litex issue)
* add "NC" pins so that there are no missing pins

16 months agoadd "nocore" option to build verilog
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 11:27:34 +0000 (12:27 +0100)]
add "nocore" option to build verilog

16 months agoswitch off internal gpio (testing)
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 11:25:17 +0000 (12:25 +0100)]
switch off internal gpio (testing)

16 months agorewrite ilang file after litex ls180 build
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 11:22:02 +0000 (12:22 +0100)]
rewrite ilang file after litex ls180 build

16 months agohad to over-ride the wishbone functions on C4M TAP
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 11:21:31 +0000 (12:21 +0100)]
had to over-ride the wishbone functions on C4M TAP
the default features assume stall, which is not available

16 months agoicache.py fix translation mistake
Cole Poirier [Sun, 27 Sep 2020 16:22:06 +0000 (09:22 -0700)]
icache.py fix translation mistake

16 months agoConvert yet another few tests to be able to use latest cxxsim
Cesar Strauss [Sun, 27 Sep 2020 14:58:06 +0000 (11:58 -0300)]
Convert yet another few tests to be able to use latest cxxsim

16 months agoadd Makefile for creating ls180.il
Luke Kenneth Casson Leighton [Sun, 27 Sep 2020 09:31:13 +0000 (10:31 +0100)]
add Makefile for creating ls180.il

16 months agorename sys_clk_i to clk_24_i
Luke Kenneth Casson Leighton [Sun, 27 Sep 2020 08:17:31 +0000 (09:17 +0100)]
rename sys_clk_i to clk_24_i

16 months agoadd clock selection mechanism
Luke Kenneth Casson Leighton [Sun, 27 Sep 2020 08:08:25 +0000 (09:08 +0100)]
add clock selection mechanism

16 months agoDMI-to-JTAG needed to be "sync" to get ack/resp right
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 23:31:30 +0000 (00:31 +0100)]
DMI-to-JTAG needed to be "sync" to get ack/resp right

16 months agodo not use simdec2 in test_pipe_caller
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 19:57:07 +0000 (20:57 +0100)]
do not use simdec2 in test_pipe_caller

16 months agofix annoying alu test_pipe_caller bug, missing asmcode
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 19:55:10 +0000 (20:55 +0100)]
fix annoying alu test_pipe_caller bug, missing asmcode

16 months agoadd alternative PowerDecode2 to branch test_pipe_caller
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 18:44:42 +0000 (19:44 +0100)]
add alternative PowerDecode2 to branch test_pipe_caller

16 months agoConvert a few more tests to be able to use cxxsim
Cesar Strauss [Sat, 26 Sep 2020 17:30:09 +0000 (14:30 -0300)]
Convert a few more tests to be able to use cxxsim

16 months agotry svf test of DMI MSR
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 17:30:41 +0000 (18:30 +0100)]
try svf test of DMI MSR

16 months agomake check of LDSTMode.update conditional in PowerDecoder2
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 17:30:24 +0000 (18:30 +0100)]
make check of LDSTMode.update conditional in PowerDecoder2

16 months agoadd ls180io.py
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 15:08:45 +0000 (16:08 +0100)]
add ls180io.py

16 months agoadd openocd script to fire off svf test
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 15:08:27 +0000 (16:08 +0100)]
add openocd script to fire off svf test

16 months agoget openocd svf test running, replicating jtag test
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 15:06:42 +0000 (16:06 +0100)]
get openocd svf test running, replicating jtag test

16 months agoput test into "server" mode for connecting with openocd
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 14:51:09 +0000 (15:51 +0100)]
put test into "server" mode for connecting with openocd

16 months agocreate client-server version of jtag debug unit test
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 14:42:24 +0000 (15:42 +0100)]
create client-server version of jtag debug unit test

16 months agocreate client-server version of jtag debug unit test
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 14:41:53 +0000 (15:41 +0100)]
create client-server version of jtag debug unit test

16 months agoclass-ify jtagremote
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 14:13:42 +0000 (15:13 +0100)]
class-ify jtagremote

16 months agosend/receive jtagremote protocol
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 12:28:31 +0000 (13:28 +0100)]
send/receive jtagremote protocol

16 months agobasic client/server socket example
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 11:41:40 +0000 (12:41 +0100)]
basic client/server socket example

16 months agoadd openocd configs
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 11:19:24 +0000 (12:19 +0100)]
add openocd configs

16 months agoreduce sdram pins to smaller address and only 1 cs_n
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 11:17:40 +0000 (12:17 +0100)]
reduce sdram pins to smaller address and only 1 cs_n

16 months agoonly enable pads connections for ls180 for now
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 11:17:04 +0000 (12:17 +0100)]
only enable pads connections for ls180 for now

16 months agoicache.py fix several subtle bugs that were lines that I had missed from
Cole Poirier [Fri, 25 Sep 2020 20:12:04 +0000 (13:12 -0700)]
icache.py fix several subtle bugs that were lines that I had missed from
icache.vhdl, as well as sneaky incorrect indentations, now it runs,
passing the 'assert valid', but failing on the
'assert insn@0x0000000000000004=00000001', time to use vcd to debug

16 months agowb_types.py add reset value of 0b11111111 for WBSelType, which is the value of the...
Cole Poirier [Fri, 25 Sep 2020 20:08:19 +0000 (13:08 -0700)]
wb_types.py add reset value of 0b11111111 for WBSelType, which is the value of the WBMasterOut object's field 'sel', wich is the 'r.wb.sel' value that appears in both icache.py and dcache.py, source of this reset value is line 614 of icache.vhdl

16 months agoUse nmutil simulator module to simplify choosing among engines
Cesar Strauss [Thu, 24 Sep 2020 22:34:28 +0000 (19:34 -0300)]
Use nmutil simulator module to simplify choosing among engines

16 months agodo not have to use uart_litex gpio_litex names
Luke Kenneth Casson Leighton [Thu, 24 Sep 2020 20:17:05 +0000 (21:17 +0100)]
do not have to use uart_litex gpio_litex names

16 months agoadd comments
Luke Kenneth Casson Leighton [Thu, 24 Sep 2020 20:00:56 +0000 (21:00 +0100)]
add comments

16 months agoenable GPIO pads through C4M JTAG
Luke Kenneth Casson Leighton [Thu, 24 Sep 2020 19:55:10 +0000 (20:55 +0100)]
enable GPIO pads through C4M JTAG

16 months agoc4m iopad integration working
Luke Kenneth Casson Leighton [Thu, 24 Sep 2020 19:39:13 +0000 (20:39 +0100)]
c4m iopad integration working

16 months agoicache.py add some missing lines from icache.vhdl, add sram for sim, fix
Cole Poirier [Thu, 24 Sep 2020 19:15:20 +0000 (12:15 -0700)]
icache.py add some missing lines from icache.vhdl, add sram for sim, fix
bug due to main state machine being indednted one level to far an thus
not triggered properly

16 months agomem_types.py wb_types.py add name constructor to all RecordObjects
Cole Poirier [Thu, 24 Sep 2020 17:23:45 +0000 (10:23 -0700)]
mem_types.py wb_types.py add name constructor to all RecordObjects

16 months agoicache.py fixed all errors that raised python exceptions, now runs sim, sim doenst...
Cole Poirier [Thu, 24 Sep 2020 17:20:02 +0000 (10:20 -0700)]
icache.py fixed all errors that raised python exceptions, now runs sim, sim doenst work properly, time to use gtkwave to debug

16 months agoFix whitespace, remove unused imports
Cesar Strauss [Thu, 24 Sep 2020 16:27:53 +0000 (13:27 -0300)]
Fix whitespace, remove unused imports

16 months agobrackets round imports looks cleaner?
Luke Kenneth Casson Leighton [Thu, 24 Sep 2020 12:27:33 +0000 (13:27 +0100)]
brackets round imports looks cleaner?

16 months agoadd jtag c4m pins which gives us a way to connect IO pads for JTAG debugging
Luke Kenneth Casson Leighton [Thu, 24 Sep 2020 12:22:00 +0000 (13:22 +0100)]
add jtag c4m pins which gives us a way to connect IO pads for JTAG debugging

16 months agoUse nmutil simulator module to simplify choosing among engines
Cesar Strauss [Thu, 24 Sep 2020 11:45:17 +0000 (08:45 -0300)]
Use nmutil simulator module to simplify choosing among engines

16 months agocs_n and cke in sdram need to match in length
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 21:59:19 +0000 (22:59 +0100)]
cs_n and cke in sdram need to match in length

16 months agochange litex sdram pinouts to ASIC type
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 21:44:56 +0000 (22:44 +0100)]
change litex sdram pinouts to ASIC type

16 months agoredo litex SDCard to send out data/cmd o/i/en pins
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 16:38:58 +0000 (17:38 +0100)]
redo litex SDCard to send out data/cmd o/i/en pins

16 months agosort out GPIO with i/o/oe in ls180
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 15:42:57 +0000 (16:42 +0100)]
sort out GPIO with i/o/oe in ls180

16 months agoadd ls180 pinmap text file
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 14:57:16 +0000 (15:57 +0100)]
add ls180 pinmap text file

16 months agoattempt GPIO bi-directional
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 11:25:37 +0000 (12:25 +0100)]
attempt GPIO bi-directional

16 months agoadd I2C master to ls180
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 10:43:53 +0000 (11:43 +0100)]
add I2C master to ls180

16 months agoadd 2 PWMs (quick, easy to do)
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 21:47:02 +0000 (22:47 +0100)]
add 2 PWMs (quick, easy to do)

16 months agomove dmi_sim to separate module
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 21:30:02 +0000 (22:30 +0100)]
move dmi_sim to separate module

16 months agoupdate submodule url
Jacob Lifshay [Tue, 22 Sep 2020 18:52:17 +0000 (11:52 -0700)]
update submodule url

16 months agoRevert "disable pia in div tests"
Jacob Lifshay [Tue, 22 Sep 2020 18:42:49 +0000 (11:42 -0700)]
Revert "disable pia in div tests"

Bug #497 resolved as invalid

This reverts commit 05b9baec72be4ef56de2ed56ec12cbf5f7f0eefe.

16 months agoadd openocd.cfg experiment
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 16:12:35 +0000 (17:12 +0100)]
add openocd.cfg experiment

16 months agocreate a JTAG platform and connect it up. jtagremote is actually running
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 14:42:57 +0000 (15:42 +0100)]
create a JTAG platform and connect it up.  jtagremote is actually running