soc.git
15 months agouse "enable" and set default actions in getopt
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 16:43:27 +0000 (17:43 +0100)]
use "enable" and set default actions in getopt

15 months agoadd extra variant to litex core
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 14:59:21 +0000 (15:59 +0100)]
add extra variant to litex core

15 months agosyntax error
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 14:58:09 +0000 (15:58 +0100)]
syntax error

15 months agodisable gpio in litex core
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 14:53:00 +0000 (15:53 +0100)]
disable gpio in litex core

15 months agoenable/disable litex irqs based on variant name
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 12:25:49 +0000 (13:25 +0100)]
enable/disable litex irqs based on variant name

15 months agoMakefile develop, when running setup.py develop specify --user so admin
Cole Poirier [Wed, 14 Oct 2020 00:37:32 +0000 (17:37 -0700)]
Makefile develop, when running setup.py develop specify --user so admin
access is not needed

15 months agoissuer_verilog.py update to use commandline args using argparse, fix
Cole Poirier [Wed, 14 Oct 2020 00:04:43 +0000 (17:04 -0700)]
issuer_verilog.py update to use commandline args using argparse, fix
formatting

15 months agomove pia from install_requires to test_requires
Cole Poirier [Tue, 13 Oct 2020 17:21:53 +0000 (10:21 -0700)]
move pia from install_requires to test_requires

15 months agolitex/florent/versa_ecp5.py add arg --fpga [versa_ecp5|ulx3s85f] default
Cole Poirier [Mon, 12 Oct 2020 23:30:10 +0000 (16:30 -0700)]
litex/florent/versa_ecp5.py add arg --fpga [versa_ecp5|ulx3s85f] default
of versa_ecp5, to build for different fpga targets, fix whitespace,
delete ulx3s85f.py as it's no longer needed

15 months agofix ModuleNotFound/Import errors found when running pytest, just due to
Cole Poirier [Mon, 12 Oct 2020 22:24:03 +0000 (15:24 -0700)]
fix ModuleNotFound/Import errors found when running pytest, just due to
things being renamed and not kept in sync

15 months agoupdate gitlab ci
Tobias Platen [Mon, 12 Oct 2020 20:00:40 +0000 (20:00 +0000)]
update gitlab ci

15 months agoadd tested working fpga compile/build/load file for ulxs3s LFE5U-85F as ulx3s85f...
Cole Poirier [Mon, 12 Oct 2020 19:36:20 +0000 (12:36 -0700)]
add tested working fpga compile/build/load file for ulxs3s LFE5U-85F as ulx3s85f.py based on versa_ecp5.py

15 months agoadd way to bypass PLL for ECP5 and sim
Luke Kenneth Casson Leighton [Sun, 11 Oct 2020 15:01:58 +0000 (16:01 +0100)]
add way to bypass PLL for ECP5 and sim

15 months agocomment out XICS/GPIO interrupt test, causes ECP5 litex build to fail
Luke Kenneth Casson Leighton [Sun, 11 Oct 2020 13:57:38 +0000 (14:57 +0100)]
comment out XICS/GPIO interrupt test, causes ECP5 litex build to fail
(input incorrectly detected as output)

15 months agorecord commands for building ECP5
Luke Kenneth Casson Leighton [Sun, 11 Oct 2020 13:50:11 +0000 (14:50 +0100)]
record commands for building ECP5

15 months agolitex sim.py operational
Luke Kenneth Casson Leighton [Sun, 11 Oct 2020 13:19:55 +0000 (14:19 +0100)]
litex sim.py operational

15 months agoflorent/versa_ecp5.py remove uneccessary imports, specify actual import
Cole Poirier [Sat, 10 Oct 2020 20:38:11 +0000 (13:38 -0700)]
florent/versa_ecp5.py remove uneccessary imports, specify actual import
instead of evil 'import *'

15 months agoadd debug start/stop to firmware_upload script
Luke Kenneth Casson Leighton [Sat, 10 Oct 2020 16:12:54 +0000 (17:12 +0100)]
add debug start/stop to firmware_upload script

15 months agoadd DMI status / reset to firmware upload script
Luke Kenneth Casson Leighton [Sat, 10 Oct 2020 14:45:59 +0000 (15:45 +0100)]
add DMI status / reset to firmware upload script

15 months agoadd first version of firmware uploader
Luke Kenneth Casson Leighton [Sat, 10 Oct 2020 14:13:38 +0000 (15:13 +0100)]
add first version of firmware uploader

15 months agoupdate submodule
Jacob Lifshay [Fri, 9 Oct 2020 23:33:39 +0000 (16:33 -0700)]
update submodule

15 months agoupdate submodule
Jacob Lifshay [Fri, 9 Oct 2020 22:57:01 +0000 (15:57 -0700)]
update submodule

15 months agouse libresoc version of c4m-jtag repo
Luke Kenneth Casson Leighton [Fri, 9 Oct 2020 13:16:20 +0000 (14:16 +0100)]
use libresoc version of c4m-jtag repo

15 months agosubmodule update
Luke Kenneth Casson Leighton [Fri, 9 Oct 2020 11:06:48 +0000 (12:06 +0100)]
submodule update

15 months agodrop in "undefined" function into ISAcaller namespace
Luke Kenneth Casson Leighton [Fri, 9 Oct 2020 10:51:18 +0000 (11:51 +0100)]
drop in "undefined" function into ISAcaller namespace

15 months agorename undef to undefined (preserving the fact that it is a function)
Luke Kenneth Casson Leighton [Fri, 9 Oct 2020 10:34:29 +0000 (11:34 +0100)]
rename undef to undefined (preserving the fact that it is a function)

15 months agomissing yields in JTAG pads test to allow settling
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 22:36:35 +0000 (23:36 +0100)]
missing yields in JTAG pads test to allow settling

15 months agofinish converting mul tests to use common code
Jacob Lifshay [Fri, 9 Oct 2020 04:19:07 +0000 (21:19 -0700)]
finish converting mul tests to use common code

15 months agoworking on splitting out common mul pipe test code
Jacob Lifshay [Fri, 9 Oct 2020 03:24:02 +0000 (20:24 -0700)]
working on splitting out common mul pipe test code

add initial tests for mul-add instructions

15 months agoadd carry handling to pia_res_to_output
Jacob Lifshay [Fri, 9 Oct 2020 03:23:17 +0000 (20:23 -0700)]
add carry handling to pia_res_to_output

15 months agomove pia_res_to_output to common test helpers
Jacob Lifshay [Fri, 9 Oct 2020 03:21:51 +0000 (20:21 -0700)]
move pia_res_to_output to common test helpers

15 months agomove mul pipe ilang test to separate file
Jacob Lifshay [Fri, 9 Oct 2020 00:45:32 +0000 (17:45 -0700)]
move mul pipe ilang test to separate file

15 months agoadd undef()
Jacob Lifshay [Fri, 9 Oct 2020 00:31:46 +0000 (17:31 -0700)]
add undef()

15 months agoupdate submodule
Jacob Lifshay [Fri, 9 Oct 2020 00:31:27 +0000 (17:31 -0700)]
update submodule

15 months agoupdate submodule
Jacob Lifshay [Thu, 8 Oct 2020 23:56:03 +0000 (16:56 -0700)]
update submodule

15 months agomissing yields in JTAG pads test to allow settling
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 22:34:23 +0000 (23:34 +0100)]
missing yields in JTAG pads test to allow settling

15 months agominor icache cleanup
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 22:27:02 +0000 (23:27 +0100)]
minor icache cleanup

15 months agosecond attempt at https://bugs.libre-soc.org/show_bug.cgi?id=485#c59,
Cole Poirier [Thu, 8 Oct 2020 20:31:51 +0000 (13:31 -0700)]
second attempt at https://bugs.libre-soc.org/show_bug.cgi?id=485#c59,
still not working properly, but it's closer

15 months agoremove singleton dict per https://bugs.libre-soc.org/show_bug.cgi?id=485#c58
Cole Poirier [Thu, 8 Oct 2020 19:28:02 +0000 (12:28 -0700)]
remove singleton dict per https://bugs.libre-soc.org/show_bug.cgi?id=485#c58

15 months agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Thu, 8 Oct 2020 18:16:40 +0000 (20:16 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

15 months agoadd WIP test_pipe_caller.py for mmu
Tobias Platen [Thu, 8 Oct 2020 17:39:06 +0000 (19:39 +0200)]
add WIP test_pipe_caller.py for mmu

15 months agoadd incoming PortInterface to be connected to LoadStoreCompUnit
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 17:13:50 +0000 (18:13 +0100)]
add incoming PortInterface to be connected to LoadStoreCompUnit

15 months agoJTAG boundary scan test 1st attempt
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 13:48:42 +0000 (14:48 +0100)]
JTAG boundary scan test 1st attempt

15 months agorework jtag test to use JTAG class not DMITAP
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 12:47:42 +0000 (13:47 +0100)]
rework jtag test to use JTAG class not DMITAP

15 months agosplit out jtag util functions to separate module
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 12:21:36 +0000 (13:21 +0100)]
split out jtag util functions to separate module

15 months agofirst attempt at 3) of
Cole Poirier [Thu, 8 Oct 2020 01:55:14 +0000 (18:55 -0700)]
first attempt at 3) of
https://bugs.libre-soc.org/show_bug.cgi?id=485#c41, not working yet

15 months agomodify wb_get per 1) of https://bugs.libre-soc.org/show_bug.cgi?id=485#c41
Cole Poirier [Thu, 8 Oct 2020 01:14:33 +0000 (18:14 -0700)]
modify wb_get per 1) of https://bugs.libre-soc.org/show_bug.cgi?id=485#c41

15 months agoconnect mmu_done, ldst_error, cache_paradox
Tobias Platen [Wed, 7 Oct 2020 19:52:44 +0000 (21:52 +0200)]
connect mmu_done, ldst_error, cache_paradox

15 months agomissing invert_in field from shiftrot input record
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 17:28:53 +0000 (18:28 +0100)]
missing invert_in field from shiftrot input record

15 months agogit submodule update
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 15:11:20 +0000 (16:11 +0100)]
git submodule update

15 months agoreorder / reorganise reset signals slightly
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 12:01:03 +0000 (13:01 +0100)]
reorder / reorganise reset signals slightly

15 months agofix div tests
Jacob Lifshay [Wed, 7 Oct 2020 04:01:15 +0000 (21:01 -0700)]
fix div tests

15 months agoupdate submodule
Jacob Lifshay [Wed, 7 Oct 2020 03:59:40 +0000 (20:59 -0700)]
update submodule

15 months agoFix forgotten test_pipe_caller changes from e0b4334c7d83dda41d5610239150079f30a2f713
Jacob Lifshay [Wed, 7 Oct 2020 01:36:06 +0000 (18:36 -0700)]
Fix forgotten test_pipe_caller changes from e0b4334c7d83dda41d5610239150079f30a2f713

15 months agoremove redunant signals
Tobias Platen [Tue, 6 Oct 2020 19:31:14 +0000 (21:31 +0200)]
remove redunant signals

15 months agoupdate comments on pimem.py
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 19:18:02 +0000 (20:18 +0100)]
update comments on pimem.py

15 months agotest_mmu_dcache_pi.py
Tobias Platen [Tue, 6 Oct 2020 18:51:34 +0000 (20:51 +0200)]
test_mmu_dcache_pi.py

15 months agocomments
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 17:18:09 +0000 (18:18 +0100)]
comments

15 months agoadd ports function to DummyPLL
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 17:09:48 +0000 (18:09 +0100)]
add ports function to DummyPLL

15 months agouse pdecode2.do not pdecode2.e in test_pipe_caller tests
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 17:08:16 +0000 (18:08 +0100)]
use pdecode2.do not pdecode2.e in test_pipe_caller tests

15 months agoskip Decode2ToOperand from PowerDecodeSubset
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 17:05:42 +0000 (18:05 +0100)]
skip Decode2ToOperand from PowerDecodeSubset

15 months agocomment SRR1 mem.exception
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 16:22:09 +0000 (17:22 +0100)]
comment SRR1 mem.exception

15 months agoadd SRR1 setting for LDST memory exception trap
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 15:58:14 +0000 (16:58 +0100)]
add SRR1 setting for LDST memory exception trap

15 months agopassing LDSTException over to Trap Pipeline
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 15:33:45 +0000 (16:33 +0100)]
passing LDSTException over to Trap Pipeline

15 months agoadd LDSTException decode/handling in PowerDecoder2
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 15:07:32 +0000 (16:07 +0100)]
add LDSTException decode/handling in PowerDecoder2

15 months agomake LDSTException fields added from list of fieldnames
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 15:05:36 +0000 (16:05 +0100)]
make LDSTException fields added from list of fieldnames

15 months agomove LDSTException to mem_types
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 14:48:17 +0000 (15:48 +0100)]
move LDSTException to mem_types

15 months agosubmodule update
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 13:06:36 +0000 (14:06 +0100)]
submodule update

15 months agoadd LDSTException to PortInterface
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 13:03:53 +0000 (14:03 +0100)]
add LDSTException to PortInterface

15 months agoadd sdr bypass routing via JTAG boundary scan
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 12:37:06 +0000 (13:37 +0100)]
add sdr bypass routing via JTAG boundary scan

15 months agoadd divde regression test
Jacob Lifshay [Tue, 6 Oct 2020 02:52:40 +0000 (19:52 -0700)]
add divde regression test

15 months agoupdate submodule
Jacob Lifshay [Tue, 6 Oct 2020 02:52:26 +0000 (19:52 -0700)]
update submodule

15 months agoadd moduw regression test
Jacob Lifshay [Tue, 6 Oct 2020 02:17:24 +0000 (19:17 -0700)]
add moduw regression test

15 months agoupdate submodule
Jacob Lifshay [Tue, 6 Oct 2020 02:16:24 +0000 (19:16 -0700)]
update submodule

15 months agoadd workaround for nmigen bug #502
Jacob Lifshay [Tue, 6 Oct 2020 01:59:39 +0000 (18:59 -0700)]
add workaround for nmigen bug #502

This fixes modsw

15 months agoupdate submodule
Jacob Lifshay [Tue, 6 Oct 2020 01:58:21 +0000 (18:58 -0700)]
update submodule

15 months agoadd modsw regression
Jacob Lifshay [Tue, 6 Oct 2020 01:07:56 +0000 (18:07 -0700)]
add modsw regression

15 months agoadd test case for divweu regression
Jacob Lifshay [Tue, 6 Oct 2020 01:06:51 +0000 (18:06 -0700)]
add test case for divweu regression

15 months agoupdate submodule
Jacob Lifshay [Tue, 6 Oct 2020 01:03:35 +0000 (18:03 -0700)]
update submodule

15 months agoprint regs in hex
Jacob Lifshay [Tue, 6 Oct 2020 00:16:29 +0000 (17:16 -0700)]
print regs in hex

15 months agoadd debug / investigation print statements
Luke Kenneth Casson Leighton [Mon, 5 Oct 2020 23:16:46 +0000 (00:16 +0100)]
add debug / investigation print statements

15 months ago`deepcopy` from cache instead of recreating parsers for `GardenSnakeCompiler`
Jacob Lifshay [Mon, 5 Oct 2020 22:21:33 +0000 (15:21 -0700)]
`deepcopy` from cache instead of recreating parsers for `GardenSnakeCompiler`

changes `make develop` time from about 1m30s to 1m09s for me

15 months agoformat code
Jacob Lifshay [Mon, 5 Oct 2020 22:20:40 +0000 (15:20 -0700)]
format code

15 months agoicache.py fix ispow2() util fn per https://bugs.libre-soc.org/show_bug.cgi?id=485#c53
Cole Poirier [Mon, 5 Oct 2020 16:44:36 +0000 (09:44 -0700)]
icache.py fix ispow2() util fn per https://bugs.libre-soc.org/show_bug.cgi?id=485#c53

15 months agowhoops fix syntax error
Luke Kenneth Casson Leighton [Mon, 5 Oct 2020 11:51:25 +0000 (12:51 +0100)]
whoops fix syntax error

15 months agowhoops fix syntax error
Luke Kenneth Casson Leighton [Mon, 5 Oct 2020 11:30:26 +0000 (12:30 +0100)]
whoops fix syntax error

15 months agoreturn test rather than "if test return True else False"
Luke Kenneth Casson Leighton [Mon, 5 Oct 2020 10:51:17 +0000 (11:51 +0100)]
return test rather than "if test return True else False"

15 months agowhitespace
Luke Kenneth Casson Leighton [Mon, 5 Oct 2020 10:49:40 +0000 (11:49 +0100)]
whitespace

15 months agowhitespace
Luke Kenneth Casson Leighton [Mon, 5 Oct 2020 10:44:03 +0000 (11:44 +0100)]
whitespace

15 months agoicache.py add python asserts that were a TODO commented section from
Cole Poirier [Mon, 5 Oct 2020 01:46:11 +0000 (18:46 -0700)]
icache.py add python asserts that were a TODO commented section from
icache.vhdl, print all constant values at start of icache_sim() in alphabetic order, make constant naming consistent

15 months agoicache.py fix formatting, mostly due to reduced indentation in preceding
Cole Poirier [Mon, 5 Oct 2020 00:30:09 +0000 (17:30 -0700)]
icache.py fix formatting, mostly due to reduced indentation in preceding
commits, remove uneccessary Display() statements

15 months agoicache.py remove comment that contained the entirety of microwatt's
Cole Poirier [Mon, 5 Oct 2020 00:14:14 +0000 (17:14 -0700)]
icache.py remove comment that contained the entirety of microwatt's
icache_tb.vhdl as it is no longer needed

15 months agoicache.py move icache_miss WAIT_ACK FSM state into method icache_miss_wait_ack()...
Cole Poirier [Mon, 5 Oct 2020 00:12:35 +0000 (17:12 -0700)]
icache.py move icache_miss WAIT_ACK FSM state into method icache_miss_wait_ack() to reduce clutter, indentation

15 months agoicache.py move icache_miss CLR_TAG FSM state into method icache_miss_clr_tag() to...
Cole Poirier [Mon, 5 Oct 2020 00:01:34 +0000 (17:01 -0700)]
icache.py move icache_miss CLR_TAG FSM state into method icache_miss_clr_tag() to reduce clutter, indentation

15 months agoicache.py move icache_miss IDLE FSM state into method icache_miss_idle()
Cole Poirier [Mon, 5 Oct 2020 00:00:04 +0000 (17:00 -0700)]
icache.py move icache_miss IDLE FSM state into method icache_miss_idle()
to reduce clutter, indentation

15 months agosimplify create_args
Jacob Lifshay [Mon, 5 Oct 2020 00:47:54 +0000 (17:47 -0700)]
simplify create_args

15 months agoSort returned variables to make sure `overflow` is last
Jacob Lifshay [Mon, 5 Oct 2020 00:32:45 +0000 (17:32 -0700)]
Sort returned variables to make sure `overflow` is last

Fixes #509

15 months agoformat caller.py
Jacob Lifshay [Mon, 5 Oct 2020 00:28:26 +0000 (17:28 -0700)]
format caller.py

15 months agochange div FSM pipeline unit to not have a combinatorial path directly from inputs...
Jacob Lifshay [Sun, 4 Oct 2020 22:17:41 +0000 (15:17 -0700)]
change div FSM pipeline unit to not have a combinatorial path directly from inputs to outputs

Fixes #510

15 months agosignificant reorg of the litex pinspecs to use pinmux JSON files
Luke Kenneth Casson Leighton [Sun, 4 Oct 2020 18:11:32 +0000 (19:11 +0100)]
significant reorg of the litex pinspecs to use pinmux JSON files