soc.git
14 months agohilarious. only just caught a bug where overflow was being taken from Rc
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 20:41:15 +0000 (21:41 +0100)]
hilarious.  only just caught a bug where overflow was being taken from Rc

14 months agocomb += missing
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 15:57:18 +0000 (16:57 +0100)]
comb += missing

14 months agoadd CR0 regression, expected 0b10 actual 0b11
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 15:32:22 +0000 (16:32 +0100)]
add CR0 regression, expected 0b10 actual 0b11

14 months agoadd regression test 8, DivPipeCore producing spurious result
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 15:18:16 +0000 (16:18 +0100)]
add regression test 8, DivPipeCore producing spurious result

14 months agoadd pia back in
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 15:15:44 +0000 (16:15 +0100)]
add pia back in

14 months agore-add pia_result_to_output function (minus "typing" which should go in .pyi)
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 15:04:02 +0000 (16:04 +0100)]
re-add pia_result_to_output function (minus "typing" which should go in .pyi)

14 months agoadd div compunit test
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 14:34:16 +0000 (15:34 +0100)]
add div compunit test

14 months agowait until pipeline indicates that its output is valid in compunit test
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 14:33:38 +0000 (15:33 +0100)]
wait until pipeline indicates that its output is valid in compunit test
DIV and other long pipelines only set wrmask when a result is available
the previous test, "is wrmask zero if so exit" was therefore reading
invalid data.

it was a matter of coincidence that all other compunit tests were only
one stage long that the wrmask *happened* to be valid

14 months agomove reset of rdmaskn to after "busy"
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 14:20:36 +0000 (15:20 +0100)]
move reset of rdmaskn to after "busy"

14 months agocomment LDST FunctionUnit
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 14:10:34 +0000 (15:10 +0100)]
comment LDST FunctionUnit

14 months agogoing on a bit of a "naming" spree, this for Jean-Paul to be able to
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 11:54:49 +0000 (12:54 +0100)]
going on a bit of a "naming" spree, this for Jean-Paul to be able to
identify operand records on pipelines

14 months agoadd spec page numbers to logical ops
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 11:25:41 +0000 (12:25 +0100)]
add spec page numbers to logical ops

14 months agoadd page-number comments to ALU main_stage
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 11:19:31 +0000 (12:19 +0100)]
add page-number comments to ALU main_stage

14 months agoupdate comment-headers (TODO include page numbers to v3.0B spec)
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 11:14:31 +0000 (12:14 +0100)]
update comment-headers (TODO include page numbers to v3.0B spec)

14 months agomake trap proof section more readable
Luke Kenneth Casson Leighton [Sat, 25 Jul 2020 11:09:30 +0000 (12:09 +0100)]
make trap proof section more readable

14 months agoProperties for MFMSR
Samuel A. Falvo II [Fri, 24 Jul 2020 23:31:09 +0000 (16:31 -0700)]
Properties for MFMSR

14 months agoReorganize code layout
Samuel A. Falvo II [Fri, 24 Jul 2020 23:19:17 +0000 (16:19 -0700)]
Reorganize code layout

Make proof code match corresponding code in main_stage.  I am constantly
getting confused about what to work on next.  Purely a cosmetic change,
but has impact on cognitive load for me.

14 months agoWIP: SC properties more closely match doc'd behavior
Samuel A. Falvo II [Fri, 24 Jul 2020 22:28:04 +0000 (15:28 -0700)]
WIP: SC properties more closely match doc'd behavior

14 months agoUpdate libreriscv/HDL_workflow with instructions how to build and
Cole Poirier [Fri, 24 Jul 2020 20:42:56 +0000 (13:42 -0700)]
Update libreriscv/HDL_workflow with instructions how to build and
install power_instruction_analyzer (pia)

14 months agoWIP: addressing code review, restoring proofs, etc.
Samuel A. Falvo II [Fri, 24 Jul 2020 15:21:29 +0000 (08:21 -0700)]
WIP: addressing code review, restoring proofs, etc.

14 months agogot fed up with bit-slice ordering crap. cut it out
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 15:12:32 +0000 (16:12 +0100)]
got fed up with bit-slice ordering crap.  cut it out

14 months agoadd better comments on field_slice
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 15:10:54 +0000 (16:10 +0100)]
add better comments on field_slice

14 months agoreturned field_slice to original, and added comments
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 15:03:31 +0000 (16:03 +0100)]
returned field_slice to original, and added comments
see https://bugs.libre-soc.org/show_bug.cgi?id=325#c134

14 months agoannoying, yet more typos
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:51:38 +0000 (14:51 +0100)]
annoying, yet more typos

14 months agoannoying, typo
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:50:23 +0000 (14:50 +0100)]
annoying, typo

14 months agobetter debug assert log message
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:43:54 +0000 (14:43 +0100)]
better debug assert log message

14 months agotoo much debug info going past, so add the test registers to the
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:42:04 +0000 (14:42 +0100)]
too much debug info going past, so add the test registers to the
failed log message

14 months agomissed import
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:34:06 +0000 (14:34 +0100)]
missed import

14 months agocalling the test dictionary from the constructor is effectively
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:33:08 +0000 (14:33 +0100)]
calling the test dictionary from the constructor is effectively
what unittest does.  this results in multiple copies of the test
being called (once by the dictionary-loop, once by unittest infrastructure)

getting the name of the actual test is a good thing.  used inspect.stack()
to find the name of the calling test

14 months agowhoops spelling
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:29:13 +0000 (14:29 +0100)]
whoops spelling

14 months agoadd the div pipe kind plus prog.assembly to the assert debug output
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:06:48 +0000 (14:06 +0100)]
add the div pipe kind plus prog.assembly to the assert debug output

14 months agocall test_write_ilang only once - ends up being called 9 times otherwise
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 13:05:53 +0000 (14:05 +0100)]
call test_write_ilang only once - ends up being called 9 times otherwise

14 months agofix how long div tests run, de-comment FSM and DivPipeCore
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 12:59:29 +0000 (13:59 +0100)]
fix how long div tests run, de-comment FSM and DivPipeCore

14 months agoargh! work-in-progress breaking / fixing how to do div unit tests
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 12:56:25 +0000 (13:56 +0100)]
argh!  work-in-progress breaking / fixing how to do div unit tests

14 months agowhoops must add DivTestCasesLong to get it to produce test_data
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 12:23:17 +0000 (13:23 +0100)]
whoops must add DivTestCasesLong to get it to produce test_data

14 months agoremove bad hack calling trunc_divs/trunc_mods
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 12:19:17 +0000 (13:19 +0100)]
remove bad hack calling trunc_divs/trunc_mods
see https://bugs.libre-soc.org/show_bug.cgi?id=436

14 months agore-enable commented-out div unit tests
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 11:52:28 +0000 (12:52 +0100)]
re-enable commented-out div unit tests

14 months agosplit out "all" div into separate unit test (takes a really long time)
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 11:50:07 +0000 (12:50 +0100)]
split out "all" div into separate unit test (takes a really long time)

14 months agoreduce variable size, continuation not needed
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 11:45:27 +0000 (12:45 +0100)]
reduce variable size, continuation not needed

14 months agocomment about timeline does not exist
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 11:43:59 +0000 (12:43 +0100)]
comment about timeline does not exist

14 months agoah ha! not using "with" was not calling the "close" function
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 11:06:08 +0000 (12:06 +0100)]
ah ha!  not using "with" was not calling the "close" function

14 months agoread into a BytesIO to avoid "too many open files"
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 10:54:24 +0000 (11:54 +0100)]
read into a BytesIO to avoid "too many open files"
 see https://bugs.libre-soc.org/show_bug.cgi?id=438

14 months agowhitespace / comments
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 10:46:19 +0000 (11:46 +0100)]
whitespace / comments

14 months agorestore modification to caller.py from reversion of div (use of pia
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 10:35:00 +0000 (11:35 +0100)]
restore modification to caller.py from reversion of div (use of pia
not properly documented)

14 months agoRevert "working on div's test_pipe_caller"
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 10:30:32 +0000 (11:30 +0100)]
Revert "working on div's test_pipe_caller"

This reverts commit 8bf37997d31250126a664aeb3bd67ac0cd72a70c.

the build / install dependencies have not been properly documented,
making it impossible for anyone to install this at the moment.

that in turn makes it impossible for anyone to run:

* the div test_pipe_caller unit test
* the test_issuer.py test
* the test_core.py test
* the compunit test_div_compunit.py test

the modifications to caller.py whilst correct are reverted as a
side-effect due to violation of the development guidelines on
"single purpose commit"

14 months agobug found in pseudocode reader when assembly code has zero args
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 10:14:16 +0000 (11:14 +0100)]
bug found in pseudocode reader when assembly code has zero args

14 months agosubmodule update
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 10:09:14 +0000 (11:09 +0100)]
submodule update
see https://bugs.libre-soc.org/show_bug.cgi?id=439

14 months agocode review comments for trap and proof
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 09:40:32 +0000 (10:40 +0100)]
code review comments for trap and proof

14 months agomade it clear what is meant by the slice numbering being inverted
Luke Kenneth Casson Leighton [Fri, 24 Jul 2020 09:25:59 +0000 (10:25 +0100)]
made it clear what is meant by the slice numbering being inverted
see https://bugs.libre-soc.org/show_bug.cgi?id=325#c126

14 months agoRefactorin of common code
Samuel A. Falvo II [Fri, 24 Jul 2020 05:37:28 +0000 (22:37 -0700)]
Refactorin of common code

14 months agoAddress code review comments
Samuel A. Falvo II [Fri, 24 Jul 2020 05:29:55 +0000 (22:29 -0700)]
Address code review comments

- Remove hypervisor-related checks and main logic.
- Use field() to work with subfields of arbitrary signals.
- Use FormXXX classes to access opcode subfields.

14 months agoworking on div's test_pipe_caller
Jacob Lifshay [Fri, 24 Jul 2020 04:59:09 +0000 (21:59 -0700)]
working on div's test_pipe_caller

14 months agoadd power-instruction-analyzer as a dependency
Jacob Lifshay [Fri, 24 Jul 2020 02:36:02 +0000 (19:36 -0700)]
add power-instruction-analyzer as a dependency

14 months agoformat
Jacob Lifshay [Fri, 24 Jul 2020 02:35:49 +0000 (19:35 -0700)]
format

14 months agosyntax error
Luke Kenneth Casson Leighton [Thu, 23 Jul 2020 21:49:32 +0000 (22:49 +0100)]
syntax error

14 months agosupport 32-bit mem width setting
Luke Kenneth Casson Leighton [Thu, 23 Jul 2020 21:42:59 +0000 (22:42 +0100)]
support 32-bit mem width setting

14 months agotry SDRAM SDR
Luke Kenneth Casson Leighton [Thu, 23 Jul 2020 21:42:29 +0000 (22:42 +0100)]
try SDRAM SDR

14 months agoallow imem to be 64/32 bit wide
Luke Kenneth Casson Leighton [Thu, 23 Jul 2020 21:41:19 +0000 (22:41 +0100)]
allow imem to be 64/32 bit wide

14 months agobegin core in running state
Luke Kenneth Casson Leighton [Thu, 23 Jul 2020 19:28:51 +0000 (20:28 +0100)]
begin core in running state

14 months agotry different MEMTEST_xxx sizes with 64 bit bus width
Luke Kenneth Casson Leighton [Thu, 23 Jul 2020 19:28:37 +0000 (20:28 +0100)]
try different MEMTEST_xxx sizes with 64 bit bus width

14 months agoUpdate libreriscv HDL_workflow/coriolis2
Cole Poirier [Thu, 23 Jul 2020 19:43:24 +0000 (12:43 -0700)]
Update libreriscv HDL_workflow/coriolis2

14 months agoadd all div* and mod* instructions to test_pipe_caller
Jacob Lifshay [Thu, 23 Jul 2020 00:42:37 +0000 (17:42 -0700)]
add all div* and mod* instructions to test_pipe_caller

14 months agoworking on fsm
Jacob Lifshay [Wed, 22 Jul 2020 23:55:51 +0000 (16:55 -0700)]
working on fsm

14 months agoMerge remote-tracking branch 'origin/master'
Jacob Lifshay [Wed, 22 Jul 2020 22:19:40 +0000 (15:19 -0700)]
Merge remote-tracking branch 'origin/master'

14 months agoformat code
Jacob Lifshay [Wed, 22 Jul 2020 22:18:03 +0000 (15:18 -0700)]
format code

14 months agore-add CRG (clock reset generator)
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 21:11:57 +0000 (22:11 +0100)]
re-add CRG (clock reset generator)

14 months agomissing ports from issuer, when doing verilog
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 20:27:42 +0000 (21:27 +0100)]
missing ports from issuer, when doing verilog

14 months agoadd clock domain using snippet taken from random file
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 20:20:30 +0000 (21:20 +0100)]
add clock domain using snippet taken from random file

14 months agocleanup in litex core.py
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 20:11:32 +0000 (21:11 +0100)]
cleanup in litex core.py

14 months agoupdate comments
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 19:56:55 +0000 (20:56 +0100)]
update comments

14 months agoadd dummy irq set/get
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 19:49:59 +0000 (20:49 +0100)]
add dummy irq set/get

14 months agoadd boot-helper.S etc from microwatt litex core
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 19:45:19 +0000 (20:45 +0100)]
add boot-helper.S etc from microwatt litex core

14 months agoset additional MSR bits according to v3.0B spec when trap occurs
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 19:18:30 +0000 (20:18 +0100)]
set additional MSR bits according to v3.0B spec when trap occurs

14 months agouse (new) MSRb and PIb which has auto-bigendian numbers
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 19:11:40 +0000 (20:11 +0100)]
use (new) MSRb and PIb which has auto-bigendian numbers

14 months agosigh, auto-create some little/big-endian classes for accessing MSR/PI fields
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 19:08:29 +0000 (20:08 +0100)]
sigh, auto-create some little/big-endian classes for accessing MSR/PI fields

14 months agomissed import of Builder, set cpu_type to "None" temporarily
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 18:31:32 +0000 (19:31 +0100)]
missed import of Builder, set cpu_type to "None" temporarily

14 months agobegin converting litex sim to libre-soc
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 18:09:00 +0000 (19:09 +0100)]
begin converting litex sim to libre-soc

14 months agowhoops forgot field accessor
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 18:08:40 +0000 (19:08 +0100)]
whoops forgot field accessor

14 months agodo not use wildcard import
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 15:36:01 +0000 (16:36 +0100)]
do not use wildcard import

14 months agostart from vexriscv sim.py from
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 15:33:55 +0000 (16:33 +0100)]
start from vexriscv sim.py from
https://github.com/enjoy-digital/litex_vexriscv_smp

14 months agocorrect syntax error
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 15:32:47 +0000 (16:32 +0100)]
correct syntax error

14 months agofirst version of litex core (to be submitted upstream once tested)
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 15:30:35 +0000 (16:30 +0100)]
first version of litex core (to be submitted upstream once tested)

14 months agowhoops typo, 63-start not 3-start (doh)
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 14:53:00 +0000 (15:53 +0100)]
whoops typo, 63-start not 3-start (doh)

14 months agofield number ordering wrong way round?
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 14:48:18 +0000 (15:48 +0100)]
field number ordering wrong way round?
see https://bugs.libre-soc.org/show_bug.cgi?id=325#c107

14 months agosyntax error
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 14:42:23 +0000 (15:42 +0100)]
syntax error

14 months agoreview trap main_stage.py modifications: we are not doing hypervisor
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 13:57:13 +0000 (14:57 +0100)]
review trap main_stage.py modifications: we are not doing hypervisor
see https://bugs.libre-soc.org/show_bug.cgi?id=325#c104

14 months agocomments, add page spec numbers for branch ops into proof
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 12:53:43 +0000 (13:53 +0100)]
comments, add page spec numbers for branch ops into proof

14 months agoadd comment headings with spec page numbers
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 12:50:31 +0000 (13:50 +0100)]
add comment headings with spec page numbers

14 months agocomment on op.insn ordering
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 12:45:58 +0000 (13:45 +0100)]
comment on op.insn ordering

14 months agocode-shuffle, add comments
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 12:42:53 +0000 (13:42 +0100)]
code-shuffle, add comments

14 months agoadd TT.size and use it in PowerDecoder and trap input record
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 11:59:13 +0000 (12:59 +0100)]
add TT.size and use it in PowerDecoder and trap input record

14 months agoinline comments in trap proof
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 11:57:24 +0000 (12:57 +0100)]
inline comments in trap proof

14 months agonote that traptype MUST increase in bitwidth corresponding to additions
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 11:54:56 +0000 (12:54 +0100)]
note that traptype MUST increase in bitwidth corresponding to additions
to TT

14 months agofix branch main_stage proof, add ctr 32-bit, fix BCREG
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 10:41:44 +0000 (11:41 +0100)]
fix branch main_stage proof, add ctr 32-bit, fix BCREG

14 months agorework branch proof to use br_input_record
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 10:14:32 +0000 (11:14 +0100)]
rework branch proof to use br_input_record

14 months agoupdate README for pipe_data.py
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 09:50:47 +0000 (10:50 +0100)]
update README for pipe_data.py

14 months agoreduce number of FastRegs read ports
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 09:29:58 +0000 (10:29 +0100)]
reduce number of FastRegs read ports

14 months agocomments on what goes into CommonPipeSpec
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 09:29:36 +0000 (10:29 +0100)]
comments on what goes into CommonPipeSpec

14 months agoComplete FV properties for OP_TRAP instructions.
Samuel A. Falvo II [Wed, 22 Jul 2020 06:03:34 +0000 (23:03 -0700)]
Complete FV properties for OP_TRAP instructions.

14 months agoPEP8 compliance
Samuel A. Falvo II [Wed, 22 Jul 2020 03:08:32 +0000 (20:08 -0700)]
PEP8 compliance