soc.git
16 months agorename regspecs to give a consistent naming scheme
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 13:54:51 +0000 (14:54 +0100)]
rename regspecs to give a consistent naming scheme
the Decode phase needs to be able to associate regspec information with
actual signals, back in Decode2Execute1Type.  the simplest way to do this
is to make the regspec register names consistent and actually refer
*to* Decode2Execute1Type signals

16 months agoadd MSR constants, TODO translated
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 11:19:32 +0000 (12:19 +0100)]
add MSR constants, TODO translated

16 months agoadd TODO comments from microwatt source code
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 11:06:42 +0000 (12:06 +0100)]
add TODO comments from microwatt source code

16 months agoAllow at least one operand to be fetched
Cesar Strauss [Tue, 2 Jun 2020 09:37:57 +0000 (06:37 -0300)]
Allow at least one operand to be fetched

We successfully disabled all rel signals. One was immediate, the other was
masked. Let's enable at least one of them, for now.
When the test code is complete, we will be able to issue several
transactions in sequence, with different combinations. We are not there
yet.

16 months agoHold rdmaskn active during the busy_o cycle
Cesar Strauss [Tue, 2 Jun 2020 09:21:50 +0000 (06:21 -0300)]
Hold rdmaskn active during the busy_o cycle

16 months agoremove reading port 3 for CR pipeline. RS moved to port 1
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 22:06:00 +0000 (23:06 +0100)]
remove reading port 3 for CR pipeline.  RS moved to port 1

16 months agookaaay add a "rdflags" function which obtains the yes/no flags for each register...
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 21:39:06 +0000 (22:39 +0100)]
okaaay add a "rdflags" function which obtains the yes/no flags for each register to the CompUnit
this to be used by the Decode phase

16 months agoadd test_bc_reg (fails)
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 20:38:43 +0000 (21:38 +0100)]
add test_bc_reg (fails)

16 months agoremove unneeded fields from Decode2Execute1Type
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 20:25:12 +0000 (21:25 +0100)]
remove unneeded fields from Decode2Execute1Type

16 months agoAdd proof for RegFile
Michael Nolan [Mon, 1 Jun 2020 19:51:43 +0000 (15:51 -0400)]
Add proof for RegFile

16 months agomore unneeded fields from SR InputRecord
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 19:16:25 +0000 (20:16 +0100)]
more unneeded fields from SR InputRecord

16 months agoremove data_len from SR input record
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 19:15:06 +0000 (20:15 +0100)]
remove data_len from SR input record

16 months agoremove zero/invert from ShiftRot Input Record
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 19:14:06 +0000 (20:14 +0100)]
remove zero/invert from ShiftRot Input Record

16 months agoadd shift-rot input record and use it
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 19:08:21 +0000 (20:08 +0100)]
add shift-rot input record and use it

16 months agoCompBROpSubset exists
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 19:03:03 +0000 (20:03 +0100)]
CompBROpSubset exists

16 months agoRS moved to port 1 (from port 3), remove need in ALU to read/mux into A operand
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 18:51:54 +0000 (19:51 +0100)]
RS moved to port 1 (from port 3), remove need in ALU to read/mux into A operand

16 months agoAdd proof for RegFileArray
Michael Nolan [Mon, 1 Jun 2020 18:50:52 +0000 (14:50 -0400)]
Add proof for RegFileArray

16 months agoremove use of reg3 in logical pipeline: CSV files moved RS to position 1
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 18:45:01 +0000 (19:45 +0100)]
remove use of reg3 in logical pipeline: CSV files moved RS to position 1

16 months agoHave regfile use AnySeq instead of AnyConst
Michael Nolan [Mon, 1 Jun 2020 18:40:41 +0000 (14:40 -0400)]
Have regfile use AnySeq instead of AnyConst

16 months agorotator carry is set into both XER CA and CA32 fields
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 18:13:08 +0000 (19:13 +0100)]
rotator carry is set into both XER CA and CA32 fields

16 months agocomment out rlwinm. for now
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 18:05:38 +0000 (19:05 +0100)]
comment out rlwinm. for now

16 months agoargh - need to zero the src_i input after "Read" is actioned
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 17:57:35 +0000 (18:57 +0100)]
argh - need to zero the src_i input after "Read" is actioned

16 months agoEnable k-induction for register file proof
Michael Nolan [Mon, 1 Jun 2020 17:48:13 +0000 (13:48 -0400)]
Enable k-induction for register file proof

16 months agoThat was weird. For some reason it wasn't generating any ports
Michael Nolan [Mon, 1 Jun 2020 17:46:17 +0000 (13:46 -0400)]
That was weird. For some reason it wasn't generating any ports

16 months agoFull BMC proof of Register
Michael Nolan [Mon, 1 Jun 2020 17:34:44 +0000 (13:34 -0400)]
Full BMC proof of Register

16 months agoBegin rewrite of proof_regfile.py
Michael Nolan [Mon, 1 Jun 2020 17:18:14 +0000 (13:18 -0400)]
Begin rewrite of proof_regfile.py

16 months agoput RB in 2nd position (matching immediate) in ShiftRot Input Data
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 17:39:50 +0000 (18:39 +0100)]
put RB in 2nd position (matching immediate) in ShiftRot Input Data

16 months agosigh - another instance where write-mask needed to mask out wr.rel
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 16:53:31 +0000 (17:53 +0100)]
sigh - another instance where write-mask needed to mask out wr.rel

16 months agoremove xer so/ov, swap rs/rb to correct(?) order in shiftrot test
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 16:01:05 +0000 (17:01 +0100)]
remove xer so/ov, swap rs/rb to correct(?) order in shiftrot test

16 months agoproof_datamerger wip
Tobias Platen [Mon, 1 Jun 2020 15:56:21 +0000 (17:56 +0200)]
proof_datamerger wip

16 months agoadd rlwinm. test instruction (sets CR0)
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 15:38:10 +0000 (16:38 +0100)]
add rlwinm. test instruction (sets CR0)

16 months agoremove duplicate signal
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 15:17:48 +0000 (16:17 +0100)]
remove duplicate signal

16 months agoallow ALU / Logical ops to select RS as 1st operand
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 12:36:14 +0000 (13:36 +0100)]
allow ALU / Logical ops to select RS as 1st operand

16 months agoallow M*-Form shiftrot to swap RS/RB back to consistent positions
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 12:27:00 +0000 (13:27 +0100)]
allow M*-Form shiftrot to swap RS/RB back to consistent positions

16 months agoadd first version of ShiftRot CompUnit test
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 11:38:45 +0000 (12:38 +0100)]
add first version of ShiftRot CompUnit test

16 months agoshiftrot uses LogicalOutputData not ALUOutputData
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 11:38:25 +0000 (12:38 +0100)]
shiftrot uses LogicalOutputData not ALUOutputData

16 months agoAdd rdmaskn parameter and assert it along issue_i
Cesar Strauss [Mon, 1 Jun 2020 10:56:12 +0000 (07:56 -0300)]
Add rdmaskn parameter and assert it along issue_i

Like zero_a and imm_ok, rdmaskn disallows the activation of go.

16 months agoadd assertions for branch compunit output
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 10:31:45 +0000 (11:31 +0100)]
add assertions for branch compunit output

16 months agoinvert SPR1/2 in branch output data
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 10:29:00 +0000 (11:29 +0100)]
invert SPR1/2 in branch output data

16 months agodecode SPRs for branch
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 04:50:28 +0000 (05:50 +0100)]
decode SPRs for branch

16 months agoswap over SPR1/2 to fit with microwatt SPR conventions
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 04:39:25 +0000 (05:39 +0100)]
swap over SPR1/2 to fit with microwatt SPR conventions

16 months agoadd first version compunit branch test
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 04:38:44 +0000 (05:38 +0100)]
add first version compunit branch test

16 months agowhoops need to read RS in CR inputs test
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 04:20:08 +0000 (05:20 +0100)]
whoops need to read RS in CR inputs test

16 months agoadd first version of CR CompUnit test
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 03:46:26 +0000 (04:46 +0100)]
add first version of CR CompUnit test

16 months agominor adjustment, zero test in ALU output stage
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 02:25:39 +0000 (03:25 +0100)]
minor adjustment, zero test in ALU output stage

16 months agoremove unneeded code
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 00:52:50 +0000 (01:52 +0100)]
remove unneeded code

16 months agobit-test on the function-unit value being tested
Luke Kenneth Casson Leighton [Sun, 31 May 2020 23:20:20 +0000 (00:20 +0100)]
bit-test on the function-unit value being tested
this because Function Unit is a bitfield

16 months agoupdate isatables to cmpb not modifying CR0
Luke Kenneth Casson Leighton [Sun, 31 May 2020 23:14:11 +0000 (00:14 +0100)]
update isatables to cmpb not modifying CR0

16 months agoadd logical compunit test
Luke Kenneth Casson Leighton [Sun, 31 May 2020 23:07:42 +0000 (00:07 +0100)]
add logical compunit test

16 months agocomment inputs and outputs from ALU unit test
Luke Kenneth Casson Leighton [Sun, 31 May 2020 18:50:34 +0000 (19:50 +0100)]
comment inputs and outputs from ALU unit test

16 months agoimports - use of globals. baaaad
Luke Kenneth Casson Leighton [Sun, 31 May 2020 18:46:44 +0000 (19:46 +0100)]
imports - use of globals. baaaad

16 months agoremove unneeded code and inputs. convert to "naming" in CompUnit inputs
Luke Kenneth Casson Leighton [Sun, 31 May 2020 18:45:12 +0000 (19:45 +0100)]
remove unneeded code and inputs. convert to "naming" in CompUnit inputs

16 months agosplit out common code from test_alu_compunit.py
Luke Kenneth Casson Leighton [Sun, 31 May 2020 18:27:56 +0000 (19:27 +0100)]
split out common code from test_alu_compunit.py

16 months agoadd comments for MultiCompUnit parallel test
Luke Kenneth Casson Leighton [Sun, 31 May 2020 17:03:31 +0000 (18:03 +0100)]
add comments for MultiCompUnit parallel test

16 months agode-hard-code-ify getting results from MultiCompUnit
Luke Kenneth Casson Leighton [Sun, 31 May 2020 16:57:46 +0000 (17:57 +0100)]
de-hard-code-ify getting results from MultiCompUnit

16 months agoremove unneeded imports
Luke Kenneth Casson Leighton [Sun, 31 May 2020 16:44:03 +0000 (17:44 +0100)]
remove unneeded imports

16 months agosplit out compalu unit tests to separate module (getting quite big)
Luke Kenneth Casson Leighton [Sun, 31 May 2020 16:41:28 +0000 (17:41 +0100)]
split out compalu unit tests to separate module (getting quite big)

16 months agoHA! found a bug in MultiCompUnit handling of write-masks
Luke Kenneth Casson Leighton [Sun, 31 May 2020 14:58:04 +0000 (15:58 +0100)]
HA! found a bug in MultiCompUnit handling of write-masks

16 months agoclarify
Luke Kenneth Casson Leighton [Sun, 31 May 2020 13:35:17 +0000 (14:35 +0100)]
clarify

16 months agoOP_CMPEQB also requesting change of output reg (stop that)
Luke Kenneth Casson Leighton [Sun, 31 May 2020 13:34:09 +0000 (14:34 +0100)]
OP_CMPEQB also requesting change of output reg (stop that)

16 months agoOP_CMP is requesting a change of the output register (should not do that)
Luke Kenneth Casson Leighton [Sun, 31 May 2020 13:26:21 +0000 (14:26 +0100)]
OP_CMP is requesting a change of the output register (should not do that)

16 months agostill investigating
Luke Kenneth Casson Leighton [Sun, 31 May 2020 12:19:35 +0000 (13:19 +0100)]
still investigating

16 months agostart with zero, try not to compare against 9 bytes in a 64-bit value: cmpeqb test
Luke Kenneth Casson Leighton [Sun, 31 May 2020 12:08:22 +0000 (13:08 +0100)]
start with zero, try not to compare against 9 bytes in a 64-bit value: cmpeqb test

16 months agomore debug statements
Luke Kenneth Casson Leighton [Sun, 31 May 2020 12:04:13 +0000 (13:04 +0100)]
more debug statements

16 months agoadd in more CR debug statements
Luke Kenneth Casson Leighton [Sun, 31 May 2020 11:54:53 +0000 (12:54 +0100)]
add in more CR debug statements

16 months agocopy in cr0.data into cr0 temp, not whole of cr0 (including ok flag)
Luke Kenneth Casson Leighton [Sun, 31 May 2020 11:54:29 +0000 (12:54 +0100)]
copy in cr0.data into cr0 temp, not whole of cr0 (including ok flag)

16 months agoremove commented-out vars from ALU input record
Luke Kenneth Casson Leighton [Sun, 31 May 2020 11:33:30 +0000 (12:33 +0100)]
remove commented-out vars from ALU input record

16 months agowrite cr0 when op.write_cr.ok is set
Luke Kenneth Casson Leighton [Sun, 31 May 2020 11:28:38 +0000 (12:28 +0100)]
write cr0 when op.write_cr.ok is set

16 months agoadd write_cr to ALU record subset
Luke Kenneth Casson Leighton [Sun, 31 May 2020 11:27:45 +0000 (12:27 +0100)]
add write_cr to ALU record subset

16 months agocomment out xer ov/so for now
Luke Kenneth Casson Leighton [Sun, 31 May 2020 10:21:31 +0000 (11:21 +0100)]
comment out xer ov/so for now

16 months agoget carry from cr write_cr
Luke Kenneth Casson Leighton [Sat, 30 May 2020 22:33:40 +0000 (23:33 +0100)]
get carry from cr write_cr

16 months agoselect CR0 write out only when RC=1
Luke Kenneth Casson Leighton [Sat, 30 May 2020 22:31:25 +0000 (23:31 +0100)]
select CR0 write out only when RC=1

16 months agoset CR0 output when OP_CMP or OP_CMPEQB need it
Luke Kenneth Casson Leighton [Sat, 30 May 2020 20:28:13 +0000 (21:28 +0100)]
set CR0 output when OP_CMP or OP_CMPEQB need it

16 months agoadd in use of "Settle"
Luke Kenneth Casson Leighton [Sat, 30 May 2020 19:39:08 +0000 (20:39 +0100)]
add in use of "Settle"

16 months agoadd in write-mask into MultiCompUnit and MCU-ALU unit test: bug detected in
Luke Kenneth Casson Leighton [Sat, 30 May 2020 19:37:10 +0000 (20:37 +0100)]
add in write-mask into MultiCompUnit and MCU-ALU unit test: bug detected in
RC handling

16 months agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Sat, 30 May 2020 19:12:07 +0000 (21:12 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

16 months agounit test for DataMerger
Tobias Platen [Sat, 30 May 2020 19:11:02 +0000 (21:11 +0200)]
unit test for DataMerger

16 months agocreate read-mask for ALU CompUnit: switches off optional operands
Luke Kenneth Casson Leighton [Sat, 30 May 2020 19:00:33 +0000 (20:00 +0100)]
create read-mask for ALU CompUnit: switches off optional operands

16 months agocreate a write-mask, anything with an "ok" in the Record fields
Luke Kenneth Casson Leighton [Sat, 30 May 2020 18:46:30 +0000 (19:46 +0100)]
create a write-mask, anything with an "ok" in the Record fields

16 months agoallow MultiCompUnit outputs to be Records, to capture Data.ok
Luke Kenneth Casson Leighton [Sat, 30 May 2020 18:39:11 +0000 (19:39 +0100)]
allow MultiCompUnit outputs to be Records, to capture Data.ok

16 months agoadd read-mask to MultiCompUnit
Luke Kenneth Casson Leighton [Sat, 30 May 2020 18:34:08 +0000 (19:34 +0100)]
add read-mask to MultiCompUnit

16 months agocode-shuffle / comments
Luke Kenneth Casson Leighton [Sat, 30 May 2020 18:29:51 +0000 (19:29 +0100)]
code-shuffle / comments

16 months agomess - but a functional mess. ALU-MultiCompUnit semi-functional using pipeline
Luke Kenneth Casson Leighton [Sat, 30 May 2020 15:23:46 +0000 (16:23 +0100)]
mess - but a functional mess.  ALU-MultiCompUnit semi-functional using pipeline

16 months agograb other results from ALU pipeline in compunit test
Luke Kenneth Casson Leighton [Sat, 30 May 2020 13:45:55 +0000 (14:45 +0100)]
grab other results from ALU pipeline in compunit test

16 months agoorder of XER so/ca wrong way round from regspec
Luke Kenneth Casson Leighton [Sat, 30 May 2020 13:27:06 +0000 (14:27 +0100)]
order of XER so/ca wrong way round from regspec

16 months agostill experimenting with ALU-CompUnit interaction
Luke Kenneth Casson Leighton [Sat, 30 May 2020 10:58:30 +0000 (11:58 +0100)]
still experimenting with ALU-CompUnit interaction

16 months agointeresting. use of Settle() works, showing that Regfile is combinatorial on read
Luke Kenneth Casson Leighton [Fri, 29 May 2020 23:51:25 +0000 (00:51 +0100)]
interesting.  use of Settle() works, showing that Regfile is combinatorial on read

16 months agomodule comments for popcount
Luke Kenneth Casson Leighton [Fri, 29 May 2020 21:38:28 +0000 (22:38 +0100)]
module comments for popcount

16 months agocomments on popcount
Luke Kenneth Casson Leighton [Fri, 29 May 2020 21:33:46 +0000 (22:33 +0100)]
comments on popcount

16 months agotrigger ALU ready when operands ready
Luke Kenneth Casson Leighton [Fri, 29 May 2020 16:11:00 +0000 (17:11 +0100)]
trigger ALU ready when operands ready

16 months agofixes for DataMerger
Tobias Platen [Fri, 29 May 2020 16:06:35 +0000 (18:06 +0200)]
fixes for DataMerger

16 months agotrigger read ALU ready/valid from latch as well
Luke Kenneth Casson Leighton [Fri, 29 May 2020 15:49:29 +0000 (16:49 +0100)]
trigger read ALU ready/valid from latch as well

16 months agouse a latch to communicate read/valid output from ALU
Luke Kenneth Casson Leighton [Fri, 29 May 2020 15:30:35 +0000 (16:30 +0100)]
use a latch to communicate read/valid output from ALU

16 months agoDataMerger: rename addr_match_i to addr_array_i
Tobias Platen [Fri, 29 May 2020 15:20:10 +0000 (17:20 +0200)]
DataMerger: rename addr_match_i to addr_array_i

16 months agofixed 'return m is missing'
Tobias Platen [Fri, 29 May 2020 14:43:07 +0000 (16:43 +0200)]
fixed 'return m is missing'

16 months agowhitespace fixes
Tobias Platen [Fri, 29 May 2020 14:40:32 +0000 (16:40 +0200)]
whitespace fixes

16 months agolatch all output on ALU output valid
Luke Kenneth Casson Leighton [Fri, 29 May 2020 13:13:07 +0000 (14:13 +0100)]
latch all output on ALU output valid

16 months agocreate read-done pulse
Luke Kenneth Casson Leighton [Fri, 29 May 2020 12:50:56 +0000 (13:50 +0100)]
create read-done pulse

16 months agowrite-release moves out of "ALU valid" due to using alu_pulse
Luke Kenneth Casson Leighton [Fri, 29 May 2020 12:35:40 +0000 (13:35 +0100)]
write-release moves out of "ALU valid" due to using alu_pulse

16 months agosignal start of request from when ALU triggers result ready
Luke Kenneth Casson Leighton [Fri, 29 May 2020 12:33:45 +0000 (13:33 +0100)]
signal start of request from when ALU triggers result ready