soc.git
12 months agodcbz and tlbie first test, still incomplete
Tobias Platen [Wed, 11 Nov 2020 18:51:41 +0000 (19:51 +0100)]
dcbz and tlbie first test, still incomplete

12 months agofu/mmu/test/test_pipe_caller.py test case for mfspr
Tobias Platen [Wed, 11 Nov 2020 18:09:52 +0000 (19:09 +0100)]
fu/mmu/test/test_pipe_caller.py test case for mfspr

12 months agoadd build commands to Makefile for versa ecp5
Luke Kenneth Casson Leighton [Tue, 10 Nov 2020 19:44:09 +0000 (19:44 +0000)]
add build commands to Makefile for versa ecp5

12 months agosubmodule update
Luke Kenneth Casson Leighton [Tue, 10 Nov 2020 19:37:49 +0000 (19:37 +0000)]
submodule update

12 months agoremove ClockSelect module, use DummyPLL
Luke Kenneth Casson Leighton [Tue, 10 Nov 2020 16:40:33 +0000 (16:40 +0000)]
remove ClockSelect module, use DummyPLL

12 months agoadd separate DummyPLL module, according to API discussed at
Luke Kenneth Casson Leighton [Tue, 10 Nov 2020 15:49:56 +0000 (15:49 +0000)]
add separate DummyPLL module, according to API discussed at
https://bugs.libre-soc.org/show_bug.cgi?id=155#c21
;

12 months agommu fsm testcase: add check_fsm_outputs based on function from soc/fu/div/test/helper.py
Tobias Platen [Sun, 8 Nov 2020 12:05:36 +0000 (13:05 +0100)]
mmu fsm testcase: add check_fsm_outputs based on function from soc/fu/div/test/helper.py

12 months agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Sun, 8 Nov 2020 09:31:11 +0000 (10:31 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

12 months agommu/fsm: test case for mtspr
Tobias Platen [Sun, 8 Nov 2020 09:30:08 +0000 (10:30 +0100)]
mmu/fsm: test case for mtspr

12 months agoupdate submodule
Luke Kenneth Casson Leighton [Sat, 7 Nov 2020 22:27:38 +0000 (22:27 +0000)]
update submodule

12 months agofixed a bug in src/soc/fu/mmu/fsm.py
Tobias Platen [Sat, 7 Nov 2020 14:43:07 +0000 (15:43 +0100)]
fixed a bug in src/soc/fu/mmu/fsm.py

12 months agosigh sorting out litex pin-connections to sdram
Luke Kenneth Casson Leighton [Fri, 6 Nov 2020 11:48:01 +0000 (11:48 +0000)]
sigh sorting out litex pin-connections to sdram

13 months agomove back to 3.3v on X3 VERSA ECP5 connector
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 19:10:28 +0000 (19:10 +0000)]
move back to 3.3v on X3 VERSA ECP5 connector

13 months agoMMU: begin test case for 'dcbz'
Tobias Platen [Wed, 4 Nov 2020 17:49:31 +0000 (18:49 +0100)]
MMU: begin test case for 'dcbz'

13 months agofix broken unittest after installing power-instruction-analyzer
Tobias Platen [Tue, 3 Nov 2020 18:48:08 +0000 (19:48 +0100)]
fix broken unittest after installing power-instruction-analyzer

13 months agoswap jtag pinorder to match ulx3s
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 13:53:41 +0000 (13:53 +0000)]
swap jtag pinorder to match ulx3s

13 months agochange LVCMOS level on versa ecp5 jtag to 2.5v
Luke Kenneth Casson Leighton [Tue, 3 Nov 2020 13:40:28 +0000 (13:40 +0000)]
change LVCMOS level on versa ecp5 jtag to 2.5v

13 months agoAdd a check for liveness.
Cesar Strauss [Sun, 1 Nov 2020 17:02:52 +0000 (14:02 -0300)]
Add a check for liveness.

There was already a check for the correctness of the results, but there
was no guarantee that any result would be produced at all.

13 months agoversa_ecp5.py add 4 arbitrarily assigned gpio pins to be used by
Cole Poirier [Fri, 30 Oct 2020 21:33:00 +0000 (14:33 -0700)]
versa_ecp5.py add 4 arbitrarily assigned gpio pins to be used by
Libre-SOC JTAG interface on ulx3s

13 months agoCheck that the read and write counters differ at most by one
Cesar Strauss [Sat, 31 Oct 2020 18:29:37 +0000 (15:29 -0300)]
Check that the read and write counters differ at most by one

This will assure there are no dropped work items.

13 months agoRemove stray comment
Cesar Strauss [Sat, 31 Oct 2020 13:46:00 +0000 (10:46 -0300)]
Remove stray comment

It was part of a code block that was removed.

13 months agoadd JTAG extension to versa_ecp5 then we can use it
Luke Kenneth Casson Leighton [Fri, 30 Oct 2020 18:47:59 +0000 (18:47 +0000)]
add JTAG extension to versa_ecp5 then we can use it

13 months agoImplement an operand producer that talks the rel_o/go_i handshake
Cesar Strauss [Wed, 28 Oct 2020 22:57:55 +0000 (19:57 -0300)]
Implement an operand producer that talks the rel_o/go_i handshake

It can be instantiated once for each operand port, working in parallel
with the main test-bench process.

13 months agosubmodule update
Luke Kenneth Casson Leighton [Sat, 24 Oct 2020 22:15:01 +0000 (23:15 +0100)]
submodule update

13 months agoCreate a GTKWave document for the test ALU unit tests
Cesar Strauss [Sat, 24 Oct 2020 17:47:16 +0000 (14:47 -0300)]
Create a GTKWave document for the test ALU unit tests

13 months agoadd query about cross-domain on the JTAG enable of WB
Luke Kenneth Casson Leighton [Thu, 22 Oct 2020 15:59:02 +0000 (16:59 +0100)]
add query about cross-domain on the JTAG enable of WB
https://bugs.libre-soc.org/show_bug.cgi?id=520

13 months agoadd detection and disable of Instruction Wishbone based on JTAG command
Luke Kenneth Casson Leighton [Thu, 22 Oct 2020 15:50:37 +0000 (16:50 +0100)]
add detection and disable of Instruction Wishbone based on JTAG command

13 months agoadd detection and disable of LoadStore Wishbone based on JTAG command
Luke Kenneth Casson Leighton [Thu, 22 Oct 2020 15:49:11 +0000 (16:49 +0100)]
add detection and disable of LoadStore Wishbone based on JTAG command

13 months agoadd JTAG enable/disable of wishbone to TestIssuer
Luke Kenneth Casson Leighton [Thu, 22 Oct 2020 15:47:23 +0000 (16:47 +0100)]
add JTAG enable/disable of wishbone to TestIssuer

13 months agoadd means to JTAG interface to enable/disable "stuff" currently just WB
Luke Kenneth Casson Leighton [Thu, 22 Oct 2020 13:13:11 +0000 (14:13 +0100)]
add means to JTAG interface to enable/disable "stuff"  currently just WB

13 months agoversa_ecp5 adds ability to build and load for ulx3s85f, fixes testgpio
Cole Poirier [Wed, 21 Oct 2020 21:26:10 +0000 (14:26 -0700)]
versa_ecp5 adds ability to build and load for ulx3s85f, fixes testgpio
feature

13 months agofix up asserts (check correct pads/cores)
Luke Kenneth Casson Leighton [Wed, 21 Oct 2020 16:47:15 +0000 (17:47 +0100)]
fix up asserts (check correct pads/cores)
https://bugs.libre-soc.org/show_bug.cgi?id=511#c12

13 months agos/alu/fsm/g
Tobias Platen [Tue, 20 Oct 2020 17:42:50 +0000 (19:42 +0200)]
s/alu/fsm/g

13 months agotest case for FSMMMUStage
Tobias Platen [Tue, 20 Oct 2020 16:41:39 +0000 (18:41 +0200)]
test case for FSMMMUStage

13 months agouse random.seed to generate repro cases of the two different failure
Cole Poirier [Sun, 18 Oct 2020 00:39:22 +0000 (17:39 -0700)]
use random.seed to generate repro cases of the two different failure
modes of test_icache()

13 months agoexperiment swapping dummy trap stage over to input
Luke Kenneth Casson Leighton [Fri, 16 Oct 2020 19:51:09 +0000 (20:51 +0100)]
experiment swapping dummy trap stage over to input

13 months agore-enable tests
Luke Kenneth Casson Leighton [Fri, 16 Oct 2020 18:29:16 +0000 (19:29 +0100)]
re-enable tests

13 months agomanually run coresync clock for test issuer
Luke Kenneth Casson Leighton [Fri, 16 Oct 2020 18:28:36 +0000 (19:28 +0100)]
manually run coresync clock for test issuer

13 months agoset defaults in pspec
Luke Kenneth Casson Leighton [Fri, 16 Oct 2020 18:26:05 +0000 (19:26 +0100)]
set defaults in pspec

13 months agoupdate submodule
Luke Kenneth Casson Leighton [Fri, 16 Oct 2020 18:14:50 +0000 (19:14 +0100)]
update submodule

13 months agoadd extra (test dummy stage in trap to see if combinatorial latency is reduced
Luke Kenneth Casson Leighton [Fri, 16 Oct 2020 18:09:40 +0000 (19:09 +0100)]
add extra (test dummy stage in trap to see if combinatorial latency is reduced

13 months agoadd LGPLv3+ notice and add copyright holders
Luke Kenneth Casson Leighton [Fri, 16 Oct 2020 18:08:24 +0000 (19:08 +0100)]
add LGPLv3+ notice and add copyright holders

13 months agoadd commented-out connection to JTAG in ECP5 litex
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 20:43:22 +0000 (21:43 +0100)]
add commented-out connection to JTAG in ECP5 litex

13 months agowrong pspec variable in selecting pll clock
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 17:11:11 +0000 (18:11 +0100)]
wrong pspec variable in selecting pll clock

13 months agosorting out missing clock somewhere
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 17:05:44 +0000 (18:05 +0100)]
sorting out missing clock somewhere

13 months agouse "enable" and set default actions in getopt
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 16:43:27 +0000 (17:43 +0100)]
use "enable" and set default actions in getopt

13 months agoadd extra variant to litex core
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 14:59:21 +0000 (15:59 +0100)]
add extra variant to litex core

13 months agosyntax error
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 14:58:09 +0000 (15:58 +0100)]
syntax error

13 months agodisable gpio in litex core
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 14:53:00 +0000 (15:53 +0100)]
disable gpio in litex core

13 months agoenable/disable litex irqs based on variant name
Luke Kenneth Casson Leighton [Thu, 15 Oct 2020 12:25:49 +0000 (13:25 +0100)]
enable/disable litex irqs based on variant name

13 months agoMakefile develop, when running setup.py develop specify --user so admin
Cole Poirier [Wed, 14 Oct 2020 00:37:32 +0000 (17:37 -0700)]
Makefile develop, when running setup.py develop specify --user so admin
access is not needed

13 months agoissuer_verilog.py update to use commandline args using argparse, fix
Cole Poirier [Wed, 14 Oct 2020 00:04:43 +0000 (17:04 -0700)]
issuer_verilog.py update to use commandline args using argparse, fix
formatting

13 months agomove pia from install_requires to test_requires
Cole Poirier [Tue, 13 Oct 2020 17:21:53 +0000 (10:21 -0700)]
move pia from install_requires to test_requires

13 months agolitex/florent/versa_ecp5.py add arg --fpga [versa_ecp5|ulx3s85f] default
Cole Poirier [Mon, 12 Oct 2020 23:30:10 +0000 (16:30 -0700)]
litex/florent/versa_ecp5.py add arg --fpga [versa_ecp5|ulx3s85f] default
of versa_ecp5, to build for different fpga targets, fix whitespace,
delete ulx3s85f.py as it's no longer needed

13 months agofix ModuleNotFound/Import errors found when running pytest, just due to
Cole Poirier [Mon, 12 Oct 2020 22:24:03 +0000 (15:24 -0700)]
fix ModuleNotFound/Import errors found when running pytest, just due to
things being renamed and not kept in sync

13 months agoupdate gitlab ci
Tobias Platen [Mon, 12 Oct 2020 20:00:40 +0000 (20:00 +0000)]
update gitlab ci

13 months agoadd tested working fpga compile/build/load file for ulxs3s LFE5U-85F as ulx3s85f...
Cole Poirier [Mon, 12 Oct 2020 19:36:20 +0000 (12:36 -0700)]
add tested working fpga compile/build/load file for ulxs3s LFE5U-85F as ulx3s85f.py based on versa_ecp5.py

13 months agoadd way to bypass PLL for ECP5 and sim
Luke Kenneth Casson Leighton [Sun, 11 Oct 2020 15:01:58 +0000 (16:01 +0100)]
add way to bypass PLL for ECP5 and sim

13 months agocomment out XICS/GPIO interrupt test, causes ECP5 litex build to fail
Luke Kenneth Casson Leighton [Sun, 11 Oct 2020 13:57:38 +0000 (14:57 +0100)]
comment out XICS/GPIO interrupt test, causes ECP5 litex build to fail
(input incorrectly detected as output)

13 months agorecord commands for building ECP5
Luke Kenneth Casson Leighton [Sun, 11 Oct 2020 13:50:11 +0000 (14:50 +0100)]
record commands for building ECP5

13 months agolitex sim.py operational
Luke Kenneth Casson Leighton [Sun, 11 Oct 2020 13:19:55 +0000 (14:19 +0100)]
litex sim.py operational

13 months agoflorent/versa_ecp5.py remove uneccessary imports, specify actual import
Cole Poirier [Sat, 10 Oct 2020 20:38:11 +0000 (13:38 -0700)]
florent/versa_ecp5.py remove uneccessary imports, specify actual import
instead of evil 'import *'

13 months agoadd debug start/stop to firmware_upload script
Luke Kenneth Casson Leighton [Sat, 10 Oct 2020 16:12:54 +0000 (17:12 +0100)]
add debug start/stop to firmware_upload script

13 months agoadd DMI status / reset to firmware upload script
Luke Kenneth Casson Leighton [Sat, 10 Oct 2020 14:45:59 +0000 (15:45 +0100)]
add DMI status / reset to firmware upload script

13 months agoadd first version of firmware uploader
Luke Kenneth Casson Leighton [Sat, 10 Oct 2020 14:13:38 +0000 (15:13 +0100)]
add first version of firmware uploader

13 months agoupdate submodule
Jacob Lifshay [Fri, 9 Oct 2020 23:33:39 +0000 (16:33 -0700)]
update submodule

13 months agoupdate submodule
Jacob Lifshay [Fri, 9 Oct 2020 22:57:01 +0000 (15:57 -0700)]
update submodule

13 months agouse libresoc version of c4m-jtag repo
Luke Kenneth Casson Leighton [Fri, 9 Oct 2020 13:16:20 +0000 (14:16 +0100)]
use libresoc version of c4m-jtag repo

13 months agosubmodule update
Luke Kenneth Casson Leighton [Fri, 9 Oct 2020 11:06:48 +0000 (12:06 +0100)]
submodule update

13 months agodrop in "undefined" function into ISAcaller namespace
Luke Kenneth Casson Leighton [Fri, 9 Oct 2020 10:51:18 +0000 (11:51 +0100)]
drop in "undefined" function into ISAcaller namespace

13 months agorename undef to undefined (preserving the fact that it is a function)
Luke Kenneth Casson Leighton [Fri, 9 Oct 2020 10:34:29 +0000 (11:34 +0100)]
rename undef to undefined (preserving the fact that it is a function)

13 months agomissing yields in JTAG pads test to allow settling
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 22:36:35 +0000 (23:36 +0100)]
missing yields in JTAG pads test to allow settling

13 months agofinish converting mul tests to use common code
Jacob Lifshay [Fri, 9 Oct 2020 04:19:07 +0000 (21:19 -0700)]
finish converting mul tests to use common code

13 months agoworking on splitting out common mul pipe test code
Jacob Lifshay [Fri, 9 Oct 2020 03:24:02 +0000 (20:24 -0700)]
working on splitting out common mul pipe test code

add initial tests for mul-add instructions

13 months agoadd carry handling to pia_res_to_output
Jacob Lifshay [Fri, 9 Oct 2020 03:23:17 +0000 (20:23 -0700)]
add carry handling to pia_res_to_output

13 months agomove pia_res_to_output to common test helpers
Jacob Lifshay [Fri, 9 Oct 2020 03:21:51 +0000 (20:21 -0700)]
move pia_res_to_output to common test helpers

13 months agomove mul pipe ilang test to separate file
Jacob Lifshay [Fri, 9 Oct 2020 00:45:32 +0000 (17:45 -0700)]
move mul pipe ilang test to separate file

13 months agoadd undef()
Jacob Lifshay [Fri, 9 Oct 2020 00:31:46 +0000 (17:31 -0700)]
add undef()

13 months agoupdate submodule
Jacob Lifshay [Fri, 9 Oct 2020 00:31:27 +0000 (17:31 -0700)]
update submodule

13 months agoupdate submodule
Jacob Lifshay [Thu, 8 Oct 2020 23:56:03 +0000 (16:56 -0700)]
update submodule

13 months agomissing yields in JTAG pads test to allow settling
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 22:34:23 +0000 (23:34 +0100)]
missing yields in JTAG pads test to allow settling

13 months agominor icache cleanup
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 22:27:02 +0000 (23:27 +0100)]
minor icache cleanup

13 months agosecond attempt at https://bugs.libre-soc.org/show_bug.cgi?id=485#c59,
Cole Poirier [Thu, 8 Oct 2020 20:31:51 +0000 (13:31 -0700)]
second attempt at https://bugs.libre-soc.org/show_bug.cgi?id=485#c59,
still not working properly, but it's closer

13 months agoremove singleton dict per https://bugs.libre-soc.org/show_bug.cgi?id=485#c58
Cole Poirier [Thu, 8 Oct 2020 19:28:02 +0000 (12:28 -0700)]
remove singleton dict per https://bugs.libre-soc.org/show_bug.cgi?id=485#c58

13 months agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Thu, 8 Oct 2020 18:16:40 +0000 (20:16 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

13 months agoadd WIP test_pipe_caller.py for mmu
Tobias Platen [Thu, 8 Oct 2020 17:39:06 +0000 (19:39 +0200)]
add WIP test_pipe_caller.py for mmu

13 months agoadd incoming PortInterface to be connected to LoadStoreCompUnit
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 17:13:50 +0000 (18:13 +0100)]
add incoming PortInterface to be connected to LoadStoreCompUnit

13 months agoJTAG boundary scan test 1st attempt
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 13:48:42 +0000 (14:48 +0100)]
JTAG boundary scan test 1st attempt

13 months agorework jtag test to use JTAG class not DMITAP
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 12:47:42 +0000 (13:47 +0100)]
rework jtag test to use JTAG class not DMITAP

13 months agosplit out jtag util functions to separate module
Luke Kenneth Casson Leighton [Thu, 8 Oct 2020 12:21:36 +0000 (13:21 +0100)]
split out jtag util functions to separate module

13 months agofirst attempt at 3) of
Cole Poirier [Thu, 8 Oct 2020 01:55:14 +0000 (18:55 -0700)]
first attempt at 3) of
https://bugs.libre-soc.org/show_bug.cgi?id=485#c41, not working yet

13 months agomodify wb_get per 1) of https://bugs.libre-soc.org/show_bug.cgi?id=485#c41
Cole Poirier [Thu, 8 Oct 2020 01:14:33 +0000 (18:14 -0700)]
modify wb_get per 1) of https://bugs.libre-soc.org/show_bug.cgi?id=485#c41

13 months agoconnect mmu_done, ldst_error, cache_paradox
Tobias Platen [Wed, 7 Oct 2020 19:52:44 +0000 (21:52 +0200)]
connect mmu_done, ldst_error, cache_paradox

13 months agomissing invert_in field from shiftrot input record
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 17:28:53 +0000 (18:28 +0100)]
missing invert_in field from shiftrot input record

13 months agogit submodule update
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 15:11:20 +0000 (16:11 +0100)]
git submodule update

13 months agoreorder / reorganise reset signals slightly
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 12:01:03 +0000 (13:01 +0100)]
reorder / reorganise reset signals slightly

13 months agofix div tests
Jacob Lifshay [Wed, 7 Oct 2020 04:01:15 +0000 (21:01 -0700)]
fix div tests

13 months agoupdate submodule
Jacob Lifshay [Wed, 7 Oct 2020 03:59:40 +0000 (20:59 -0700)]
update submodule

13 months agoFix forgotten test_pipe_caller changes from e0b4334c7d83dda41d5610239150079f30a2f713
Jacob Lifshay [Wed, 7 Oct 2020 01:36:06 +0000 (18:36 -0700)]
Fix forgotten test_pipe_caller changes from e0b4334c7d83dda41d5610239150079f30a2f713

13 months agoremove redunant signals
Tobias Platen [Tue, 6 Oct 2020 19:31:14 +0000 (21:31 +0200)]
remove redunant signals