soc.git
15 months agoattempting to access self.msr directly
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 19:31:05 +0000 (20:31 +0100)]
attempting to access self.msr directly

15 months agoSPR: FV that should fail currently passes
Samuel A. Falvo II [Tue, 14 Jul 2020 19:17:45 +0000 (12:17 -0700)]
SPR: FV that should fail currently passes

WIP.  Cannot figure out why this is not failing.  Code review requested.

15 months agoset up masks for OP_RL* formal proof
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 15:06:29 +0000 (16:06 +0100)]
set up masks for OP_RL* formal proof

15 months agoadd priv instruction checking to ISACaller simulator
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 13:05:38 +0000 (14:05 +0100)]
add priv instruction checking to ISACaller simulator

15 months agoadd in privileged instruction decision-making in PowerDecode2
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 12:00:19 +0000 (13:00 +0100)]
add in privileged instruction decision-making in PowerDecode2

15 months agoadd MSR reading to issue FSM
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 11:43:53 +0000 (12:43 +0100)]
add MSR reading to issue FSM

15 months agocomments on PowerDecode2
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 11:00:54 +0000 (12:00 +0100)]
comments on PowerDecode2

15 months agoadd MSR to PowerDecoder2
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 10:47:05 +0000 (11:47 +0100)]
add MSR to PowerDecoder2

15 months agodisable cxxsim test
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 10:42:29 +0000 (11:42 +0100)]
disable cxxsim test

15 months agoattempting running cxxsim on ALU pipeline test
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 10:41:41 +0000 (11:41 +0100)]
attempting running cxxsim on ALU pipeline test

15 months agofirst attempt running cxxsim
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 22:59:34 +0000 (23:59 +0100)]
first attempt running cxxsim

15 months agofix path to nmigen-soc.git
Tobias Platen [Tue, 14 Jul 2020 05:32:42 +0000 (07:32 +0200)]
fix path to nmigen-soc.git

15 months agowhitespace
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 19:30:39 +0000 (20:30 +0100)]
whitespace

15 months agoformal proof of OP_EXTSWSLI
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 19:28:11 +0000 (20:28 +0100)]
formal proof of OP_EXTSWSLI

15 months agoquick test showing how left/right mask work
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 19:27:56 +0000 (20:27 +0100)]
quick test showing how left/right mask work

15 months agoadd nmigen-soc to .gitlab-ci.yml
Tobias Platen [Mon, 13 Jul 2020 18:13:03 +0000 (20:13 +0200)]
add nmigen-soc to .gitlab-ci.yml

15 months agoadd mtmsrd instruction and unit test
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 18:07:08 +0000 (19:07 +0100)]
add mtmsrd instruction and unit test

15 months agocomments
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 15:14:24 +0000 (16:14 +0100)]
comments

15 months agoattempting formal proof of OP_EXTSWSLI
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 15:07:09 +0000 (16:07 +0100)]
attempting formal proof of OP_EXTSWSLI

15 months agoreduce rotl module to one line (use bit_select)
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 14:13:21 +0000 (15:13 +0100)]
reduce rotl module to one line (use bit_select)

15 months agodocument rb as sh
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 13:55:04 +0000 (14:55 +0100)]
document rb as sh

15 months agoincrease range of test values for extswsli
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 13:45:09 +0000 (14:45 +0100)]
increase range of test values for extswsli

15 months agoadd EXTSWSLI "pass" to formal shift_rot proof
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 13:21:44 +0000 (14:21 +0100)]
add EXTSWSLI "pass" to formal shift_rot proof

15 months agoremove unneeded spec patching
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 13:18:14 +0000 (14:18 +0100)]
remove unneeded spec patching

15 months agoenable extswsli tests, fix spec-patching
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 13:17:34 +0000 (14:17 +0100)]
enable extswsli tests, fix spec-patching

15 months agoadd regression test, simulator is wrong
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 12:03:28 +0000 (13:03 +0100)]
add regression test, simulator is wrong

15 months agoadd simulator test against qemu for extswsli
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 12:02:22 +0000 (13:02 +0100)]
add simulator test against qemu for extswsli

15 months agofix read of sliced register
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 11:55:48 +0000 (12:55 +0100)]
fix read of sliced register

15 months agonot perfect but close enough: add read registers RA/S/B/C in parser
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 10:30:30 +0000 (11:30 +0100)]
not perfect but close enough: add read registers RA/S/B/C in parser

15 months agoadd extswsli unit test
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 10:27:08 +0000 (11:27 +0100)]
add extswsli unit test

15 months agoadd link to rotator, sign-extend mode OP_EXTSWSLI
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 10:02:15 +0000 (11:02 +0100)]
add link to rotator, sign-extend mode OP_EXTSWSLI

15 months agorename InternalOp to MicrOp
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 22:01:50 +0000 (23:01 +0100)]
rename InternalOp to MicrOp

15 months agoattempting to get test_trap_sim working, seems to switch mode
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 21:08:45 +0000 (22:08 +0100)]
attempting to get test_trap_sim working, seems to switch mode

15 months agosubmodule update
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:55:54 +0000 (21:55 +0100)]
submodule update

15 months agoadd OP_ATTN test back in
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:55:48 +0000 (21:55 +0100)]
add OP_ATTN test back in

15 months agoexit FSM when termination detected
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:48:36 +0000 (21:48 +0100)]
exit FSM when termination detected

15 months agocode-morph on core connect_instruction
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:32:44 +0000 (21:32 +0100)]
code-morph on core connect_instruction

15 months agomodify PowerDecoder to read LDSTMode correctly
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:04:24 +0000 (21:04 +0100)]
modify PowerDecoder to read LDSTMode correctly

15 months agochange CSV LD/ST update field to LDSTMode (support cix)
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 19:46:47 +0000 (20:46 +0100)]
change CSV LD/ST update field to LDSTMode (support cix)

15 months agoreturn unsigned int from binary reading
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 12:33:19 +0000 (13:33 +0100)]
return unsigned int from binary reading

15 months agoupdate submodule
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 12:13:09 +0000 (13:13 +0100)]
update submodule

15 months agomissed setting of link register on OP_BC in PowerDecoder2
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 10:46:22 +0000 (11:46 +0100)]
missed setting of link register on OP_BC in PowerDecoder2

15 months agomsb of instruction causing sign-overflow
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 04:10:10 +0000 (05:10 +0100)]
msb of instruction causing sign-overflow

15 months agoadd std and stdu ldst unit tests
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 03:46:31 +0000 (04:46 +0100)]
add std and stdu ldst unit tests

15 months agoupdate-mode request write signalled too early
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 03:46:04 +0000 (04:46 +0100)]
update-mode request write signalled too early

15 months agosort out core write latching: gate by busy, and use CompUnit dest output
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 22:48:46 +0000 (23:48 +0100)]
sort out core write latching: gate by busy, and use CompUnit dest output

15 months ago* clarifying core function unit enable
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 22:24:20 +0000 (23:24 +0100)]
* clarifying core function unit enable
* disabling wrflag based on fu busy
* NOP enabled when not stopped
g

15 months agoadd bigendian flag
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 22:13:44 +0000 (23:13 +0100)]
add bigendian flag

15 months agoadd endian
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 21:53:19 +0000 (22:53 +0100)]
add endian

15 months agofix spr setting, set endianness
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 21:50:37 +0000 (22:50 +0100)]
fix spr setting, set endianness

15 months agosigh spelling
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 21:48:58 +0000 (22:48 +0100)]
sigh spelling

15 months agoadd bigendian
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 21:46:10 +0000 (22:46 +0100)]
add bigendian

15 months agomore setting bigendian
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 20:06:51 +0000 (21:06 +0100)]
more setting bigendian

15 months agoadd bigendian mode to helloworld test
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 20:01:47 +0000 (21:01 +0100)]
add bigendian mode to helloworld test

15 months agosort out big/little endian startup on qemu
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 16:38:14 +0000 (17:38 +0100)]
sort out big/little endian startup on qemu

15 months agosorting out bigendian/littleendian including in qemu
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 16:34:07 +0000 (17:34 +0100)]
sorting out bigendian/littleendian including in qemu
qemu is a pain!

15 months agowhoops output trunc_divs not trunc_div
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 11:35:23 +0000 (12:35 +0100)]
whoops output trunc_divs not trunc_div

15 months agoadd random mulhd and mulld tests
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 11:02:29 +0000 (12:02 +0100)]
add random mulhd and mulld tests

15 months agoenable mul tests after sorting pseudo-code mul overflow
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 10:26:20 +0000 (11:26 +0100)]
enable mul tests after sorting pseudo-code mul overflow

15 months agospecial test for mul hw to cope with ignoring OE flag
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 10:08:48 +0000 (11:08 +0100)]
special test for mul hw to cope with ignoring OE flag

15 months agoadd a DIVS function as separate and discrete from floor_div
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 20:09:30 +0000 (21:09 +0100)]
add a DIVS function as separate and discrete from floor_div
likewise for MODS and MULS

15 months agoadd random unsigned div tests
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 15:29:07 +0000 (16:29 +0100)]
add random unsigned div tests

15 months agoadd overflow div tests
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 15:28:24 +0000 (16:28 +0100)]
add overflow div tests

15 months agopropagate missing parameters from div
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 15:28:12 +0000 (16:28 +0100)]
propagate missing parameters from div

15 months agocode comments
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 15:27:01 +0000 (16:27 +0100)]
code comments

15 months agodo not set div result if overflow occurs
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 15:16:12 +0000 (16:16 +0100)]
do not set div result if overflow occurs

15 months agore-enable div random tests and other regressions
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 15:05:23 +0000 (16:05 +0100)]
re-enable div random tests and other regressions

15 months agocheck for div_overflow equal to None rather than == 1
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 15:04:08 +0000 (16:04 +0100)]
check for div_overflow equal to None rather than == 1

15 months agore-add rc/oe back into LDST input record
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 13:30:28 +0000 (14:30 +0100)]
re-add rc/oe back into LDST input record
this for later use with st*cx because it writes CR and OV (and SO)

15 months agowhew panic over, missed a bigendian argument in test_compunit.py
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 13:21:48 +0000 (14:21 +0100)]
whew panic over, missed a bigendian argument in test_compunit.py

15 months agoadd test7 div regression
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 13:12:50 +0000 (14:12 +0100)]
add test7 div regression

15 months agoadd more debug output for #425
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 09:40:15 +0000 (10:40 +0100)]
add more debug output for #425

15 months agoadd debugging chain for #425
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 09:16:28 +0000 (10:16 +0100)]
add debugging chain for #425

15 months agoupdate submodule
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 09:15:52 +0000 (10:15 +0100)]
update submodule

15 months agocut/paste error writing to wrong vcd file
Luke Kenneth Casson Leighton [Fri, 10 Jul 2020 08:44:27 +0000 (09:44 +0100)]
cut/paste error writing to wrong vcd file

15 months agoswitch to using Signal.width instead of Signal.shape()[0] since Shape isn't a tuple...
Jacob Lifshay [Fri, 10 Jul 2020 00:21:37 +0000 (17:21 -0700)]
switch to using Signal.width instead of Signal.shape()[0] since Shape isn't a tuple anymore

see https://github.com/nmigen/nmigen/pull/422

15 months agoformat file
Jacob Lifshay [Fri, 10 Jul 2020 00:21:19 +0000 (17:21 -0700)]
format file

15 months agoupdate libreriscv submodule
Jacob Lifshay [Fri, 10 Jul 2020 00:19:29 +0000 (17:19 -0700)]
update libreriscv submodule

15 months agoadd regression test for div overflow case
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 23:18:53 +0000 (00:18 +0100)]
add regression test for div overflow case
see https://bugs.libre-soc.org/show_bug.cgi?id=425

15 months agoslightly different so handling in common output stage
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 21:20:41 +0000 (22:20 +0100)]
slightly different so handling in common output stage

15 months agoalso set so only if OE requires it
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 21:08:55 +0000 (22:08 +0100)]
also set so only if OE requires it

15 months agodebug information related to 32/64 bit mode
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 21:08:15 +0000 (22:08 +0100)]
debug information related to 32/64 bit mode

15 months agobug #424 - 32/64 bit is a *global* flag not a per-op one
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 21:07:06 +0000 (22:07 +0100)]
bug #424 - 32/64 bit is a *global* flag not a per-op one
when it comes to setting CR0

15 months agotest top bit 31 in 32-bit mode for CR0 creation
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 20:10:37 +0000 (21:10 +0100)]
test top bit 31 in 32-bit mode for CR0 creation

15 months agoha ha very funny. pipelines being pipelines, you have to wait for them
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:54:09 +0000 (20:54 +0100)]
ha ha very funny.  pipelines being pipelines, you have to wait for them
just as with MUL, it was necessary to set the "valid" signal for
only one cycle otherwise spurious output is created

15 months agowhoops test gets copied 4 times on the If.
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:44:34 +0000 (20:44 +0100)]
whoops test gets copied 4 times on the If.
create intermediate signal

15 months agoALU output stage, change logic slightly
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:37:14 +0000 (20:37 +0100)]
ALU output stage, change logic slightly
test for oe/ok then set xer/ov data/ok if true

15 months agoset xer_ov.ok = 1
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:28:54 +0000 (20:28 +0100)]
set xer_ov.ok = 1

15 months agoremove unneeded xer.ca in MulOutputData
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:18:04 +0000 (20:18 +0100)]
remove unneeded xer.ca in MulOutputData

15 months agosomething weird going on with div. interaction between tests
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:14:29 +0000 (20:14 +0100)]
something weird going on with div.  interaction between tests

15 months agosimplify setting of mul overflow into xer_ov
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:00:29 +0000 (20:00 +0100)]
simplify setting of mul overflow into xer_ov

15 months agoclarifying comments on setting xer_ov/so
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 19:00:07 +0000 (20:00 +0100)]
clarifying comments on setting xer_ov/so

15 months agoDIV overflow needs to be copied into both bits of XER.ov
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 18:59:45 +0000 (19:59 +0100)]
DIV overflow needs to be copied into both bits of XER.ov
(OV, OV32)

15 months agoadd debug output of DIV results
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 18:58:13 +0000 (19:58 +0100)]
add debug output of DIV results

15 months agocheck result first then CR second
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 18:57:34 +0000 (19:57 +0100)]
check result first then CR second

15 months agomunge alu_fsm Shifter into looking like CompALU API compliant
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 17:07:25 +0000 (18:07 +0100)]
munge alu_fsm Shifter into looking like CompALU API compliant

15 months agoresolving issues with div tests (turned out to be nmutil.divmod)
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 12:34:07 +0000 (13:34 +0100)]
resolving issues with div tests (turned out to be nmutil.divmod)
adding more tests to track down a CR0 issue

15 months agoremove xer_ca from DIV pipeline (took a bit of messing about)
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 10:49:51 +0000 (11:49 +0100)]
remove xer_ca from DIV pipeline (took a bit of messing about)

15 months agoDefine ports for a simple sequential Shifter
Cesar Strauss [Thu, 9 Jul 2020 09:50:47 +0000 (06:50 -0300)]
Define ports for a simple sequential Shifter

15 months agoirony comment on how one line creates a massive array of gates
Luke Kenneth Casson Leighton [Thu, 9 Jul 2020 09:55:52 +0000 (10:55 +0100)]
irony comment on how one line creates a massive array of gates