soc.git
7 hours agoput mbits back into segment_check (like it is in microwatt) master
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:28:29 +0000 (01:28 +0100)]
put mbits back into segment_check (like it is in microwatt)

7 hours agoradixmmu cleanup
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:08:51 +0000 (01:08 +0100)]
radixmmu cleanup

7 hours agocall addrshift and get_pgtable_addr inside while loop for radixmmu
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:04:07 +0000 (01:04 +0100)]
call addrshift and get_pgtable_addr inside while loop for radixmmu

7 hours agocode-cleanup in radixmmu
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:00:01 +0000 (01:00 +0100)]
code-cleanup in radixmmu

8 hours agowhitespace and corrections to NLS, RTS1, RTS2
Luke Kenneth Casson Leighton [Thu, 15 Apr 2021 23:21:09 +0000 (00:21 +0100)]
whitespace and corrections to NLS, RTS1, RTS2

14 hours agofix radix testcase
Tobias Platen [Thu, 15 Apr 2021 17:05:51 +0000 (19:05 +0200)]
fix radix testcase

15 hours agoconcat en_sigs together in JTAG to make sure they are not missed out
Luke Kenneth Casson Leighton [Thu, 15 Apr 2021 15:43:12 +0000 (16:43 +0100)]
concat en_sigs together in JTAG to make sure they are not missed out

22 hours agoadd icachemmu option to ISACaller
Luke Kenneth Casson Leighton [Thu, 15 Apr 2021 08:48:37 +0000 (09:48 +0100)]
add icachemmu option to ISACaller

36 hours agosubmodule update
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 19:08:38 +0000 (20:08 +0100)]
submodule update

36 hours agowhitespace
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 19:08:28 +0000 (20:08 +0100)]
whitespace

36 hours agosubmodule update
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 16:04:24 +0000 (17:04 +0100)]
submodule update

37 hours agoupdate test_caller_radix.py
Tobias Platen [Wed, 14 Apr 2021 18:22:20 +0000 (20:22 +0200)]
update test_caller_radix.py

37 hours agoradixmmu: handle badtree
Tobias Platen [Wed, 14 Apr 2021 18:16:00 +0000 (20:16 +0200)]
radixmmu: handle badtree

37 hours agoupdate test case for radix mmu
Tobias Platen [Wed, 14 Apr 2021 17:39:08 +0000 (19:39 +0200)]
update test case for radix mmu

38 hours agoradixmmu: error handling
Tobias Platen [Wed, 14 Apr 2021 17:34:13 +0000 (19:34 +0200)]
radixmmu: error handling

2 days agomore fixes for radixmmu.py
Tobias Platen [Tue, 13 Apr 2021 17:21:18 +0000 (19:21 +0200)]
more fixes for radixmmu.py

2 days agofix AttributeError in radixmmu testcase
Tobias Platen [Tue, 13 Apr 2021 16:43:37 +0000 (18:43 +0200)]
fix AttributeError in radixmmu testcase

3 days agoradixmmu.py: cleanup
Tobias Platen [Mon, 12 Apr 2021 17:50:20 +0000 (19:50 +0200)]
radixmmu.py: cleanup

4 days agofix bug in radixmmu.py
Tobias Platen [Sun, 11 Apr 2021 18:48:12 +0000 (20:48 +0200)]
fix bug in radixmmu.py

5 days agoradixmmu: more work on segment check
Tobias Platen [Sun, 11 Apr 2021 06:45:06 +0000 (08:45 +0200)]
radixmmu: more work on segment check

5 days agoImplement 1<<r3 predicate mode
Cesar Strauss [Sat, 10 Apr 2021 20:27:48 +0000 (17:27 -0300)]
Implement 1<<r3 predicate mode

The mask bit selected by r3 is set to one.
A possible optimization would be to do step = r3 directly, but this is only
valid in non-zero mode.
The corresponding test cases now pass.

5 days agoAdd 1<<r3 test cases to TestIssuer
Cesar Strauss [Sat, 10 Apr 2021 19:59:19 +0000 (16:59 -0300)]
Add 1<<r3 test cases to TestIssuer

They fail, since it's not implemented yet.

5 days agoAdd test cases for 1<<r3 predication
Cesar Strauss [Sat, 10 Apr 2021 19:40:09 +0000 (16:40 -0300)]
Add test cases for 1<<r3 predication

6 days agoadd blinken lights assembly (not used yet)
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 11:40:48 +0000 (12:40 +0100)]
add blinken lights assembly (not used yet)

7 days agotest firmware upload program needed to branch back further in order to loop
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 00:09:32 +0000 (01:09 +0100)]
test firmware upload program needed to branch back further in order to loop

7 days agosort out pc reset when DMI interface requests reset
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 23:24:42 +0000 (00:24 +0100)]
sort out pc reset when DMI interface requests reset

7 days agosubmodule update
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:53:31 +0000 (21:53 +0100)]
submodule update

7 days agoargh, wb jtag stall probably is not working
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:53:03 +0000 (21:53 +0100)]
argh, wb jtag stall probably is not working

7 days agoupload over 32-bit JTAG Wishbone
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:38:55 +0000 (21:38 +0100)]
upload over 32-bit JTAG Wishbone

7 days agoshrink JTAG master bus to 32-bit (match with litex)
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:21:09 +0000 (21:21 +0100)]
shrink JTAG master bus to 32-bit (match with litex)

8 days agosubmodule update
Luke Kenneth Casson Leighton [Wed, 7 Apr 2021 19:27:37 +0000 (20:27 +0100)]
submodule update

8 days agoWIP: calculate address of first page table entry
Tobias Platen [Wed, 7 Apr 2021 19:17:35 +0000 (21:17 +0200)]
WIP: calculate address of first page table entry

8 days agoradixmmu: fix segment_check function and its caller
Tobias Platen [Wed, 7 Apr 2021 18:26:54 +0000 (20:26 +0200)]
radixmmu: fix segment_check function and its caller

9 days ago4k SRAM Instance needs write-enable @ 8-bit width
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 21:07:12 +0000 (22:07 +0100)]
4k SRAM Instance needs write-enable @ 8-bit width

9 days ago8-bit granularity on JTAG wishbone
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 20:38:04 +0000 (21:38 +0100)]
8-bit granularity on JTAG wishbone

9 days agoremove unneeded code
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 20:35:12 +0000 (21:35 +0100)]
remove unneeded code

9 days agosoc-cocotb-sim submodule update
Staf Verhaegen [Tue, 6 Apr 2021 18:50:58 +0000 (20:50 +0200)]
soc-cocotb-sim submodule update

9 days agoadd mmu_states.dia
Tobias Platen [Tue, 6 Apr 2021 17:21:14 +0000 (19:21 +0200)]
add mmu_states.dia

9 days agogit submodule update
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 14:58:36 +0000 (15:58 +0100)]
git submodule update

9 days agoMake the VL loop reentrant in HDL
Cesar Strauss [Tue, 6 Apr 2021 11:31:14 +0000 (08:31 -0300)]
Make the VL loop reentrant in HDL

This is done by shifting-out already used mask bits, at predicate fetch.
The corresponding test case now passes.

9 days agoAdd a HDL test case, where we start at the middle of the VL loop
Cesar Strauss [Tue, 6 Apr 2021 11:26:43 +0000 (08:26 -0300)]
Add a HDL test case, where we start at the middle of the VL loop

It is expected to fail, since the HDL is not reentrant at this moment.

9 days agoStart the test case from a point where the predicate bits are zeros
Cesar Strauss [Tue, 6 Apr 2021 11:18:26 +0000 (08:18 -0300)]
Start the test case from a point where the predicate bits are zeros

Since SVSTATE is user-programmable, src/dst step can really point anywhere,
at instruction start. Although interrupts will always restore src/dest step
pointing to a set mask bit, this is not guaranteed in general.

10 days agolitex submodule update
Luke Kenneth Casson Leighton [Mon, 5 Apr 2021 11:06:31 +0000 (12:06 +0100)]
litex submodule update

10 days agosubmodule update
Luke Kenneth Casson Leighton [Mon, 5 Apr 2021 10:47:10 +0000 (11:47 +0100)]
submodule update

11 days agosoc-cocotb-sim submodule update
Staf Verhaegen [Sun, 4 Apr 2021 16:09:17 +0000 (18:09 +0200)]
soc-cocotb-sim submodule update

11 days agoAdd test case for reentrant VL loop
Cesar Strauss [Sun, 4 Apr 2021 11:59:22 +0000 (08:59 -0300)]
Add test case for reentrant VL loop

We explicitly initialize src/dst step, as if we were returning from an
interrupt.

12 days agoReminder for a possible hardware optimization
Cesar Strauss [Sat, 3 Apr 2021 20:12:30 +0000 (17:12 -0300)]
Reminder for a possible hardware optimization

12 days agoBe more precise when using a one-bit constant
Cesar Strauss [Sat, 3 Apr 2021 20:02:39 +0000 (17:02 -0300)]
Be more precise when using a one-bit constant

12 days agoFix typo
Cesar Strauss [Sat, 3 Apr 2021 19:18:56 +0000 (16:18 -0300)]
Fix typo

12 days agoAdd test case with all mask bits equal to zero
Cesar Strauss [Sat, 3 Apr 2021 19:16:48 +0000 (16:16 -0300)]
Add test case with all mask bits equal to zero

12 days agoAdd a test case for integer single predication
Cesar Strauss [Sat, 3 Apr 2021 19:04:49 +0000 (16:04 -0300)]
Add a test case for integer single predication

12 days agoDisallow unknown encmodes in SVP64 Assembly
Cesar Strauss [Sat, 3 Apr 2021 18:48:50 +0000 (15:48 -0300)]
Disallow unknown encmodes in SVP64 Assembly

12 days agoEnable remaining disabled test cases
Cesar Strauss [Sat, 3 Apr 2021 18:45:39 +0000 (15:45 -0300)]
Enable remaining disabled test cases

They all work, now, after the ISA Caller fixes.

12 days agoAllow the Simulator to handle back-to-back signaling from TestIssuer
Cesar Strauss [Sat, 3 Apr 2021 18:40:31 +0000 (15:40 -0300)]
Allow the Simulator to handle back-to-back signaling from TestIssuer

TestIssuer can signal the end of an instruction and, after skipping mask
bits, signal the end of the VL loop, right on the following cycle.
Since there is no handshake between TestIssuer and Simulator, we need to
remove any wait state that would cause the Simulator to miss the one-clock
pulse.

12 days agoSignal the simulator when completing a VL loop
Cesar Strauss [Sat, 3 Apr 2021 18:21:37 +0000 (15:21 -0300)]
Signal the simulator when completing a VL loop

When we reach the end of the VL loop, by skipping masked bits in the
predicate, we still need to synchronize with the Simulator, even if no
instruction was issued.

12 days agoFix typo
Cesar Strauss [Sat, 3 Apr 2021 11:21:21 +0000 (08:21 -0300)]
Fix typo

12 days agoAdd twin predication test
Cesar Strauss [Sat, 3 Apr 2021 11:07:51 +0000 (08:07 -0300)]
Add twin predication test

Another simulator failure. Seems like the VL loop is still not terminating
properly. Will investigate.

13 days agoEnd VL loop as soon as either src/dst step reaches VL
Cesar Strauss [Fri, 2 Apr 2021 22:26:21 +0000 (19:26 -0300)]
End VL loop as soon as either src/dst step reaches VL

Also, avoid incrementing dststep beyond VL-1

13 days agoFix typo
Cesar Strauss [Fri, 2 Apr 2021 22:20:26 +0000 (19:20 -0300)]
Fix typo

13 days agoAdd VEXPAND test case for the ISA Simulator
Cesar Strauss [Fri, 2 Apr 2021 20:43:15 +0000 (17:43 -0300)]
Add VEXPAND test case for the ISA Simulator

The test currently does not pass, there must be a bug somewhere.
Seems like it is skipping the middle source element, as if it was doing
single-pred.

13 days agoAdd VCOMPRESS test case for the ISA Simulator
Cesar Strauss [Fri, 2 Apr 2021 20:25:13 +0000 (17:25 -0300)]
Add VCOMPRESS test case for the ISA Simulator

13 days agoPut sanity check inside the existing '2Pred' case, and simplify
Cesar Strauss [Fri, 2 Apr 2021 19:58:48 +0000 (16:58 -0300)]
Put sanity check inside the existing '2Pred' case, and simplify

13 days agoEnforce explicit src/dest masks on CR twin-predication
Cesar Strauss [Fri, 2 Apr 2021 19:53:32 +0000 (16:53 -0300)]
Enforce explicit src/dest masks on CR twin-predication

13 days agoDisallow mixing of sm=xx and/or dm=xx with m=xx on twin-pred
Cesar Strauss [Fri, 2 Apr 2021 19:32:33 +0000 (16:32 -0300)]
Disallow mixing of sm=xx and/or dm=xx with m=xx on twin-pred

13 days agoDisallow dm=xx on single predication
Cesar Strauss [Fri, 2 Apr 2021 18:51:46 +0000 (15:51 -0300)]
Disallow dm=xx on single predication

Adjust test cases accordingly.

13 days agoFix typo
Cesar Strauss [Fri, 2 Apr 2021 17:04:20 +0000 (14:04 -0300)]
Fix typo

13 days agoReally enforce sm=xx not being allowed on single-pred
Cesar Strauss [Fri, 2 Apr 2021 15:06:00 +0000 (12:06 -0300)]
Really enforce sm=xx not being allowed on single-pred

Before, using m=xx together with sm=xx would defeat the assertion.

13 days agoKeep mask mode flags separate
Cesar Strauss [Fri, 2 Apr 2021 14:23:31 +0000 (11:23 -0300)]
Keep mask mode flags separate

Before, when m=xx was seen, we couldn't tell whether sm=xx or dm=xx was
also seen. We will need this, later.
Adjust uses accordingly, preserving truth value.

2 weeks agogit submodule update
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:41:24 +0000 (23:41 +0100)]
git submodule update

2 weeks agoTWI enabled in JTAG boundary scan
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:14:58 +0000 (23:14 +0100)]
TWI enabled in JTAG boundary scan

2 weeks agogit submodule update
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:08:10 +0000 (23:08 +0100)]
git submodule update

2 weeks agoreduce subset of functions to be created in JTAG boundary scan
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:07:53 +0000 (23:07 +0100)]
reduce subset of functions to be created in JTAG boundary scan

2 weeks agouse OrderedDict to restore exact order from JSON file
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:07:26 +0000 (23:07 +0100)]
use OrderedDict to restore exact order from JSON file

2 weeks agoadd soc-cocotb-sim submodule
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 21:46:40 +0000 (22:46 +0100)]
add soc-cocotb-sim submodule

2 weeks agosubmodule update
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 15:52:11 +0000 (16:52 +0100)]
submodule update

2 weeks agolibresoc-litex submodule update
Staf Verhaegen [Thu, 1 Apr 2021 12:56:53 +0000 (14:56 +0200)]
libresoc-litex submodule update

2 weeks agobug in iverilog, segfaults due to empty case statement
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 12:17:53 +0000 (13:17 +0100)]
bug in iverilog, segfaults due to empty case statement

2 weeks agoadd no pll ls180 build
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 12:10:00 +0000 (13:10 +0100)]
add no pll ls180 build

2 weeks agolibresoc-litex submodule update
Staf Verhaegen [Thu, 1 Apr 2021 11:51:33 +0000 (13:51 +0200)]
libresoc-litex submodule update

2 weeks ago_new_lookup: remove unused argument mbits
Tobias Platen [Wed, 31 Mar 2021 19:45:57 +0000 (21:45 +0200)]
_new_lookup: remove unused argument mbits

2 weeks agoradixmmu: read prtable entry
Tobias Platen [Wed, 31 Mar 2021 18:42:24 +0000 (20:42 +0200)]
radixmmu: read prtable entry

2 weeks agoradixmmu.py: remove redunant code
Tobias Platen [Wed, 31 Mar 2021 17:35:14 +0000 (19:35 +0200)]
radixmmu.py: remove redunant code

2 weeks agosubmodule update
Luke Kenneth Casson Leighton [Wed, 31 Mar 2021 13:41:48 +0000 (14:41 +0100)]
submodule update

2 weeks agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Tue, 30 Mar 2021 19:28:16 +0000 (21:28 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

2 weeks agomore work on _prtable_lookup and testcase
Tobias Platen [Tue, 30 Mar 2021 19:27:23 +0000 (21:27 +0200)]
more work on _prtable_lookup and testcase

2 weeks agoadd comments
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 19:16:12 +0000 (20:16 +0100)]
add comments

2 weeks agouse PRTBL SPR in RADIXMMU
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 19:09:34 +0000 (20:09 +0100)]
use PRTBL SPR in RADIXMMU

2 weeks agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Tue, 30 Mar 2021 18:45:52 +0000 (20:45 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

2 weeks agocomment about microwatt implementation details
Tobias Platen [Tue, 30 Mar 2021 18:11:00 +0000 (20:11 +0200)]
comment about microwatt implementation details

2 weeks agosubmodule update
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 18:10:37 +0000 (19:10 +0100)]
submodule update

2 weeks agoadd comments, correct load addresses
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 17:40:32 +0000 (18:40 +0100)]
add comments, correct load addresses

2 weeks agoMerge branch 'master' of git.libre-soc.org:soc
Alain D D Williams [Tue, 30 Mar 2021 18:10:09 +0000 (19:10 +0100)]
Merge branch 'master' of git.libre-soc.org:soc

2 weeks agoAllow comments
Alain D D Williams [Tue, 30 Mar 2021 18:09:41 +0000 (19:09 +0100)]
Allow comments

2 weeks agoadd function _prtable_lookup and unit test
Tobias Platen [Tue, 30 Mar 2021 17:26:41 +0000 (19:26 +0200)]
add function _prtable_lookup and unit test

2 weeks agosubmodule update
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 16:52:44 +0000 (17:52 +0100)]
submodule update

2 weeks agomight have RADIXMMU at least semi-working... maybe
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 15:13:18 +0000 (16:13 +0100)]
might have RADIXMMU at least semi-working... maybe

2 weeks agouse assertEqual in RADIXMMU unit test
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 14:04:23 +0000 (15:04 +0100)]
use assertEqual in RADIXMMU unit test

2 weeks agoskip 1-pred check if m= used in SVP64Asm
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 13:20:27 +0000 (14:20 +0100)]
skip 1-pred check if m= used in SVP64Asm

2 weeks agoEnable VCOMPRESS test case
Cesar Strauss [Tue, 30 Mar 2021 12:47:56 +0000 (09:47 -0300)]
Enable VCOMPRESS test case

VEXPAND seems to have some issue in the Simulator maybe.

2 weeks agosubmodule update
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 12:35:14 +0000 (13:35 +0100)]
submodule update