soc.git
9 months agowhoops tried doing mtspr priv, it failed but failed by trying to run TRAP div_pipeline
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 10:24:09 +0000 (11:24 +0100)]
whoops tried doing mtspr priv, it failed but failed by trying to run TRAP
which is of course not in this pipeline

9 months agoget shiftrot compunit working
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 10:18:05 +0000 (11:18 +0100)]
get shiftrot compunit working

9 months agomore tidyup on use of CompOpSubsetBase
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 10:17:18 +0000 (11:17 +0100)]
more tidyup on use of CompOpSubsetBase

9 months agouse CompOpSubsetBase in ldst record
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 10:14:48 +0000 (11:14 +0100)]
use CompOpSubsetBase in ldst record

9 months agosigh, bug in sprset.patch
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 10:06:04 +0000 (11:06 +0100)]
sigh, bug in sprset.patch

9 months agoupdate cr input record to use new CompOpSubsetBase
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 09:52:14 +0000 (10:52 +0100)]
update cr input record to use new CompOpSubsetBase

9 months agoadd regression test on setb simulator error
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 09:51:52 +0000 (10:51 +0100)]
add regression test on setb simulator error

9 months agouse CompOpSubsetBase class in Branch op record
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 09:47:16 +0000 (10:47 +0100)]
use CompOpSubsetBase class in Branch op record

9 months agoget branch compunit working (missing bigendian arg)
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 09:42:21 +0000 (10:42 +0100)]
get branch compunit working (missing bigendian arg)

9 months agoget trap compunit test working, adding bigendian and msr
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 09:41:13 +0000 (10:41 +0100)]
get trap compunit test working, adding bigendian and msr

9 months agoadd mfmsr trap tests
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 09:26:46 +0000 (10:26 +0100)]
add mfmsr trap tests

9 months agouse new CompOpSubsetBase in trap
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 19:58:10 +0000 (20:58 +0100)]
use new CompOpSubsetBase in trap

9 months agoremove unneeded comment in trap msin stage
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 19:42:36 +0000 (20:42 +0100)]
remove unneeded comment in trap msin stage

9 months agoremove unneeded comment in trap pipe_data
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 19:38:04 +0000 (20:38 +0100)]
remove unneeded comment in trap pipe_data

9 months agodocument branch pipeline relationship with PowerDecode2
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 17:26:27 +0000 (18:26 +0100)]
document branch pipeline relationship with PowerDecode2

9 months agosimplify instr_is_priv
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 16:42:05 +0000 (17:42 +0100)]
simplify instr_is_priv

9 months agomove traptype to soc.consts
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 16:25:12 +0000 (17:25 +0100)]
move traptype to soc.consts

9 months agoadd better comments on mul overflow
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 15:11:19 +0000 (16:11 +0100)]
add better comments on mul overflow

9 months agotest privileged rfid call
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 15:07:53 +0000 (16:07 +0100)]
test privileged rfid call

9 months agospelling error
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 14:59:28 +0000 (15:59 +0100)]
spelling error

9 months agorange of testing overflow was incorrect in mul
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 14:59:02 +0000 (15:59 +0100)]
range of testing overflow was incorrect in mul
see https://bugs.libre-soc.org/show_bug.cgi?id=432

9 months agoset MSR up properly for privileged mtmsr test
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 14:56:54 +0000 (15:56 +0100)]
set MSR up properly for privileged mtmsr test

9 months agowhoops forgot to update PC after trap in ISACaller
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 14:21:30 +0000 (15:21 +0100)]
whoops forgot to update PC after trap in ISACaller

9 months agomove priv test to above illegal/trap test
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 14:20:59 +0000 (15:20 +0100)]
move priv test to above illegal/trap test

9 months agocomments on IntegerData class
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 13:53:15 +0000 (14:53 +0100)]
comments on IntegerData class

9 months agoimport PipeContext not FPPipeContext
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 13:52:12 +0000 (14:52 +0100)]
import PipeContext not FPPipeContext

9 months agominor reorg on PowerDecoder2, use switch/case rather than if/or
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 13:38:46 +0000 (14:38 +0100)]
minor reorg on PowerDecoder2, use switch/case rather than if/or

9 months agocomments on SPRmap done in PowerDecode2
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 13:29:36 +0000 (14:29 +0100)]
comments on SPRmap done in PowerDecode2

9 months agocomments on SPRmap done in PowerDecode2
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 13:28:12 +0000 (14:28 +0100)]
comments on SPRmap done in PowerDecode2

9 months agouse case statement in PowerDecode2
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 13:21:23 +0000 (14:21 +0100)]
use case statement in PowerDecode2

9 months agoselect RA based on LDSTMode.update in PowerDecode2
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 13:13:28 +0000 (14:13 +0100)]
select RA based on LDSTMode.update in PowerDecode2

9 months agoadd cache cx to LDSTMode
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 13:10:30 +0000 (14:10 +0100)]
add cache cx to LDSTMode

9 months agoremove unused class XerBits
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 13:05:28 +0000 (14:05 +0100)]
remove unused class XerBits

9 months agouse Record Assert and also check muxid
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 10:49:52 +0000 (11:49 +0100)]
use Record Assert and also check muxid
see https://bugs.libre-soc.org/show_bug.cgi?id=429#c3

9 months agono need to check individual port members, just check the Record (dut.i.ctx.op)
Luke Kenneth Casson Leighton [Wed, 15 Jul 2020 10:18:27 +0000 (11:18 +0100)]
no need to check individual port members, just check the Record (dut.i.ctx.op)

9 months agocookie-cut setup from alu proof_main_stage.py
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 19:59:59 +0000 (20:59 +0100)]
cookie-cut setup from alu proof_main_stage.py

9 months agoreduce code size by using CompOpSubsetBase for ALU and Logical
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 19:54:21 +0000 (20:54 +0100)]
reduce code size by using CompOpSubsetBase for ALU and Logical

9 months agosplit out CompOpSubsetBase (meaning to do for a while)
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 19:43:22 +0000 (20:43 +0100)]
split out CompOpSubsetBase (meaning to do for a while)

9 months agoupdate docstrings
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 19:31:49 +0000 (20:31 +0100)]
update docstrings

9 months agoadding MSR.PR unit test intended to activate privileged trap
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 19:31:38 +0000 (20:31 +0100)]
adding MSR.PR unit test intended to activate privileged trap

9 months agoattempting to access self.msr directly
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 19:31:05 +0000 (20:31 +0100)]
attempting to access self.msr directly

9 months agoSPR: FV that should fail currently passes
Samuel A. Falvo II [Tue, 14 Jul 2020 19:17:45 +0000 (12:17 -0700)]
SPR: FV that should fail currently passes

WIP.  Cannot figure out why this is not failing.  Code review requested.

9 months agoset up masks for OP_RL* formal proof
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 15:06:29 +0000 (16:06 +0100)]
set up masks for OP_RL* formal proof

9 months agoadd priv instruction checking to ISACaller simulator
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 13:05:38 +0000 (14:05 +0100)]
add priv instruction checking to ISACaller simulator

9 months agoadd in privileged instruction decision-making in PowerDecode2
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 12:00:19 +0000 (13:00 +0100)]
add in privileged instruction decision-making in PowerDecode2

9 months agoadd MSR reading to issue FSM
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 11:43:53 +0000 (12:43 +0100)]
add MSR reading to issue FSM

9 months agocomments on PowerDecode2
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 11:00:54 +0000 (12:00 +0100)]
comments on PowerDecode2

9 months agoadd MSR to PowerDecoder2
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 10:47:05 +0000 (11:47 +0100)]
add MSR to PowerDecoder2

9 months agodisable cxxsim test
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 10:42:29 +0000 (11:42 +0100)]
disable cxxsim test

9 months agoattempting running cxxsim on ALU pipeline test
Luke Kenneth Casson Leighton [Tue, 14 Jul 2020 10:41:41 +0000 (11:41 +0100)]
attempting running cxxsim on ALU pipeline test

9 months agofirst attempt running cxxsim
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 22:59:34 +0000 (23:59 +0100)]
first attempt running cxxsim

9 months agofix path to nmigen-soc.git
Tobias Platen [Tue, 14 Jul 2020 05:32:42 +0000 (07:32 +0200)]
fix path to nmigen-soc.git

9 months agowhitespace
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 19:30:39 +0000 (20:30 +0100)]
whitespace

9 months agoformal proof of OP_EXTSWSLI
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 19:28:11 +0000 (20:28 +0100)]
formal proof of OP_EXTSWSLI

9 months agoquick test showing how left/right mask work
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 19:27:56 +0000 (20:27 +0100)]
quick test showing how left/right mask work

9 months agoadd nmigen-soc to .gitlab-ci.yml
Tobias Platen [Mon, 13 Jul 2020 18:13:03 +0000 (20:13 +0200)]
add nmigen-soc to .gitlab-ci.yml

9 months agoadd mtmsrd instruction and unit test
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 18:07:08 +0000 (19:07 +0100)]
add mtmsrd instruction and unit test

9 months agocomments
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 15:14:24 +0000 (16:14 +0100)]
comments

9 months agoattempting formal proof of OP_EXTSWSLI
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 15:07:09 +0000 (16:07 +0100)]
attempting formal proof of OP_EXTSWSLI

9 months agoreduce rotl module to one line (use bit_select)
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 14:13:21 +0000 (15:13 +0100)]
reduce rotl module to one line (use bit_select)

9 months agodocument rb as sh
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 13:55:04 +0000 (14:55 +0100)]
document rb as sh

9 months agoincrease range of test values for extswsli
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 13:45:09 +0000 (14:45 +0100)]
increase range of test values for extswsli

9 months agoadd EXTSWSLI "pass" to formal shift_rot proof
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 13:21:44 +0000 (14:21 +0100)]
add EXTSWSLI "pass" to formal shift_rot proof

9 months agoremove unneeded spec patching
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 13:18:14 +0000 (14:18 +0100)]
remove unneeded spec patching

9 months agoenable extswsli tests, fix spec-patching
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 13:17:34 +0000 (14:17 +0100)]
enable extswsli tests, fix spec-patching

9 months agoadd regression test, simulator is wrong
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 12:03:28 +0000 (13:03 +0100)]
add regression test, simulator is wrong

9 months agoadd simulator test against qemu for extswsli
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 12:02:22 +0000 (13:02 +0100)]
add simulator test against qemu for extswsli

9 months agofix read of sliced register
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 11:55:48 +0000 (12:55 +0100)]
fix read of sliced register

9 months agonot perfect but close enough: add read registers RA/S/B/C in parser
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 10:30:30 +0000 (11:30 +0100)]
not perfect but close enough: add read registers RA/S/B/C in parser

9 months agoadd extswsli unit test
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 10:27:08 +0000 (11:27 +0100)]
add extswsli unit test

9 months agoadd link to rotator, sign-extend mode OP_EXTSWSLI
Luke Kenneth Casson Leighton [Mon, 13 Jul 2020 10:02:15 +0000 (11:02 +0100)]
add link to rotator, sign-extend mode OP_EXTSWSLI

9 months agorename InternalOp to MicrOp
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 22:01:50 +0000 (23:01 +0100)]
rename InternalOp to MicrOp

9 months agoattempting to get test_trap_sim working, seems to switch mode
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 21:08:45 +0000 (22:08 +0100)]
attempting to get test_trap_sim working, seems to switch mode

9 months agosubmodule update
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:55:54 +0000 (21:55 +0100)]
submodule update

9 months agoadd OP_ATTN test back in
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:55:48 +0000 (21:55 +0100)]
add OP_ATTN test back in

9 months agoexit FSM when termination detected
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:48:36 +0000 (21:48 +0100)]
exit FSM when termination detected

9 months agocode-morph on core connect_instruction
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:32:44 +0000 (21:32 +0100)]
code-morph on core connect_instruction

9 months agomodify PowerDecoder to read LDSTMode correctly
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 20:04:24 +0000 (21:04 +0100)]
modify PowerDecoder to read LDSTMode correctly

9 months agochange CSV LD/ST update field to LDSTMode (support cix)
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 19:46:47 +0000 (20:46 +0100)]
change CSV LD/ST update field to LDSTMode (support cix)

9 months agoreturn unsigned int from binary reading
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 12:33:19 +0000 (13:33 +0100)]
return unsigned int from binary reading

9 months agoupdate submodule
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 12:13:09 +0000 (13:13 +0100)]
update submodule

9 months agomissed setting of link register on OP_BC in PowerDecoder2
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 10:46:22 +0000 (11:46 +0100)]
missed setting of link register on OP_BC in PowerDecoder2

9 months agomsb of instruction causing sign-overflow
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 04:10:10 +0000 (05:10 +0100)]
msb of instruction causing sign-overflow

9 months agoadd std and stdu ldst unit tests
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 03:46:31 +0000 (04:46 +0100)]
add std and stdu ldst unit tests

9 months agoupdate-mode request write signalled too early
Luke Kenneth Casson Leighton [Sun, 12 Jul 2020 03:46:04 +0000 (04:46 +0100)]
update-mode request write signalled too early

9 months agosort out core write latching: gate by busy, and use CompUnit dest output
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 22:48:46 +0000 (23:48 +0100)]
sort out core write latching: gate by busy, and use CompUnit dest output

9 months ago* clarifying core function unit enable
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 22:24:20 +0000 (23:24 +0100)]
* clarifying core function unit enable
* disabling wrflag based on fu busy
* NOP enabled when not stopped
g

9 months agoadd bigendian flag
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 22:13:44 +0000 (23:13 +0100)]
add bigendian flag

9 months agoadd endian
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 21:53:19 +0000 (22:53 +0100)]
add endian

9 months agofix spr setting, set endianness
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 21:50:37 +0000 (22:50 +0100)]
fix spr setting, set endianness

9 months agosigh spelling
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 21:48:58 +0000 (22:48 +0100)]
sigh spelling

9 months agoadd bigendian
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 21:46:10 +0000 (22:46 +0100)]
add bigendian

9 months agomore setting bigendian
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 20:06:51 +0000 (21:06 +0100)]
more setting bigendian

9 months agoadd bigendian mode to helloworld test
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 20:01:47 +0000 (21:01 +0100)]
add bigendian mode to helloworld test

9 months agosort out big/little endian startup on qemu
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 16:38:14 +0000 (17:38 +0100)]
sort out big/little endian startup on qemu

9 months agosorting out bigendian/littleendian including in qemu
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 16:34:07 +0000 (17:34 +0100)]
sorting out bigendian/littleendian including in qemu
qemu is a pain!

9 months agowhoops output trunc_divs not trunc_div
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 11:35:23 +0000 (12:35 +0100)]
whoops output trunc_divs not trunc_div

9 months agoadd random mulhd and mulld tests
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 11:02:29 +0000 (12:02 +0100)]
add random mulhd and mulld tests

9 months agoenable mul tests after sorting pseudo-code mul overflow
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 10:26:20 +0000 (11:26 +0100)]
enable mul tests after sorting pseudo-code mul overflow

9 months agospecial test for mul hw to cope with ignoring OE flag
Luke Kenneth Casson Leighton [Sat, 11 Jul 2020 10:08:48 +0000 (11:08 +0100)]
special test for mul hw to cope with ignoring OE flag