From 03fda1dbfc1fc690a2f3724c3d0b157252103947 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 4 May 2021 13:25:30 +0100 Subject: [PATCH] rename IntegerData to FUBaseData --- src/soc/fu/alu/pipe_data.py | 6 +++--- src/soc/fu/branch/pipe_data.py | 6 +++--- src/soc/fu/cr/pipe_data.py | 6 +++--- src/soc/fu/div/pipe_data.py | 6 +++--- src/soc/fu/ldst/pipe_data.py | 6 +++--- src/soc/fu/logical/pipe_data.py | 8 ++++---- src/soc/fu/mmu/pipe_data.py | 6 +++--- src/soc/fu/mul/pipe_data.py | 4 ++-- src/soc/fu/pipe_data.py | 6 +++--- src/soc/fu/shift_rot/pipe_data.py | 8 ++++---- src/soc/fu/spr/pipe_data.py | 6 +++--- src/soc/fu/trap/pipe_data.py | 6 +++--- 12 files changed, 37 insertions(+), 37 deletions(-) diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py index 71363049..7b133415 100644 --- a/src/soc/fu/alu/pipe_data.py +++ b/src/soc/fu/alu/pipe_data.py @@ -1,8 +1,8 @@ from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.fu.pipe_data import IntegerData, CommonPipeSpec +from soc.fu.pipe_data import FUBaseData, CommonPipeSpec -class ALUInputData(IntegerData): +class ALUInputData(FUBaseData): regspec = [('INT', 'ra', '0:63'), # RA ('INT', 'rb', '0:63'), # RB/immediate ('XER', 'xer_so', '32'), # XER bit 32: SO @@ -13,7 +13,7 @@ class ALUInputData(IntegerData): self.a, self.b = self.ra, self.rb -class ALUOutputData(IntegerData): +class ALUOutputData(FUBaseData): regspec = [('INT', 'o', '0:63'), ('CR', 'cr_a', '0:3'), ('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32 diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py index 9b62246f..a2f5bcf2 100644 --- a/src/soc/fu/branch/pipe_data.py +++ b/src/soc/fu/branch/pipe_data.py @@ -23,11 +23,11 @@ op_bctarl CR, TAR, CTR """ -from soc.fu.pipe_data import IntegerData, CommonPipeSpec +from soc.fu.pipe_data import FUBaseData, CommonPipeSpec from soc.fu.branch.br_input_record import CompBROpSubset # TODO: replace -class BranchInputData(IntegerData): +class BranchInputData(FUBaseData): # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR # this involves the *decode* unit selecting the register, based # on detecting the operand being bcctr, bclr or bctar @@ -44,7 +44,7 @@ class BranchInputData(IntegerData): self.cr = self.cr_a -class BranchOutputData(IntegerData): +class BranchOutputData(FUBaseData): regspec = [('FAST', 'fast1', '0:63'), ('FAST', 'fast2', '0:63'), ('STATE', 'nia', '0:63')] diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py index 06c7bfb7..edcad2e9 100644 --- a/src/soc/fu/cr/pipe_data.py +++ b/src/soc/fu/cr/pipe_data.py @@ -2,11 +2,11 @@ Links: * https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs """ -from soc.fu.pipe_data import IntegerData, CommonPipeSpec +from soc.fu.pipe_data import FUBaseData, CommonPipeSpec from soc.fu.cr.cr_input_record import CompCROpSubset -class CRInputData(IntegerData): +class CRInputData(FUBaseData): regspec = [('INT', 'ra', '0:63'), # 64 bit range ('INT', 'rb', '0:63'), # 64 bit range ('CR', 'full_cr', '0:31'), # 32 bit range @@ -19,7 +19,7 @@ class CRInputData(IntegerData): self.a, self.b = self.ra, self.rb -class CROutputData(IntegerData): +class CROutputData(FUBaseData): regspec = [('INT', 'o', '0:63'), # RA - 64 bit range ('CR', 'full_cr', '0:31'), # 32 bit range ('CR', 'cr_a', '0:3')] # 4 bit range diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py index c8279f42..4c70fdf1 100644 --- a/src/soc/fu/div/pipe_data.py +++ b/src/soc/fu/div/pipe_data.py @@ -1,6 +1,6 @@ import enum from nmigen import Signal, Const -from soc.fu.pipe_data import IntegerData +from soc.fu.pipe_data import FUBaseData from soc.fu.alu.pipe_data import CommonPipeSpec from soc.fu.logical.logical_input_record import CompLogicalOpSubset from ieee754.div_rem_sqrt_rsqrt.core import ( @@ -9,7 +9,7 @@ from ieee754.div_rem_sqrt_rsqrt.core import ( DivPipeCoreSetupStage, DivPipeCoreCalculateStage, DivPipeCoreFinalStage) -class DivInputData(IntegerData): +class DivInputData(FUBaseData): regspec = [('INT', 'ra', '0:63'), # RA ('INT', 'rb', '0:63'), # RB/immediate ('XER', 'xer_so', '32'), ] # XER bit 32: SO @@ -21,7 +21,7 @@ class DivInputData(IntegerData): # output stage shared between div and mul: like ALUOutputData but no CA/32 -class DivMulOutputData(IntegerData): +class DivMulOutputData(FUBaseData): regspec = [('INT', 'o', '0:63'), ('CR', 'cr_a', '0:3'), ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32 diff --git a/src/soc/fu/ldst/pipe_data.py b/src/soc/fu/ldst/pipe_data.py index a2f61e93..f356ab00 100644 --- a/src/soc/fu/ldst/pipe_data.py +++ b/src/soc/fu/ldst/pipe_data.py @@ -1,8 +1,8 @@ from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset -from soc.fu.pipe_data import IntegerData, CommonPipeSpec +from soc.fu.pipe_data import FUBaseData, CommonPipeSpec -class LDSTInputData(IntegerData): +class LDSTInputData(FUBaseData): regspec = [('INT', 'ra', '0:63'), # RA ('INT', 'rb', '0:63'), # RB/immediate ('INT', 'rc', '0:63'), # RC @@ -14,7 +14,7 @@ class LDSTInputData(IntegerData): self.rs = self.rc -class LDSTOutputData(IntegerData): +class LDSTOutputData(FUBaseData): regspec = [('INT', 'o', '0:63'), # RT ('INT', 'o1', '0:63'), # RA (effective address, update mode) # TODO, later ('CR', 'cr_a', '0:3'), diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py index 42a31ca1..3d9077aa 100644 --- a/src/soc/fu/logical/pipe_data.py +++ b/src/soc/fu/logical/pipe_data.py @@ -1,10 +1,10 @@ -from soc.fu.pipe_data import IntegerData +from soc.fu.pipe_data import FUBaseData from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec from soc.fu.logical.logical_input_record import CompLogicalOpSubset # input (and output) for logical initial stage (common input) -class LogicalInputData(IntegerData): +class LogicalInputData(FUBaseData): regspec = [('INT', 'ra', '0:63'), # RA ('INT', 'rb', '0:63'), # RB/immediate ('XER', 'xer_so', '32'), # bit0: so @@ -16,7 +16,7 @@ class LogicalInputData(IntegerData): # input to logical final stage (common output) -class LogicalOutputData(IntegerData): +class LogicalOutputData(FUBaseData): regspec = [('INT', 'o', '0:63'), # RT ('CR', 'cr_a', '0:3'), ('XER', 'xer_so', '32'), # bit0: so @@ -29,7 +29,7 @@ class LogicalOutputData(IntegerData): # output from logical final stage (common output) - note that XER.so # is *not* included (the only reason it's in the input is because of CR0) -class LogicalOutputDataFinal(IntegerData): +class LogicalOutputDataFinal(FUBaseData): regspec = [('INT', 'o', '0:63'), # RT ('CR', 'cr_a', '0:3'), ] diff --git a/src/soc/fu/mmu/pipe_data.py b/src/soc/fu/mmu/pipe_data.py index 1b7066d4..bc86e291 100644 --- a/src/soc/fu/mmu/pipe_data.py +++ b/src/soc/fu/mmu/pipe_data.py @@ -10,12 +10,12 @@ Links: * https://libre-soc.org/3d_gpu/architecture/regfile/ """ -from soc.fu.pipe_data import IntegerData +from soc.fu.pipe_data import FUBaseData from soc.fu.mmu.mmu_input_record import CompMMUOpSubset from soc.fu.alu.pipe_data import CommonPipeSpec -class MMUInputData(IntegerData): +class MMUInputData(FUBaseData): regspec = [('INT', 'ra', '0:63'), # RA ('INT', 'rb', '0:63'), # RB ('SPR', 'spr1', '0:63'), # MMU (slow) @@ -27,7 +27,7 @@ class MMUInputData(IntegerData): self.b = self.rb -class MMUOutputData(IntegerData): +class MMUOutputData(FUBaseData): regspec = [('INT', 'o', '0:63'), # RT ('SPR', 'spr1', '0:63'), # MMU (slow) ] diff --git a/src/soc/fu/mul/pipe_data.py b/src/soc/fu/mul/pipe_data.py index bb77c5ce..a55e80d1 100644 --- a/src/soc/fu/mul/pipe_data.py +++ b/src/soc/fu/mul/pipe_data.py @@ -1,5 +1,5 @@ from soc.fu.mul.mul_input_record import CompMULOpSubset -from soc.fu.pipe_data import IntegerData, CommonPipeSpec +from soc.fu.pipe_data import FUBaseData, CommonPipeSpec from soc.fu.div.pipe_data import DivInputData, DivMulOutputData from nmigen import Signal @@ -14,7 +14,7 @@ class MulIntermediateData(DivInputData): self.data.append(self.neg_res32) -class MulOutputData(IntegerData): +class MulOutputData(FUBaseData): regspec = [('INT', 'o', '0:128'), ('XER', 'xer_so', '32')] # XER bit 32: SO def __init__(self, pspec): diff --git a/src/soc/fu/pipe_data.py b/src/soc/fu/pipe_data.py index a9318eb5..1f780336 100644 --- a/src/soc/fu/pipe_data.py +++ b/src/soc/fu/pipe_data.py @@ -5,8 +5,8 @@ from openpower.decoder.power_decoder2 import Data from soc.fu.regspec import get_regspec_bitwidth -class IntegerData: - """IntegerData: base class for all pipeline data structures +class FUBaseData: + """FUBaseData: base class for all pipeline data structures see README.md for explanation of parameters and purpose. @@ -41,7 +41,7 @@ class IntegerData: (repr(self), repr(i), repr(self.data), repr(i.data)) for j in range(len(self.data)): assert type(self.data[j]) == type(i.data[j]), \ - "type mismatch in IntegerData %s %s" % \ + "type mismatch in FUBaseData %s %s" % \ (repr(self.data[j]), repr(i.data[j])) eqs.append(self.data[j].eq(i.data[j])) return eqs diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py index adafe1af..fd2336dd 100644 --- a/src/soc/fu/shift_rot/pipe_data.py +++ b/src/soc/fu/shift_rot/pipe_data.py @@ -1,9 +1,9 @@ from soc.fu.shift_rot.sr_input_record import CompSROpSubset -from soc.fu.pipe_data import IntegerData, CommonPipeSpec +from soc.fu.pipe_data import FUBaseData, CommonPipeSpec from soc.fu.alu.pipe_data import ALUOutputData -class ShiftRotInputData(IntegerData): +class ShiftRotInputData(FUBaseData): regspec = [('INT', 'ra', '0:63'), # RA ('INT', 'rb', '0:63'), # RB ('INT', 'rc', '0:63'), # RS @@ -16,7 +16,7 @@ class ShiftRotInputData(IntegerData): # input to shiftrot final stage (common output) -class ShiftRotOutputData(IntegerData): +class ShiftRotOutputData(FUBaseData): regspec = [('INT', 'o', '0:63'), # RT ('CR', 'cr_a', '0:3'), ('XER', 'xer_so', '32'), # bit0: so @@ -30,7 +30,7 @@ class ShiftRotOutputData(IntegerData): # output from shiftrot final stage (common output) - note that XER.so # is *not* included (the only reason it's in the input is because of CR0) -class ShiftRotOutputDataFinal(IntegerData): +class ShiftRotOutputDataFinal(FUBaseData): regspec = [('INT', 'o', '0:63'), # RT ('CR', 'cr_a', '0:3'), ('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32 diff --git a/src/soc/fu/spr/pipe_data.py b/src/soc/fu/spr/pipe_data.py index b66c35a0..bd0ed97e 100644 --- a/src/soc/fu/spr/pipe_data.py +++ b/src/soc/fu/spr/pipe_data.py @@ -10,12 +10,12 @@ Links: * https://libre-soc.org/3d_gpu/architecture/regfile/ """ -from soc.fu.pipe_data import IntegerData +from soc.fu.pipe_data import FUBaseData from soc.fu.spr.spr_input_record import CompSPROpSubset from soc.fu.alu.pipe_data import CommonPipeSpec -class SPRInputData(IntegerData): +class SPRInputData(FUBaseData): regspec = [('INT', 'ra', '0:63'), # RA ('SPR', 'spr1', '0:63'), # SPR (slow) ('FAST', 'fast1', '0:63'), # SPR (fast: LR, CTR etc) @@ -28,7 +28,7 @@ class SPRInputData(IntegerData): self.a = self.ra -class SPROutputData(IntegerData): +class SPROutputData(FUBaseData): regspec = [('INT', 'o', '0:63'), # RT ('SPR', 'spr1', '0:63'), # SPR (slow) ('FAST', 'fast1', '0:63'), # SPR (fast: LR, CTR etc) diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py index 863710c5..67b32b67 100644 --- a/src/soc/fu/trap/pipe_data.py +++ b/src/soc/fu/trap/pipe_data.py @@ -1,8 +1,8 @@ -from soc.fu.pipe_data import IntegerData, CommonPipeSpec +from soc.fu.pipe_data import FUBaseData, CommonPipeSpec from soc.fu.trap.trap_input_record import CompTrapOpSubset -class TrapInputData(IntegerData): +class TrapInputData(FUBaseData): regspec = [('INT', 'ra', '0:63'), # RA ('INT', 'rb', '0:63'), # RB/immediate ('FAST', 'fast1', '0:63'), # SRR0 @@ -17,7 +17,7 @@ class TrapInputData(IntegerData): self.a, self.b = self.ra, self.rb -class TrapOutputData(IntegerData): +class TrapOutputData(FUBaseData): regspec = [('INT', 'o', '0:63'), # RA ('FAST', 'fast1', '0:63'), # SRR0 SPR ('FAST', 'fast2', '0:63'), # SRR1 SPR -- 2.30.2