From 13380310509b737cf3ba8be2c290142e2511671f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 15 Jul 2020 15:21:30 +0100 Subject: [PATCH] whoops forgot to update PC after trap in ISACaller --- src/soc/decoder/isa/caller.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index aea6d035..f2ba7b28 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -264,6 +264,7 @@ class ISACaller: assert self.respect_pc == False, "instructions required to honor pc" print ("ISACaller insns", respect_pc, initial_insns, disassembly) + print ("ISACaller initial_msr", initial_msr) # "fake program counter" mode (for unit testing) self.fake_pc = 0 @@ -577,10 +578,13 @@ class ISACaller: MicrOp.OP_MTSPR.value] and spr_msb: instr_is_privileged = True - print ("is priv", instr_is_privileged, self.msr[63-MSR.PR]) + print ("is priv", instr_is_privileged, hex(self.msr.value), + self.msr[63-MSR.PR]) # check MSR priv bit and whether op is privileged: if so, throw trap if instr_is_privileged and self.msr[63-MSR.PR] == 1: self.TRAP(0x700, PI.PRIV) + self.namespace['NIA'] = self.trap_nia + self.pc.update(self.namespace) return # check halted condition -- 2.30.2