From 237d4f455ae825941b0542819c02fdc87585808a Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sat, 4 Apr 2020 16:23:01 -0400 Subject: [PATCH] Sorta working add instruction --- src/soc/decoder/isa/caller.py | 40 ++++++++++++++++-------------- src/soc/decoder/isa/test_caller.py | 29 ++++++++++++++-------- src/soc/decoder/pseudo/pywriter.py | 14 +++-------- 3 files changed, 44 insertions(+), 39 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index f177042d..a75dc3fa 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -1,6 +1,15 @@ from functools import wraps +from soc.decoder.orderedset import OrderedSet from soc.decoder.selectable_int import SelectableInt, selectconcat +def create_args(reglist, extra=None): + args = OrderedSet() + for reg in reglist: + args.add(reg) + args = list(args) + if extra: + args = [extra] + args + return args class Mem: @@ -64,17 +73,28 @@ class ISACaller: 'MEM': self.mem, 'memassign': self.memassign } + self.decoder = decoder2 def memassign(self, ea, sz, val): self.mem.memassign(ea, sz, val) def call(self, name): function, read_regs, uninit_regs, write_regs = self.instrs[name] + input_names = create_args(read_regs | uninit_regs) + print(input_names) + inputs = [] + for name in input_names: + regnum = yield getattr(self.decoder, name) + print(regnum) + inputs.append(self.gpr(regnum)) + print(inputs) + results = function(self, *inputs) + print(results) -def inject(context): +def inject(): """ Decorator factory. """ def variable_injector(func): @wraps(func) @@ -84,6 +104,7 @@ def inject(context): except AttributeError: func_globals = func.func_globals # Earlier versions. + context = args[0].namespace saved_values = func_globals.copy() # Shallow copy of dict. func_globals.update(context) @@ -99,20 +120,3 @@ def inject(context): return variable_injector -if __name__ == '__main__': - d = {'1': 1} - namespace = {'a': 5, 'b': 3, 'd': d} - - @inject(namespace) - def test(): - print (globals()) - print('a:', a) - print('b:', b) - print('d1:', d['1']) - d[2] = 5 - - return locals() - - test() - - print (namespace) diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index 9d693a42..b958795c 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -15,17 +15,23 @@ from soc.decoder.orderedset import OrderedSet class fixedarith(ISACaller): - @inject + @inject() def op_addi(self, RA): if RA == 0: - RT = EXTS(SI) + RT = SI else: - RT = RA + EXTS(SI) + RT = RA + SI + return (RT,) + @inject() + def op_add(self, RA, RB): + RT = RA + RB return (RT,) instrs = {} instrs['addi'] = (op_addi, OrderedSet(['RA']), OrderedSet(), OrderedSet(['RT'])) + instrs['add'] = (op_add, OrderedSet(['RA', 'RB']), + OrderedSet(), OrderedSet(['RT'])) @@ -36,13 +42,13 @@ class Register: class DecoderTestCase(FHDLTestCase): - def run_tst(self, generator): + def run_tst(self, generator, initial_regs): m = Module() comb = m.d.comb instruction = Signal(32) pdecode = create_pdecode() - simulator = fixedarith(pdecode, [0] * 32) + simulator = fixedarith(pdecode, initial_regs) m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) comb += pdecode2.dec.raw_opcode_in.eq(instruction) @@ -68,13 +74,16 @@ class DecoderTestCase(FHDLTestCase): sim.run() return simulator - def test_addi(self): - lst = ["addi 1, 0, 0x1234"] + def test_add(self): + lst = ["add 1, 3, 2"] + initial_regs = [0] * 32 + initial_regs[3] = 0x1234 + initial_regs[2] = 0x4321 with Program(lst) as program: - self.run_test_program(program) + self.run_test_program(program, initial_regs) - def run_test_program(self, prog): - simulator = self.run_tst(prog) + def run_test_program(self, prog, initial_regs): + simulator = self.run_tst(prog, initial_regs) print(simulator.gpr) if __name__ == "__main__": diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py index 2f5cd3a4..a9f58acd 100644 --- a/src/soc/decoder/pseudo/pywriter.py +++ b/src/soc/decoder/pseudo/pywriter.py @@ -4,21 +4,13 @@ import os from soc.decoder.pseudo.pagereader import ISA from soc.decoder.power_pseudo import convert_to_python from soc.decoder.orderedset import OrderedSet +from soc.decoder.isa.caller import create_args def get_isasrc_dir(): fdir = os.path.abspath(os.path.dirname(__file__)) fdir = os.path.split(fdir)[0] return os.path.join(fdir, "isa") -def create_args(reglist, extra=None): - args = OrderedSet() - for reg in reglist: - args.add(reg) - args = list(args) - if extra: - args = [extra] + args - return ', '.join(args) - header = """\ # auto-generated by pywriter.py, do not edit or commit @@ -53,9 +45,9 @@ class PyISAWriter(ISA): pycode, rused = convert_to_python(pcode) # create list of arguments to call regs = list(rused['read_regs']) + list(rused['uninit_regs']) - args = create_args(regs, 'self') + args = ', '.join(create_args(regs, 'self')) # create list of arguments to return - retargs = create_args(rused['write_regs']) + retargs = ', '.join(create_args(rused['write_regs'])) # write out function. pre-pend "op_" because some instrs are # also python keywords (cmp). also replace "." with "_" op_fname ="op_%s" % page.replace(".", "_") -- 2.30.2