From 407f41392acaec1902e75cde2953c9c8f5d0692c Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 20 May 2020 19:10:53 +0100
Subject: [PATCH] add register specs to pipeline in/out so that they can be
 used to connect up Function Units to regfiles

---
 src/soc/fu/alu/pipe_data.py       |  9 +++++++++
 src/soc/fu/branch/pipe_data.py    |  7 +++++++
 src/soc/fu/cr/pipe_data.py        |  8 ++++++--
 src/soc/fu/logical/pipe_data.py   |  4 ++++
 src/soc/fu/shift_rot/pipe_data.py |  5 +++++
 src/soc/fu/trap/pipe_data.py      | 12 ++++++++++--
 6 files changed, 41 insertions(+), 4 deletions(-)

diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index 0d299ef4..3d64de89 100644
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -21,6 +21,10 @@ class IntegerData:
 
 
 class ALUInputData(IntegerData):
+    regspec = [('INT', 'a', '0:63'),
+               ('INT', 'b', '0:63'),
+               ('XER', 'xer_so', '32'),
+               ('XER', 'xer_ca', '34,45')]
     def __init__(self, pspec):
         super().__init__(pspec)
         self.a = Signal(64, reset_less=True) # RA
@@ -47,6 +51,11 @@ class ALUInputData(IntegerData):
 # https://bugs.libre-soc.org/show_bug.cgi?id=305#c19
 
 class ALUOutputData(IntegerData):
+    regspec = [('INT', 'o', '0:63'),
+               ('CR', 'cr0', '0:3'),
+               ('XER', 'xer_ca', '34,45'),
+               ('XER', 'xer_ov', '33,44'),
+               ('XER', 'xer_so', '32')]
     def __init__(self, pspec):
         super().__init__(pspec)
         self.o = Signal(64, reset_less=True, name="stage_o")
diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index 2772236e..05d3a931 100644
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -30,6 +30,10 @@ from soc.fu.alu.pipe_data import IntegerData
 
 
 class BranchInputData(IntegerData):
+    regspec = [('SPR', 'spr1', '0:63'),
+               ('SPR', 'spr2', '0:63'),
+               ('CR', 'cr', '32'),
+               ('PC', 'cia', '0:63')]
     def __init__(self, pspec):
         super().__init__(pspec)
         # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
@@ -59,6 +63,9 @@ class BranchInputData(IntegerData):
 
 
 class BranchOutputData(IntegerData):
+    regspec = [('SPR', 'spr1', '0:63'),
+               ('SPR', 'spr2', '0:63'),
+               ('PC', 'cia', '0:63')]
     def __init__(self, pspec):
         super().__init__(pspec)
         self.spr1 = Data(64, name="spr1")
diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index 107a340e..2b240263 100644
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -4,10 +4,12 @@ from soc.fu.alu.pipe_data import IntegerData
 
 
 class CRInputData(IntegerData):
+    regspec = [('INT', 'a', '0:63'),
+               ('CR', 'cr', '32')]
     def __init__(self, pspec):
         super().__init__(pspec)
         self.a = Signal(64, reset_less=True) # RA
-        self.cr = Signal(64, reset_less=True) # CR in
+        self.cr = Signal(32, reset_less=True) # CR in
 
     def __iter__(self):
         yield from super().__iter__()
@@ -20,10 +22,12 @@ class CRInputData(IntegerData):
                       self.cr.eq(i.cr)]
 
 class CROutputData(IntegerData):
+    regspec = [('INT', 'o', '0:63'),
+               ('CR', 'cr', '32')]
     def __init__(self, pspec):
         super().__init__(pspec)
         self.o = Signal(64, reset_less=True) # RA
-        self.cr = Signal(64, reset_less=True) # CR in
+        self.cr = Signal(32, reset_less=True) # CR in
 
     def __iter__(self):
         yield from super().__iter__()
diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index aed78689..9ed7252f 100644
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -4,6 +4,10 @@ from soc.fu.alu.pipe_data import IntegerData
 
 
 class LogicalInputData(IntegerData):
+    regspec = [('INT', 'a', '0:63'),
+               ('INT', 'rb', '0:63'),
+               ('XER', 'xer_so', '32'),
+               ('XER', 'xer_ca', '34,45')]
     def __init__(self, pspec):
         super().__init__(pspec)
         self.a = Signal(64, reset_less=True) # RA
diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index 0c0e6cab..eed4dffe 100644
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -6,6 +6,11 @@ from soc.fu.alu.pipe_data import IntegerData
 
 
 class ShiftRotInputData(IntegerData):
+    regspec = [('INT', 'ra', '0:63'),
+               ('INT', 'rs', '0:63'),
+               ('INT', 'rb', '0:63'),
+               ('XER', 'xer_so', '32'),
+               ('XER', 'xer_ca', '34,45')]
     def __init__(self, pspec):
         super().__init__(pspec)
         self.ra = Signal(64, reset_less=True) # RA
diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py
index ebe34fd6..033f7bb1 100644
--- a/src/soc/fu/trap/pipe_data.py
+++ b/src/soc/fu/trap/pipe_data.py
@@ -5,6 +5,10 @@ from soc.decoder.power_decoder2 import Data
 
 
 class TrapInputData(IntegerData):
+    regspec = [('INT', 'a', '0:63'),
+               ('INT', 'b', '0:63'),
+               ('PC', 'cia', '0:63'),
+               ('MSR', 'msr', '0:63')]
     def __init__(self, pspec):
         super().__init__(pspec)
         self.a = Signal(64, reset_less=True)  # RA
@@ -26,12 +30,16 @@ class TrapInputData(IntegerData):
 
 
 class TrapOutputData(IntegerData):
+    regspec = [('SPR', 'srr0', '0:63'),
+               ('SPR', 'srr1', '0:63'),
+               ('PC', 'nia', '0:63'),
+               ('MSR', 'msr', '0:63')]
     def __init__(self, pspec):
         super().__init__(pspec)
-        self.nia = Data(64, name="nia") # NIA (Next PC)
-        self.msr = Signal(64, reset_less=True) # MSR
         self.srr0 = Data(64, name="srr0") # SRR0 SPR
         self.srr1 = Data(64, name="srr1") # SRR1 SPR
+        self.nia = Data(64, name="nia") # NIA (Next PC)
+        self.msr = Signal(64, reset_less=True) # MSR
 
     def __iter__(self):
         yield from super().__iter__()
-- 
2.30.2