From 52215e08906096690085424fb4302c694f0793df Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 20 Jun 2020 13:16:00 +0100 Subject: [PATCH] add asserts to check data output is correct --- src/soc/bus/test/test_sram_wishbone.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/soc/bus/test/test_sram_wishbone.py b/src/soc/bus/test/test_sram_wishbone.py index 0a25314a..dfebb3b8 100644 --- a/src/soc/bus/test/test_sram_wishbone.py +++ b/src/soc/bus/test/test_sram_wishbone.py @@ -54,10 +54,15 @@ def process(): # see sync_behaviors.py # for why we need Settle() + # debug print the bus address/data yield Settle() yield from print_sig(sram.bus.adr) yield from print_sig(sram.bus.dat_r, "h") + # check the result + data = yield sram.bus.dat_r + assert data == 0 + # set necessary signal to read bus # at address 4 yield sram.bus.we.eq(0) @@ -66,10 +71,17 @@ def process(): yield sram.bus.stb.eq(1) yield + # see sync_behaviors.py + # for why we need Settle() + # debug print the bus address/data yield Settle() yield from print_sig(sram.bus.adr) yield from print_sig(sram.bus.dat_r, "h") + # check the result + data = yield sram.bus.dat_r + assert data == 0xdeadbeef + # disable signals yield sram.bus.cyc.eq(0) yield sram.bus.stb.eq(0) -- 2.30.2