From 8a8656cda656db9cd5ed66537f03dda185b2b4f6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 21 Jul 2020 19:36:39 +0100 Subject: [PATCH 1/1] convert branch pipeline to use msr/cia as immediates --- src/soc/decoder/isa/caller.py | 2 ++ src/soc/fu/branch/br_input_record.py | 3 ++- src/soc/fu/branch/main_stage.py | 2 +- src/soc/fu/branch/pipe_data.py | 2 +- src/soc/fu/branch/test/test_pipe_caller.py | 25 ++++++++++++++++------ src/soc/fu/spr/test/test_pipe_caller.py | 1 + 6 files changed, 26 insertions(+), 9 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 85b8aa5c..fce89a44 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -500,6 +500,8 @@ class ISACaller: yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) yield self.dec2.dec.bigendian.eq(self.bigendian) + yield self.dec2.msr.eq(self.msr.value) + yield self.dec2.cia.eq(pc) def execute_one(self): """execute one instruction diff --git a/src/soc/fu/branch/br_input_record.py b/src/soc/fu/branch/br_input_record.py index 697b8fb4..2e0a1e1e 100644 --- a/src/soc/fu/branch/br_input_record.py +++ b/src/soc/fu/branch/br_input_record.py @@ -12,7 +12,8 @@ class CompBROpSubset(CompOpSubsetBase): grab subsets. """ def __init__(self, name=None): - layout = (('insn_type', MicrOp), + layout = (('cia', 64), # PC "state" + ('insn_type', MicrOp), ('fn_unit', Function), ('insn', 32), ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py index d6425f03..39631afd 100644 --- a/src/soc/fu/branch/main_stage.py +++ b/src/soc/fu/branch/main_stage.py @@ -72,7 +72,7 @@ class BranchMainStage(PipeModBase): comb = m.d.comb op = self.i.ctx.op lk = op.lk # see PowerDecode2 as to why this is done - cr, cia, ctr, fast1 = self.i.cr, self.i.cia, self.i.ctr, self.i.fast1 + cr, cia, ctr, fast1 = self.i.cr, op.cia, self.i.ctr, self.i.fast1 fast2 = self.i.fast2 nia_o, lr_o, ctr_o = self.o.nia, self.o.lr, self.o.ctr diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py index fb01775d..9bbe0552 100644 --- a/src/soc/fu/branch/pipe_data.py +++ b/src/soc/fu/branch/pipe_data.py @@ -34,7 +34,7 @@ class BranchInputData(IntegerData): regspec = [('FAST', 'fast1', '0:63'), # see table above, SPR1 ('FAST', 'fast2', '0:63'), # see table above, SPR2 ('CR', 'cr_a', '0:3'), # Condition Register(s) CR0-7 - ('FAST', 'cia', '0:63')] # Current Instruction Address + ] def __init__(self, pspec): super().__init__(pspec, False) diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index 70796198..b29d8a45 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -55,7 +55,7 @@ def get_cu_inputs(dec2, sim): res = {} # CIA (PC) - res['cia'] = sim.pc.CIA.value + #res['cia'] = sim.pc.CIA.value yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) yield from ALUHelpers.get_sim_fast_spr2(res, sim, dec2) @@ -77,6 +77,13 @@ class BranchTestCase(FHDLTestCase): initial_regs, initial_sprs, initial_cr) self.test_data.append(tc) + def test_0_regression_unconditional(self): + for i in range(2): + imm = random.randrange(-1<<23, (1<<23)-1) * 4 + lst = [f"bl {imm}"] + initial_regs = [0] * 32 + self.run_tst_program(Program(lst, bigendian), initial_regs) + def test_unconditional(self): choices = ["b", "ba", "bl", "bla"] for i in range(20): @@ -174,7 +181,9 @@ class TestRunner(FHDLTestCase): gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) - index = (simulator.pc.CIA.value - initial_cia)//4 + pc = simulator.pc.CIA.value + msr = simulator.msr.value + index = (pc - initial_cia)//4 while index < len(instructions) and index >= 0: print(index) ins, code = instructions[index] @@ -184,6 +193,8 @@ class TestRunner(FHDLTestCase): # ask the decoder to decode this binary data (endian'd) yield pdecode2.dec.bigendian.eq(bigendian) # little / big? + yield pdecode2.msr.eq(msr) # set MSR in pdecode2 + yield pdecode2.cia.eq(pc) # set PC in pdecode2 yield instruction.eq(ins) # raw binary instr. # note, here, the op will need further decoding in order # to set the correct SPRs on SPR1/2/3. op_bc* require @@ -192,6 +203,8 @@ class TestRunner(FHDLTestCase): # if op_sc*, op_rf* and op_hrfid are to be added here # then additional op-decoding is required, accordingly yield Settle() + lk = yield pdecode2.e.do.lk + print ("lk:", lk) yield from self.set_inputs(branch, pdecode2, simulator) fn_unit = yield pdecode2.e.do.fn_unit self.assertEqual(fn_unit, Function.BRANCH.value, code) @@ -200,14 +213,15 @@ class TestRunner(FHDLTestCase): opname = code.split(' ')[0] prev_nia = simulator.pc.NIA.value yield from simulator.call(opname) - index = (simulator.pc.CIA.value - initial_cia)//4 + pc = simulator.pc.CIA.value + msr = simulator.msr.value + index = (pc - initial_cia)//4 yield from self.assert_outputs(branch, pdecode2, simulator, prev_nia, code) sim.add_sync_process(process) - with sim.write_vcd("simulator.vcd", "simulator.gtkw", - traces=[]): + with sim.write_vcd("branch_simulator.vcd"): sim.run() def assert_outputs(self, branch, dec2, sim, prev_nia, code): @@ -234,7 +248,6 @@ class TestRunner(FHDLTestCase): inp = yield from get_cu_inputs(dec2, sim) - yield from ALUHelpers.set_cia(branch, dec2, inp) yield from ALUHelpers.set_fast_spr1(branch, dec2, inp) yield from ALUHelpers.set_fast_spr2(branch, dec2, inp) yield from ALUHelpers.set_cr_a(branch, dec2, inp) diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py index 3ba1ac3d..e20c55e0 100644 --- a/src/soc/fu/spr/test/test_pipe_caller.py +++ b/src/soc/fu/spr/test/test_pipe_caller.py @@ -210,6 +210,7 @@ class TestRunner(FHDLTestCase): # ask the decoder to decode this binary data (endian'd) yield pdecode2.dec.bigendian.eq(bigendian) # little / big? yield pdecode2.msr.eq(msr) # set MSR in pdecode2 + yield pdecode2.cia.eq(pc) # set PC in pdecode2 yield instruction.eq(ins) # raw binary instr. yield Settle() -- 2.30.2