From 91b360fca92401f8d54016a02b013f38383aed56 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 22 Oct 2020 16:50:37 +0100 Subject: [PATCH] add detection and disable of Instruction Wishbone based on JTAG command --- src/soc/minerva/units/fetch.py | 68 +++++++++++++++++++--------------- 1 file changed, 39 insertions(+), 29 deletions(-) diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py index b3e536b0..a1f14b3d 100644 --- a/src/soc/minerva/units/fetch.py +++ b/src/soc/minerva/units/fetch.py @@ -34,6 +34,14 @@ class FetchUnitInterface: self.f_fetch_err_o = Signal() self.f_badaddr_o = Signal(bad_wid) + # detect whether the wishbone bus is enabled / disabled + if (hasattr(pspec, "wb_icache_en") and + isinstance(pspec.wb_icache_en, Signal)): + self.jtag_en = pspec.wb_icache_en + else: + self.jtag_en = Const(1, 1) # permanently on + + def __iter__(self): yield self.a_pc_i yield self.a_stall_i @@ -56,40 +64,42 @@ class BareFetchUnit(FetchUnitInterface, Elaboratable): def elaborate(self, platform): m = Module() - ibus_rdata = Signal.like(self.ibus.dat_r) - with m.If(self.ibus.cyc): - with m.If(self.ibus.ack | self.ibus.err | ~self.f_valid_i): + with m.If(self.jtag_en): # for safety, JTAG can completely disable WB + + ibus_rdata = Signal.like(self.ibus.dat_r) + with m.If(self.ibus.cyc): + with m.If(self.ibus.ack | self.ibus.err | ~self.f_valid_i): + m.d.sync += [ + self.ibus.cyc.eq(0), + self.ibus.stb.eq(0), + self.ibus.sel.eq(0), + ibus_rdata.eq(self.ibus.dat_r) + ] + with m.Elif(self.a_valid_i & ~self.a_stall_i): m.d.sync += [ - self.ibus.cyc.eq(0), - self.ibus.stb.eq(0), - self.ibus.sel.eq(0), - ibus_rdata.eq(self.ibus.dat_r) + self.ibus.adr.eq(self.a_pc_i[self.adr_lsbs:]), + self.ibus.cyc.eq(1), + self.ibus.stb.eq(1), + self.ibus.sel.eq((1<<(1<