From 9594bf2a065c4544049769d77475d086e4ff3186 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Wed, 13 May 2020 16:22:44 -0400 Subject: [PATCH] Fix weirdness with rldicl and friends in test_caller.py --- src/soc/decoder/isa/fixedshift.patch | 56 +++++++++++++++++++++++++++- src/soc/decoder/isa/test_caller.py | 8 ++++ 2 files changed, 62 insertions(+), 2 deletions(-) diff --git a/src/soc/decoder/isa/fixedshift.patch b/src/soc/decoder/isa/fixedshift.patch index 42fc2ac6..442f9f91 100644 --- a/src/soc/decoder/isa/fixedshift.patch +++ b/src/soc/decoder/isa/fixedshift.patch @@ -1,5 +1,5 @@ --- fixedshift.py.orig 2020-05-11 10:20:55.781417649 -0400 -+++ fixedshift.py 2020-05-13 14:02:01.147691354 -0400 ++++ fixedshift.py 2020-05-13 16:22:30.896089413 -0400 @@ -13,7 +13,7 @@ def op_rlwinm(self, RS): n = SH @@ -45,7 +45,7 @@ RA = r & m | RA & ~m return (RA,) -@@ -53,7 +53,7 @@ +@@ -53,13 +53,13 @@ def op_rlwimi_(self, RS, RA): n = SH r = ROTL32(RS[32:64], n) @@ -54,6 +54,58 @@ RA = r & m | RA & ~m return (RA,) + @inject() + def op_rldicl(self, RS): +- n = concat(sh[5], sh[0:5]) ++ n = sh + r = ROTL64(RS, n) + b = concat(mb[5], mb[0:5]) + m = MASK(b, 63) +@@ -68,7 +68,7 @@ + + @inject() + def op_rldicl_(self, RS): +- n = concat(sh[5], sh[0:5]) ++ n = sh + r = ROTL64(RS, n) + b = concat(mb[5], mb[0:5]) + m = MASK(b, 63) +@@ -77,7 +77,7 @@ + + @inject() + def op_rldicr(self, RS): +- n = concat(sh[5], sh[0:5]) ++ n = sh + r = ROTL64(RS, n) + e = concat(me[5], me[0:5]) + m = MASK(0, e) +@@ -86,7 +86,7 @@ + + @inject() + def op_rldicr_(self, RS): +- n = concat(sh[5], sh[0:5]) ++ n = sh + r = ROTL64(RS, n) + e = concat(me[5], me[0:5]) + m = MASK(0, e) +@@ -95,7 +95,7 @@ + + @inject() + def op_rldic(self, RS): +- n = concat(sh[5], sh[0:5]) ++ n = sh + r = ROTL64(RS, n) + b = concat(mb[5], mb[0:5]) + m = MASK(b, ~n) +@@ -104,7 +104,7 @@ + + @inject() + def op_rldic_(self, RS): +- n = concat(sh[5], sh[0:5]) ++ n = sh + r = ROTL64(RS, n) + b = concat(mb[5], mb[0:5]) + m = MASK(b, ~n) @@ -168,9 +168,9 @@ @inject() def op_slw(self, RB, RS): diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index 239e1d46..4050fab3 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -222,6 +222,14 @@ class DecoderTestCase(FHDLTestCase): sim = self.run_tst_program(program, initial_regs) self.assertEqual(sim.gpr(3), SelectableInt(0xd5b7ddfbd4345dfb, 64)) + def test_rldic(self): + lst = ["rldic 3, 1, 5, 20"] + initial_regs = [0] * 32 + initial_regs[1] = 0xdeadbeefcafec0de + with Program(lst) as program: + sim = self.run_tst_program(program, initial_regs) + self.assertEqual(sim.gpr(3), SelectableInt(0xdf95fd81bc0, 64)) + def test_mtcrf(self): for i in range(4): # 0x76540000 gives expected (3+4) (2+4) (1+4) (0+4) for -- 2.30.2