From 98b2ca3b6fc9d82ec34ab32847e719023aae134b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 9 May 2021 20:14:28 +0100 Subject: [PATCH] add comments in LoadStore1 --- src/soc/fu/ldst/loadstore.py | 6 ++++++ src/soc/simple/test/test_issuer_mmu.py | 8 ++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index a9dbaba3..f3544b08 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -187,6 +187,7 @@ class LoadStore1(PortInterfaceBase): pass with m.Case(State.COMPLETE): pass + # microwatt: only if State.ACK_WAIZ with m.If(d_out.error): with m.If(d_out.cache_paradox): @@ -242,6 +243,11 @@ class LoadStore1(PortInterfaceBase): with m.Else(): m.d.sync += d_in.data.eq(0) + # this must move into the FSM, conditionally noticing that + # the "blip" comes from self.d_validblip. + # task 1: look up in dcache + # task 2: if dcache fails, look up in MMU. + # do **NOT** confuse the two. m.d.comb += d_in.load.eq(self.load) m.d.comb += d_in.byte_sel.eq(self.byte_sel) m.d.comb += d_in.addr.eq(self.addr) diff --git a/src/soc/simple/test/test_issuer_mmu.py b/src/soc/simple/test/test_issuer_mmu.py index b24b73eb..4bf4d37a 100644 --- a/src/soc/simple/test/test_issuer_mmu.py +++ b/src/soc/simple/test/test_issuer_mmu.py @@ -46,12 +46,12 @@ if __name__ == "__main__": # microwatt_mmu=True)) # LD/ST tests should all still work - #suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64, - # microwatt_mmu=True)) + suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64, + microwatt_mmu=True)) # LD/ST exception cases - suite.addTest(TestRunner(LDSTExceptionTestCase().test_data, svp64=svp64, - microwatt_mmu=True)) + #suite.addTest(TestRunner(LDSTExceptionTestCase().test_data, svp64=svp64, + # microwatt_mmu=True)) runner = unittest.TextTestRunner() runner.run(suite) -- 2.30.2