From b92b8d7f87b8700d879413579d996690d0fda17f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 12 Jul 2020 23:01:50 +0100 Subject: [PATCH] rename InternalOp to MicrOp --- src/soc/decoder/decode2execute1.py | 4 +- src/soc/decoder/formal/proof_decoder.py | 6 +- src/soc/decoder/formal/proof_decoder2.py | 10 +-- src/soc/decoder/isa/caller.py | 10 +-- src/soc/decoder/power_decoder.py | 6 +- src/soc/decoder/power_decoder2.py | 58 ++++++------- src/soc/decoder/power_enums.py | 2 +- src/soc/decoder/test/test_decoder_gas.py | 82 +++++++++---------- src/soc/decoder/test/test_power_decoder.py | 6 +- src/soc/experiment/alu_hier.py | 34 ++++---- src/soc/experiment/compalu.py | 8 +- src/soc/experiment/compldst_multi.py | 10 +-- src/soc/experiment/l0_cache.py | 2 +- src/soc/experiment/score6600.py | 10 +-- src/soc/experiment/score6600_multi.py | 10 +-- src/soc/experiment/sim.py | 6 +- src/soc/experiment/test/test_compalu_multi.py | 20 ++--- src/soc/fu/alu/alu_input_record.py | 4 +- src/soc/fu/alu/formal/proof_input_stage.py | 2 +- src/soc/fu/alu/formal/proof_main_stage.py | 10 +-- src/soc/fu/alu/formal/proof_output_stage.py | 6 +- src/soc/fu/alu/main_stage.py | 14 ++-- src/soc/fu/alu/output_stage.py | 2 +- src/soc/fu/alu/test/test_pipe_caller.py | 2 +- src/soc/fu/branch/br_input_record.py | 4 +- src/soc/fu/branch/formal/proof_input_stage.py | 4 +- src/soc/fu/branch/formal/proof_main_stage.py | 8 +- src/soc/fu/branch/main_stage.py | 10 +-- src/soc/fu/branch/test/test_pipe_caller.py | 2 +- src/soc/fu/common_input_stage.py | 2 +- src/soc/fu/common_output_stage.py | 6 +- src/soc/fu/compunits/formal/test_compunit.py | 4 +- src/soc/fu/cr/cr_input_record.py | 4 +- src/soc/fu/cr/formal/proof_main_stage.py | 22 ++--- src/soc/fu/cr/main_stage.py | 14 ++-- src/soc/fu/div/core_stages.py | 2 +- src/soc/fu/div/formal/proof_main_stage.py | 14 ++-- src/soc/fu/div/output_stage.py | 8 +- src/soc/fu/div/setup_stage.py | 10 +-- src/soc/fu/div/test/test_pipe_caller.py | 2 +- src/soc/fu/ldst/ldst_input_record.py | 4 +- src/soc/fu/ldst/test/test_pipe_caller.py | 2 +- .../fu/logical/formal/proof_input_stage.py | 4 +- src/soc/fu/logical/formal/proof_main_stage.py | 18 ++-- src/soc/fu/logical/logical_input_record.py | 4 +- src/soc/fu/logical/main_stage.py | 18 ++-- src/soc/fu/logical/output_stage.py | 2 +- src/soc/fu/mul/formal/proof_main_stage.py | 6 +- src/soc/fu/mul/mul_input_record.py | 4 +- src/soc/fu/mul/post_stage.py | 6 +- src/soc/fu/mul/test/test_pipe_caller.py | 2 +- .../fu/shift_rot/formal/proof_main_stage.py | 12 +-- src/soc/fu/shift_rot/main_stage.py | 12 +-- src/soc/fu/shift_rot/sr_input_record.py | 4 +- src/soc/fu/spr/main_stage.py | 6 +- src/soc/fu/spr/spr_input_record.py | 4 +- src/soc/fu/spr/test/test_pipe_caller.py | 2 +- src/soc/fu/trap/main_stage.py | 14 ++-- src/soc/fu/trap/test/test_pipe_caller.py | 2 +- src/soc/fu/trap/trap_input_record.py | 4 +- src/soc/simple/core.py | 6 +- src/soc/simple/issuer.py | 4 +- src/soc/simulator/test_div_sim.py | 2 +- src/soc/simulator/test_helloworld_sim.py | 2 +- src/soc/simulator/test_mul_sim.py | 2 +- src/soc/simulator/test_sim.py | 2 +- src/soc/simulator/test_trap_sim.py | 2 +- 67 files changed, 295 insertions(+), 295 deletions(-) diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py index d6b191f0..8141e2f7 100644 --- a/src/soc/decoder/decode2execute1.py +++ b/src/soc/decoder/decode2execute1.py @@ -5,7 +5,7 @@ based on Anton Blanchard microwatt decode2.vhdl """ from nmigen import Signal, Record from nmutil.iocontrol import RecordObject -from soc.decoder.power_enums import InternalOp, CryIn, Function, SPR, LDSTMode +from soc.decoder.power_enums import MicrOp, CryIn, Function, SPR, LDSTMode class Data(Record): @@ -29,7 +29,7 @@ class Decode2ToOperand(RecordObject): RecordObject.__init__(self, name=name) - self.insn_type = Signal(InternalOp, reset_less=True) + self.insn_type = Signal(MicrOp, reset_less=True) self.fn_unit = Signal(Function, reset_less=True) self.imm_data = Data(64, name="imm") diff --git a/src/soc/decoder/formal/proof_decoder.py b/src/soc/decoder/formal/proof_decoder.py index e1d793ea..5abd9182 100644 --- a/src/soc/decoder/formal/proof_decoder.py +++ b/src/soc/decoder/formal/proof_decoder.py @@ -6,7 +6,7 @@ from soc.decoder.power_decoder import create_pdecode, PowerOp from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel, OutSel, RC, Form, Function, LdstLen, CryIn, - InternalOp, SPR, get_csv) + MicrOp, SPR, get_csv) from soc.decoder.power_decoder2 import (PowerDecode2, Decode2ToExecute1Type) import unittest @@ -60,7 +60,7 @@ class Driver(Elaboratable): self.comb += self.assert_dec1_signals(dec1, row) with self.m.Default(): self.comb += Assert(dec.op.internal_op == - InternalOp.OP_ILLEGAL) + MicrOp.OP_ILLEGAL) def handle_subdecoders(self, dec1, decoders): @@ -75,7 +75,7 @@ class Driver(Elaboratable): def assert_dec1_signals(self, dec, row): op = dec.op return [Assert(op.function_unit == Function[row['unit']]), - Assert(op.internal_op == InternalOp[row['internal op']]), + Assert(op.internal_op == MicrOp[row['internal op']]), Assert(op.in1_sel == In1Sel[row['in1']]), Assert(op.in2_sel == In2Sel[row['in2']]), Assert(op.in3_sel == In3Sel[row['in3']]), diff --git a/src/soc/decoder/formal/proof_decoder2.py b/src/soc/decoder/formal/proof_decoder2.py index b19588f6..19504473 100644 --- a/src/soc/decoder/formal/proof_decoder2.py +++ b/src/soc/decoder/formal/proof_decoder2.py @@ -5,7 +5,7 @@ from nmutil.formaltest import FHDLTestCase from soc.decoder.power_decoder import create_pdecode, PowerOp from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel, OutSel, RC, Form, - InternalOp, SPR) + MicrOp, SPR) from soc.decoder.power_decoder2 import (PowerDecode2, Decode2ToExecute1Type) import unittest @@ -53,13 +53,13 @@ class Driver(Elaboratable): comb += Assert(pdecode2.e.read_reg1.data == ra) comb += Assert(pdecode2.e.read_reg1.ok == 1) op = pdecode.op.internal_op - with m.If((op == InternalOp.OP_BC) | - (op == InternalOp.OP_BCREG)): + with m.If((op == MicrOp.OP_BC) | + (op == MicrOp.OP_BCREG)): with m.If(~self.instr_bits(8)): comb += Assert(pdecode2.e.read_spr1.data == SPR.CTR) comb += Assert(pdecode2.e.read_spr1.ok == 1) - with m.If((op == InternalOp.OP_MFSPR) | - (op == InternalOp.OP_MTSPR)): + with m.If((op == MicrOp.OP_MFSPR) | + (op == MicrOp.OP_MTSPR)): comb += Assert(pdecode2.e.read_spr1.data == self.instr_bits(11, 20)) comb += Assert(pdecode2.e.read_spr1.ok == 1) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index aeeaa5d5..e5fdfc5a 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -14,7 +14,7 @@ from soc.decoder.orderedset import OrderedSet from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt, selectconcat) from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits, - insns, InternalOp) + insns, MicrOp) from soc.decoder.helpers import exts from soc.consts import PI, MSR @@ -515,7 +515,7 @@ class ISACaller: rc_ok = yield self.dec2.e.do.rc.ok # grrrr have to special-case MUL op (see DecodeOE) print ("ov en rc en", ov_ok, ov_en, rc_ok, rc_en, int_op) - if int_op in [InternalOp.OP_MUL_H64.value, InternalOp.OP_MUL_H32.value]: + if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]: print ("mul op") if rc_en & rc_ok: asmop += "." @@ -526,12 +526,12 @@ class ISACaller: if lk: asmop += "l" print ("int_op", int_op) - if int_op in [InternalOp.OP_B.value, InternalOp.OP_BC.value]: + if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]: AA = yield self.dec2.dec.fields.FormI.AA[0:-1] print ("AA", AA) if AA: asmop += "a" - if int_op == InternalOp.OP_MFCR.value: + if int_op == MicrOp.OP_MFCR.value: dec_insn = yield self.dec2.e.do.insn if dec_insn & (1<<20) != 0: # sigh asmop = 'mfocrf' @@ -539,7 +539,7 @@ class ISACaller: asmop = 'mfcr' # XXX TODO: for whatever weird reason this doesn't work # https://bugs.libre-soc.org/show_bug.cgi?id=390 - if int_op == InternalOp.OP_MTCRF.value: + if int_op == MicrOp.OP_MTCRF.value: dec_insn = yield self.dec2.e.do.insn if dec_insn & (1<<20) != 0: # sigh asmop = 'mtocrf' diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py index c93ee518..b0ad17b2 100644 --- a/src/soc/decoder/power_decoder.py +++ b/src/soc/decoder/power_decoder.py @@ -82,7 +82,7 @@ Top Level: from collections import namedtuple from nmigen import Module, Elaboratable, Signal, Cat, Mux from nmigen.cli import rtlil -from soc.decoder.power_enums import (Function, Form, InternalOp, +from soc.decoder.power_enums import (Function, Form, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, LDSTMode, CryIn, get_csv, single_bit_flags, CRInSel, @@ -117,7 +117,7 @@ class PowerOp: def __init__(self, incl_asm=True): self.function_unit = Signal(Function, reset_less=True) - self.internal_op = Signal(InternalOp, reset_less=True) + self.internal_op = Signal(MicrOp, reset_less=True) self.form = Signal(Form, reset_less=True) if incl_asm: # for simulator only self.asmcode = Signal(8, reset_less=True) @@ -156,7 +156,7 @@ class PowerOp: ldst_mode = LDSTMode[ldst_mode] res = [self.function_unit.eq(Function[row['unit']]), self.form.eq(Form[row['form']]), - self.internal_op.eq(InternalOp[row['internal op']]), + self.internal_op.eq(MicrOp[row['internal op']]), self.in1_sel.eq(In1Sel[row['in1']]), self.in2_sel.eq(In2Sel[row['in2']]), self.in3_sel.eq(In3Sel[row['in3']]), diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 615f78f7..eba6c71d 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -15,7 +15,7 @@ from nmutil.extend import exts from soc.decoder.power_regspec_map import regspec_decode_read from soc.decoder.power_regspec_map import regspec_decode_write from soc.decoder.power_decoder import create_pdecode -from soc.decoder.power_enums import (InternalOp, CryIn, Function, +from soc.decoder.power_enums import (MicrOp, CryIn, Function, CRInSel, CROutSel, LdstLen, In1Sel, In2Sel, In3Sel, OutSel, SPR, RC) @@ -41,12 +41,12 @@ def instr_is_priv(m, op, insn): comb = m.d.comb Signal = is_priv_insn(reset_less=True) with m.Switch(op): - with m.Case(InternalOp.OP_ATTN) : comb += is_priv_insn.eq(1) - with m.Case(InternalOp.OP_MFMSR) : comb += is_priv_insn.eq(1) - with m.Case(InternalOp.OP_MTMSRD): comb += is_priv_insn.eq(1) - with m.Case(InternalOp.OP_MTMSR): comb += is_priv_insn.eq(1) - with m.Case(InternalOp.OP_RFID) : comb += is_priv_insn.eq(1) - with m.Case(InternalOp.OP_TLBIE) : comb += is_priv_insn.eq(1) + with m.Case(MicrOp.OP_ATTN) : comb += is_priv_insn.eq(1) + with m.Case(MicrOp.OP_MFMSR) : comb += is_priv_insn.eq(1) + with m.Case(MicrOp.OP_MTMSRD): comb += is_priv_insn.eq(1) + with m.Case(MicrOp.OP_MTMSR): comb += is_priv_insn.eq(1) + with m.Case(MicrOp.OP_RFID) : comb += is_priv_insn.eq(1) + with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1) with m.If(op == OP_MFSPR | op == OP_MTSPR): with m.If(insn[20]): # field XFX.spr[-1] i think comb += is_priv_insn.eq(1) @@ -112,11 +112,11 @@ class DecodeA(Elaboratable): # decode Fast-SPR based on instruction type op = self.dec.op # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut - with m.If(op.internal_op == InternalOp.OP_BC): + with m.If(op.internal_op == MicrOp.OP_BC): with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR comb += self.fast_out.ok.eq(1) - with m.Elif(op.internal_op == InternalOp.OP_BCREG): + with m.Elif(op.internal_op == MicrOp.OP_BCREG): xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO xo5 = self.dec.FormXL.XO[5] # 3.0B p38 with m.If(xo9 & ~xo5): @@ -124,7 +124,7 @@ class DecodeA(Elaboratable): comb += self.fast_out.ok.eq(1) # MFSPR move from SPRs - with m.If(op.internal_op == InternalOp.OP_MFSPR): + with m.If(op.internal_op == MicrOp.OP_MFSPR): spr = Signal(10, reset_less=True) comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX with m.Switch(spr): @@ -224,7 +224,7 @@ class DecodeB(Elaboratable): op = self.dec.op # BCREG implicitly uses LR or TAR for 2nd reg # CTR however is already in fast_spr1 *not* 2. - with m.If(op.internal_op == InternalOp.OP_BCREG): + with m.If(op.internal_op == MicrOp.OP_BCREG): xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO xo5 = self.dec.FormXL.XO[5] # 3.0B p38 with m.If(~xo9): @@ -297,7 +297,7 @@ class DecodeOut(Elaboratable): spr = Signal(10, reset_less=True) comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX # TODO MTSPR 1st spr (fast) - with m.If(op.internal_op == InternalOp.OP_MTSPR): + with m.If(op.internal_op == MicrOp.OP_MTSPR): with m.Switch(spr): # fast SPRs with m.Case(SPR.CTR.value): @@ -326,14 +326,14 @@ class DecodeOut(Elaboratable): # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA op = self.dec.op - with m.If((op.internal_op == InternalOp.OP_BC) | - (op.internal_op == InternalOp.OP_BCREG)): + with m.If((op.internal_op == MicrOp.OP_BC) | + (op.internal_op == MicrOp.OP_BCREG)): with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR comb += self.fast_out.ok.eq(1) # RFID 1st spr (fast) - with m.If(op.internal_op == InternalOp.OP_RFID): + with m.If(op.internal_op == MicrOp.OP_RFID): comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0 comb += self.fast_out.ok.eq(1) @@ -366,15 +366,15 @@ class DecodeOut2(Elaboratable): # B, BC or BCREG: potential implicit register (LR) output # these give bl, bcl, bclrl, etc. op = self.dec.op - with m.If((op.internal_op == InternalOp.OP_BC) | - (op.internal_op == InternalOp.OP_B) | - (op.internal_op == InternalOp.OP_BCREG)): + with m.If((op.internal_op == MicrOp.OP_BC) | + (op.internal_op == MicrOp.OP_B) | + (op.internal_op == MicrOp.OP_BCREG)): with m.If(self.lk): # "link" mode comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR comb += self.fast_out.ok.eq(1) # RFID 2nd spr (fast) - with m.If(op.internal_op == InternalOp.OP_RFID): + with m.If(op.internal_op == MicrOp.OP_RFID): comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1 comb += self.fast_out.ok.eq(1) @@ -433,8 +433,8 @@ class DecodeOE(Elaboratable): comb = m.d.comb op = self.dec.op - with m.If((op.internal_op == InternalOp.OP_MUL_H64) | - (op.internal_op == InternalOp.OP_MUL_H32)): + with m.If((op.internal_op == MicrOp.OP_MUL_H64) | + (op.internal_op == MicrOp.OP_MUL_H32)): # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE pass with m.Else(): @@ -653,27 +653,27 @@ class PowerDecode2(Elaboratable): # sigh this is exactly the sort of thing for which the # decoder is designed to not need. MTSPR, MFSPR and others need # access to the XER bits. however setting e.oe is not appropriate - with m.If(op.internal_op == InternalOp.OP_MFSPR): + with m.If(op.internal_op == MicrOp.OP_MFSPR): comb += e.xer_in.eq(1) - with m.If(op.internal_op == InternalOp.OP_MTSPR): + with m.If(op.internal_op == MicrOp.OP_MTSPR): comb += e.xer_out.eq(1) # set the trapaddr to 0x700 for a td/tw/tdi/twi operation - with m.If(op.internal_op == InternalOp.OP_TRAP): + with m.If(op.internal_op == MicrOp.OP_TRAP): comb += do.trapaddr.eq(0x70) # addr=0x700 (strip first nibble) # illegal instruction must redirect to trap. this is done by # *overwriting* the decoded instruction and starting again. # (note: the same goes for interrupts and for privileged operations, # just with different trapaddr and traptype) - with m.If(op.internal_op == InternalOp.OP_ILLEGAL): + with m.If(op.internal_op == MicrOp.OP_ILLEGAL): # illegal instruction trap self.trap(m, TT_ILLEG, 0x700) # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs # Note: OP_SC could actually be modified to just be a trap - with m.If((do.insn_type == InternalOp.OP_TRAP) | - (do.insn_type == InternalOp.OP_SC)): + with m.If((do.insn_type == MicrOp.OP_TRAP) | + (do.insn_type == MicrOp.OP_SC)): # TRAP write fast1 = SRR0 comb += e.write_fast1.data.eq(FastRegs.SRR0) # constant: SRR0 comb += e.write_fast1.ok.eq(1) @@ -682,7 +682,7 @@ class PowerDecode2(Elaboratable): comb += e.write_fast2.ok.eq(1) # RFID: needs to read SRR0/1 - with m.If(do.insn_type == InternalOp.OP_RFID): + with m.If(do.insn_type == MicrOp.OP_RFID): # TRAP read fast1 = SRR0 comb += e.read_fast1.data.eq(FastRegs.SRR0) # constant: SRR0 comb += e.read_fast1.ok.eq(1) @@ -706,7 +706,7 @@ class PowerDecode2(Elaboratable): comb += e.eq(0) # reset eeeeeverything # start again comb += do.insn.eq(self.dec.opcode_in) - comb += do.insn_type.eq(InternalOp.OP_TRAP) + comb += do.insn_type.eq(MicrOp.OP_TRAP) comb += do.fn_unit.eq(Function.TRAP) comb += do.trapaddr.eq(trapaddr >> 4) # cut bottom 4 bits comb += do.traptype.eq(traptype) # request type diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py index 92b7101c..817bbd19 100644 --- a/src/soc/decoder/power_enums.py +++ b/src/soc/decoder/power_enums.py @@ -132,7 +132,7 @@ for i, insn in enumerate(_insns): # Internal Operation numbering. Add new opcodes here (FPADD, FPMUL etc.) @unique -class InternalOp(Enum): +class MicrOp(Enum): OP_ILLEGAL = 0 # important that this is zero (see power_decoder.py) OP_NOP = 1 OP_ADD = 2 diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py index 80206db4..72d05a79 100644 --- a/src/soc/decoder/test/test_decoder_gas.py +++ b/src/soc/decoder/test/test_decoder_gas.py @@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay from nmutil.formaltest import FHDLTestCase import unittest from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, InternalOp, +from soc.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, single_bit_flags, Form, SPR, @@ -39,12 +39,12 @@ class Checker: class RegRegOp: def __init__(self): self.ops = { - "add": InternalOp.OP_ADD, - "and": InternalOp.OP_AND, - "or": InternalOp.OP_OR, - "add.": InternalOp.OP_ADD, - "lwzx": InternalOp.OP_LOAD, - "stwx": InternalOp.OP_STORE, + "add": MicrOp.OP_ADD, + "and": MicrOp.OP_AND, + "or": MicrOp.OP_OR, + "add.": MicrOp.OP_ADD, + "lwzx": MicrOp.OP_LOAD, + "stwx": MicrOp.OP_STORE, } self.opcodestr = random.choice(list(self.ops.keys())) self.opcode = self.ops[self.opcodestr] @@ -60,7 +60,7 @@ class RegRegOp: return string def check_results(self, pdecode2): - if self.opcode == InternalOp.OP_STORE: + if self.opcode == MicrOp.OP_STORE: r1sel = yield pdecode2.e.read_reg3.data else: r1sel = yield pdecode2.e.write_reg.data @@ -92,10 +92,10 @@ class RegImmOp(Checker): def __init__(self): super().__init__() self.ops = { - "addi": InternalOp.OP_ADD, - "addis": InternalOp.OP_ADD, - "andi.": InternalOp.OP_AND, - "ori": InternalOp.OP_OR, + "addi": MicrOp.OP_ADD, + "addis": MicrOp.OP_ADD, + "andi.": MicrOp.OP_AND, + "ori": MicrOp.OP_OR, } self.opcodestr = random.choice(list(self.ops.keys())) self.opcode = self.ops[self.opcodestr] @@ -140,14 +140,14 @@ class LdStOp(Checker): def __init__(self): super().__init__() self.ops = { - "lwz": InternalOp.OP_LOAD, - "stw": InternalOp.OP_STORE, - "lwzu": InternalOp.OP_LOAD, - "stwu": InternalOp.OP_STORE, - "lbz": InternalOp.OP_LOAD, - "lhz": InternalOp.OP_LOAD, - "stb": InternalOp.OP_STORE, - "sth": InternalOp.OP_STORE, + "lwz": MicrOp.OP_LOAD, + "stw": MicrOp.OP_STORE, + "lwzu": MicrOp.OP_LOAD, + "stwu": MicrOp.OP_STORE, + "lbz": MicrOp.OP_LOAD, + "lhz": MicrOp.OP_LOAD, + "stb": MicrOp.OP_STORE, + "sth": MicrOp.OP_STORE, } self.opcodestr = random.choice(list(self.ops.keys())) self.opcode = self.ops[self.opcodestr] @@ -167,7 +167,7 @@ class LdStOp(Checker): def check_results(self, pdecode2): print("Check") r2sel = yield pdecode2.e.read_reg1.data - if self.opcode == InternalOp.OP_STORE: + if self.opcode == MicrOp.OP_STORE: r1sel = yield pdecode2.e.read_reg3.data else: r1sel = yield pdecode2.e.write_reg.data @@ -198,7 +198,7 @@ class LdStOp(Checker): class CmpRegOp: def __init__(self): self.ops = { - "cmp": InternalOp.OP_CMP, + "cmp": MicrOp.OP_CMP, } self.opcodestr = random.choice(list(self.ops.keys())) self.opcode = self.ops[self.opcodestr] @@ -226,12 +226,12 @@ class CmpRegOp: class RotateOp: def __init__(self): self.ops = { - "rlwinm": InternalOp.OP_CMP, - "rlwnm": InternalOp.OP_CMP, - "rlwimi": InternalOp.OP_CMP, - "rlwinm.": InternalOp.OP_CMP, - "rlwnm.": InternalOp.OP_CMP, - "rlwimi.": InternalOp.OP_CMP, + "rlwinm": MicrOp.OP_CMP, + "rlwnm": MicrOp.OP_CMP, + "rlwimi": MicrOp.OP_CMP, + "rlwinm.": MicrOp.OP_CMP, + "rlwnm.": MicrOp.OP_CMP, + "rlwimi.": MicrOp.OP_CMP, } self.opcodestr = random.choice(list(self.ops.keys())) self.opcode = self.ops[self.opcodestr] @@ -278,10 +278,10 @@ class RotateOp: class Branch: def __init__(self): self.ops = { - "b": InternalOp.OP_B, - "bl": InternalOp.OP_B, - "ba": InternalOp.OP_B, - "bla": InternalOp.OP_B, + "b": MicrOp.OP_B, + "bl": MicrOp.OP_B, + "ba": MicrOp.OP_B, + "bla": MicrOp.OP_B, } self.opcodestr = random.choice(list(self.ops.keys())) self.opcode = self.ops[self.opcodestr] @@ -311,10 +311,10 @@ class Branch: class BranchCond: def __init__(self): self.ops = { - "bc": InternalOp.OP_B, - "bcl": InternalOp.OP_B, - "bca": InternalOp.OP_B, - "bcla": InternalOp.OP_B, + "bc": MicrOp.OP_B, + "bcl": MicrOp.OP_B, + "bca": MicrOp.OP_B, + "bcla": MicrOp.OP_B, } # Given in Figure 40 "BO field encodings" in section 2.4, page # 33 of the Power ISA v3.0B manual @@ -360,10 +360,10 @@ class BranchCond: class BranchRel: def __init__(self): self.ops = { - "bclr": InternalOp.OP_B, - "bcctr": InternalOp.OP_B, - "bclrl": InternalOp.OP_B, - "bcctrl": InternalOp.OP_B, + "bclr": MicrOp.OP_B, + "bcctr": MicrOp.OP_B, + "bclrl": MicrOp.OP_B, + "bcctrl": MicrOp.OP_B, } # Given in Figure 40 "BO field encodings" in section 2.4, page # 33 of the Power ISA v3.0B manual @@ -403,7 +403,7 @@ class BranchRel: class CROp: def __init__(self): self.ops = { - "crand": InternalOp.OP_CROP, + "crand": MicrOp.OP_CROP, } # Given in Figure 40 "BO field encodings" in section 2.4, page # 33 of the Power ISA v3.0B manual diff --git a/src/soc/decoder/test/test_power_decoder.py b/src/soc/decoder/test/test_power_decoder.py index a03589c3..24da6f44 100644 --- a/src/soc/decoder/test/test_power_decoder.py +++ b/src/soc/decoder/test/test_power_decoder.py @@ -5,7 +5,7 @@ from nmigen.cli import rtlil import os import unittest from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, InternalOp, +from soc.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, CRInSel, CROutSel, OutSel, RC, LdstLen, CryIn, @@ -20,7 +20,7 @@ class DecoderTestCase(FHDLTestCase): comb = m.d.comb opcode = Signal(32) function_unit = Signal(Function) - internal_op = Signal(InternalOp) + internal_op = Signal(MicrOp) in1_sel = Signal(In1Sel) in2_sel = Signal(In2Sel) in3_sel = Signal(In3Sel) @@ -76,7 +76,7 @@ class DecoderTestCase(FHDLTestCase): yield Delay(1e-6) signals = [(function_unit, Function, 'unit'), - (internal_op, InternalOp, 'internal op'), + (internal_op, MicrOp, 'internal op'), (in1_sel, In1Sel, 'in1'), (in2_sel, In2Sel, 'in2'), (in3_sel, In3Sel, 'in3'), diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py index c1ca6fa3..90838b26 100644 --- a/src/soc/experiment/alu_hier.py +++ b/src/soc/experiment/alu_hier.py @@ -16,7 +16,7 @@ from nmigen.cli import verilog, rtlil from nmigen.compat.sim import run_simulation from nmigen.back.pysim import Simulator, Settle -from soc.decoder.power_enums import InternalOp, Function, CryIn +from soc.decoder.power_enums import MicrOp, Function, CryIn from soc.fu.alu.alu_input_record import CompALUOpSubset from soc.fu.cr.cr_input_record import CompCROpSubset @@ -239,24 +239,24 @@ class ALU(Elaboratable): with m.If(self.p.valid_i): # as this is a "fake" pipeline, just grab the output right now - with m.If(self.op.insn_type == InternalOp.OP_ADD): + with m.If(self.op.insn_type == MicrOp.OP_ADD): m.d.sync += alu_r.eq(add.o) - with m.Elif(self.op.insn_type == InternalOp.OP_MUL_L64): + with m.Elif(self.op.insn_type == MicrOp.OP_MUL_L64): m.d.sync += alu_r.eq(mul.o) - with m.Elif(self.op.insn_type == InternalOp.OP_SHR): + with m.Elif(self.op.insn_type == MicrOp.OP_SHR): m.d.sync += alu_r.eq(shf.o) # SUB is zero-delay, no need to register # NOTE: all of these are fake, just something to test # MUL, to take 5 instructions - with m.If(self.op.insn_type == InternalOp.OP_MUL_L64): + with m.If(self.op.insn_type == MicrOp.OP_MUL_L64): m.d.sync += self.counter.eq(5) # SHIFT to take 1, straight away - with m.Elif(self.op.insn_type == InternalOp.OP_SHR): + with m.Elif(self.op.insn_type == MicrOp.OP_SHR): m.d.sync += self.counter.eq(1) # ADD/SUB to take 3 - with m.Elif(self.op.insn_type == InternalOp.OP_ADD): + with m.Elif(self.op.insn_type == MicrOp.OP_ADD): m.d.sync += self.counter.eq(3) # others to take no delay with m.Else(): @@ -417,25 +417,25 @@ def run_op(dut, a, b, op, inv_a=0): def alu_sim(dut): - result = yield from run_op(dut, 5, 3, InternalOp.OP_ADD) + result = yield from run_op(dut, 5, 3, MicrOp.OP_ADD) print ("alu_sim add", result) assert (result == 8) - result = yield from run_op(dut, 2, 3, InternalOp.OP_MUL_L64) + result = yield from run_op(dut, 2, 3, MicrOp.OP_MUL_L64) print ("alu_sim mul", result) assert (result == 6) - result = yield from run_op(dut, 5, 3, InternalOp.OP_ADD, inv_a=1) + result = yield from run_op(dut, 5, 3, MicrOp.OP_ADD, inv_a=1) print ("alu_sim add-inv", result) assert (result == 65533) # test zero-delay ALU # don't have OP_SUB, so use any other - result = yield from run_op(dut, 5, 3, InternalOp.OP_NOP) + result = yield from run_op(dut, 5, 3, MicrOp.OP_NOP) print ("alu_sim sub", result) assert (result == 2) - result = yield from run_op(dut, 13, 2, InternalOp.OP_SHR) + result = yield from run_op(dut, 13, 2, MicrOp.OP_SHR) print ("alu_sim shr", result) assert (result == 3) @@ -496,21 +496,21 @@ def test_alu_parallel(): # note that, for this test, we do not wait for the result to be ready, # before presenting the next input # 5 + 3 - yield from send(5, 3, InternalOp.OP_ADD) + yield from send(5, 3, MicrOp.OP_ADD) yield yield # 2 * 3 - yield from send(2, 3, InternalOp.OP_MUL_L64) + yield from send(2, 3, MicrOp.OP_MUL_L64) # (-5) + 3 - yield from send(5, 3, InternalOp.OP_ADD, inv_a=1) + yield from send(5, 3, MicrOp.OP_ADD, inv_a=1) yield # 5 - 3 # note that this is a zero-delay operation - yield from send(5, 3, InternalOp.OP_NOP) + yield from send(5, 3, MicrOp.OP_NOP) yield yield # 13 >> 2 - yield from send(13, 2, InternalOp.OP_SHR) + yield from send(13, 2, MicrOp.OP_SHR) def consumer(): # receive and check results, interspersed with wait states diff --git a/src/soc/experiment/compalu.py b/src/soc/experiment/compalu.py index 52e21f7b..dcab911a 100644 --- a/src/soc/experiment/compalu.py +++ b/src/soc/experiment/compalu.py @@ -4,7 +4,7 @@ from nmigen import Module, Signal, Mux, Elaboratable from nmutil.latch import SRLatch, latchregister from soc.decoder.power_decoder2 import Data -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp from soc.experiment.alu_hier import CompALUOpSubset @@ -211,14 +211,14 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0): def scoreboard_sim(dut): - result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0, + result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=0, imm=8, imm_ok=1) assert result == 13 - result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1) + result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=1) assert result == 65532 - result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD) + result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD) assert result == 7 diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index 2bc00937..2a040917 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -90,7 +90,7 @@ from soc.experiment.compalu_multi import go_record, CompUnitRecord from soc.experiment.l0_cache import PortInterface from soc.fu.regspec import RegSpecAPI -from soc.decoder.power_enums import InternalOp, Function, LDSTMode +from soc.decoder.power_enums import MicrOp, Function, LDSTMode from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset from soc.decoder.power_decoder2 import Data @@ -388,8 +388,8 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): sync += alu_ok.eq(alu_valid) # keep ack in sync with EA # decode bits of operand (latched) - comb += op_is_st.eq(oper_r.insn_type == InternalOp.OP_STORE) # ST - comb += op_is_ld.eq(oper_r.insn_type == InternalOp.OP_LOAD) # LD + comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE) # ST + comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD) # LD op_is_update = oper_r.ldst_mode == LDSTMode.update # UPDATE op_is_cix = oper_r.ldst_mode == LDSTMode.cix # cache-inhibit comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i) @@ -550,7 +550,7 @@ def wait_for(sig, wait=True, test1st=False): def store(dut, src1, src2, src3, imm, imm_ok=True, update=False, byterev=True): print ("ST", src1, src2, src3, imm, imm_ok, update) - yield dut.oper_i.insn_type.eq(InternalOp.OP_STORE) + yield dut.oper_i.insn_type.eq(MicrOp.OP_STORE) yield dut.oper_i.data_len.eq(2) # half-word yield dut.oper_i.byte_reverse.eq(byterev) yield dut.src1_i.eq(src1) @@ -606,7 +606,7 @@ def store(dut, src1, src2, src3, imm, imm_ok=True, update=False, def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False, byterev=True): print ("LD", src1, src2, imm, imm_ok, update) - yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD) + yield dut.oper_i.insn_type.eq(MicrOp.OP_LOAD) yield dut.oper_i.data_len.eq(2) # half-word yield dut.oper_i.byte_reverse.eq(byterev) yield dut.src1_i.eq(src1) diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index 6efde593..7c20f0e9 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -24,7 +24,7 @@ from nmigen.hdl.rec import Record, Layout from nmutil.latch import SRLatch, latchregister from soc.decoder.power_decoder2 import Data -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp from soc.regfile.regfile import ortreereduce from nmutil.util import treereduce diff --git a/src/soc/experiment/score6600.py b/src/soc/experiment/score6600.py index 83049a53..8995631f 100644 --- a/src/soc/experiment/score6600.py +++ b/src/soc/experiment/score6600.py @@ -20,7 +20,7 @@ from soc.experiment.testmem import TestMemory from soc.experiment.alu_hier import ALU, BranchALU, CompALUOpSubset -from soc.decoder.power_enums import InternalOp, Function +from soc.decoder.power_enums import MicrOp, Function from soc.decoder.power_decoder import (create_pdecode) from soc.decoder.power_decoder2 import (PowerDecode2) from soc.simulator.program import Program @@ -1178,15 +1178,15 @@ def scoreboard_sim(dut, alusim): instrs.append((1, 7, 2, 2, 0, 0, (0, 0))) if True: - instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU, + instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU, 0, 0, (0, 0))) - instrs.append((5, 3, 3, InternalOp.OP_ADD, Function.ALU, + instrs.append((5, 3, 3, MicrOp.OP_ADD, Function.ALU, 0, 0, (0, 0))) if False: - instrs.append((3, 5, 5, InternalOp.OP_MUL_L64, Function.ALU, + instrs.append((3, 5, 5, MicrOp.OP_MUL_L64, Function.ALU, 1, 7, (0, 0))) if False: - instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU, + instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU, 0, 0, (0, 0))) if False: diff --git a/src/soc/experiment/score6600_multi.py b/src/soc/experiment/score6600_multi.py index 95f12dc3..2d3ba001 100644 --- a/src/soc/experiment/score6600_multi.py +++ b/src/soc/experiment/score6600_multi.py @@ -23,7 +23,7 @@ from soc.experiment.l0_cache import TstL0CacheBuffer from soc.experiment.alu_hier import ALU, BranchALU from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import InternalOp, Function +from soc.decoder.power_enums import MicrOp, Function from soc.decoder.power_decoder import (create_pdecode) from soc.decoder.power_decoder2 import (PowerDecode2) from soc.decoder.power_decoder2 import Decode2ToExecute1Type @@ -1229,15 +1229,15 @@ def scoreboard_sim(dut, alusim): instrs.append((1, 7, 2, 2, 0, 0, (0, 0))) if True: - instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU, + instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU, 0, 0, (0, 0))) - instrs.append((5, 3, 3, InternalOp.OP_ADD, Function.ALU, + instrs.append((5, 3, 3, MicrOp.OP_ADD, Function.ALU, 0, 0, (0, 0))) if False: - instrs.append((3, 5, 5, InternalOp.OP_MUL_L64, Function.ALU, + instrs.append((3, 5, 5, MicrOp.OP_MUL_L64, Function.ALU, 1, 7, (0, 0))) if False: - instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU, + instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU, 0, 0, (0, 0))) if False: diff --git a/src/soc/experiment/sim.py b/src/soc/experiment/sim.py index 1c725b25..2c2197aa 100644 --- a/src/soc/experiment/sim.py +++ b/src/soc/experiment/sim.py @@ -1,4 +1,4 @@ -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp from random import randint, seed from copy import deepcopy @@ -43,9 +43,9 @@ class RegSim: src2 = imm else: src2 = self.regs[src2] & maxbits - if op == InternalOp.OP_ADD: + if op == MicrOp.OP_ADD: val = src1 + src2 - elif op == InternalOp.OP_MUL_L64: + elif op == MicrOp.OP_MUL_L64: val = src1 * src2 print ("mul src1, src2", src1, src2, val) elif op == ISUB: diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py index 31a50bba..f32f6631 100644 --- a/src/soc/experiment/test/test_compalu_multi.py +++ b/src/soc/experiment/test/test_compalu_multi.py @@ -14,7 +14,7 @@ from nmigen.compat.sim import run_simulation, Settle from nmigen.cli import rtlil from nmigen import Module -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp from soc.experiment.compalu_multi import MultiCompUnit from soc.experiment.alu_hier import ALU, DummyALU @@ -75,37 +75,37 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0): def scoreboard_sim_dummy(dut): - result = yield from op_sim(dut, 5, 2, InternalOp.OP_NOP, inv_a=0, + result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP, inv_a=0, imm=8, imm_ok=1) assert result == 5, result - result = yield from op_sim(dut, 9, 2, InternalOp.OP_NOP, inv_a=0, + result = yield from op_sim(dut, 9, 2, MicrOp.OP_NOP, inv_a=0, imm=8, imm_ok=1) assert result == 9, result def scoreboard_sim(dut): - result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0, + result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=0, imm=8, imm_ok=1) assert result == 13 - result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD) + result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD) assert result == 7 - result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1) + result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=1) assert result == 65532 - result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1, + result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1, imm=8, imm_ok=1) assert result == 8 - result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1) + result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1) assert result == 2 # test combinatorial zero-delay operation # In the test ALU, any operation other than ADD, MUL or SHR # is zero-delay, and do a subtraction. - result = yield from op_sim(dut, 5, 2, InternalOp.OP_NOP) + result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP) assert result == 3 @@ -153,7 +153,7 @@ class CompUnitParallelTest: def driver(self): print("Begin parallel test.") - yield from self.operation(5, 2, InternalOp.OP_ADD) + yield from self.operation(5, 2, MicrOp.OP_ADD) def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0, rdmaskn=(0, 0)): diff --git a/src/soc/fu/alu/alu_input_record.py b/src/soc/fu/alu/alu_input_record.py index 70e4a9c2..253714e9 100644 --- a/src/soc/fu/alu/alu_input_record.py +++ b/src/soc/fu/alu/alu_input_record.py @@ -1,6 +1,6 @@ from nmigen.hdl.rec import Record, Layout -from soc.decoder.power_enums import InternalOp, Function, CryIn +from soc.decoder.power_enums import MicrOp, Function, CryIn class CompALUOpSubset(Record): @@ -11,7 +11,7 @@ class CompALUOpSubset(Record): grab subsets. """ def __init__(self, name=None): - layout = (('insn_type', InternalOp), + layout = (('insn_type', MicrOp), ('fn_unit', Function), ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data diff --git a/src/soc/fu/alu/formal/proof_input_stage.py b/src/soc/fu/alu/formal/proof_input_stage.py index f9b71600..0d664a75 100644 --- a/src/soc/fu/alu/formal/proof_input_stage.py +++ b/src/soc/fu/alu/formal/proof_input_stage.py @@ -9,7 +9,7 @@ from nmigen.cli import rtlil from soc.fu.alu.input_stage import ALUInputStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp import unittest diff --git a/src/soc/fu/alu/formal/proof_main_stage.py b/src/soc/fu/alu/formal/proof_main_stage.py index c1e71536..5e70d1e8 100644 --- a/src/soc/fu/alu/formal/proof_main_stage.py +++ b/src/soc/fu/alu/formal/proof_main_stage.py @@ -16,7 +16,7 @@ from nmigen.cli import rtlil from soc.fu.alu.main_stage import ALUMainStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp import unittest @@ -90,7 +90,7 @@ class Driver(Elaboratable): # main assertion of arithmetic operations with m.Switch(rec.insn_type): - with m.Case(InternalOp.OP_ADD): + with m.Case(MicrOp.OP_ADD): # check result of 65-bit add-with-carry comb += Assert(Cat(o, ca_o) == (a + b + ca_in)) @@ -105,7 +105,7 @@ class Driver(Elaboratable): comb += ca_ok.eq(1) comb += o_ok.eq(1) - with m.Case(InternalOp.OP_EXTS): + with m.Case(MicrOp.OP_EXTS): for i in [1, 2, 4]: with m.If(rec.data_len == i): # main part, then sign-bit replicated up @@ -113,12 +113,12 @@ class Driver(Elaboratable): comb += Assert(o[i*8:64] == Repl(a[i*8-1], 64-(i*8))) comb += o_ok.eq(1) - with m.Case(InternalOp.OP_CMP): + with m.Case(MicrOp.OP_CMP): # CMP is defined as not taking in carry comb += Assume(ca_in == 0) comb += Assert(o == (a+b)[0:64]) - with m.Case(InternalOp.OP_CMPEQB): + with m.Case(MicrOp.OP_CMPEQB): src1 = a[0:8] eqs = Signal(8) for i in range(8): diff --git a/src/soc/fu/alu/formal/proof_output_stage.py b/src/soc/fu/alu/formal/proof_output_stage.py index 8148d1eb..7dd3f383 100644 --- a/src/soc/fu/alu/formal/proof_output_stage.py +++ b/src/soc/fu/alu/formal/proof_output_stage.py @@ -15,7 +15,7 @@ from nmigen.cli import rtlil from soc.fu.alu.output_stage import ALUOutputStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp import unittest @@ -83,13 +83,13 @@ class Driver(Elaboratable): # sigh. see https://bugs.libre-soc.org/show_bug.cgi?id=305#c61 # for OP_CMP we do b-a rather than a-b (just like ADD) and # then invert the *test condition*. - with m.If(rec.insn_type == InternalOp.OP_CMP): + with m.If(rec.insn_type == MicrOp.OP_CMP): comb += Assert(cr_out[3] == 1) with m.Else(): comb += Assert(cr_out[2] == 1) with m.Elif(o_signed < 0): # ditto as above - with m.If(rec.insn_type == InternalOp.OP_CMP): + with m.If(rec.insn_type == MicrOp.OP_CMP): comb += Assert(cr_out[2] == 1) with m.Else(): comb += Assert(cr_out[3] == 1) diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py index 24330676..719a9a73 100644 --- a/src/soc/fu/alu/main_stage.py +++ b/src/soc/fu/alu/main_stage.py @@ -8,7 +8,7 @@ from nmutil.pipemodbase import PipeModBase from nmutil.extend import exts from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp # microwatt calc_ov function. @@ -46,8 +46,8 @@ class ALUMainStage(PipeModBase): add_a = Signal(a.width + 2, reset_less=True) add_b = Signal(a.width + 2, reset_less=True) add_o = Signal(a.width + 2, reset_less=True) - with m.If((op.insn_type == InternalOp.OP_ADD) | - (op.insn_type == InternalOp.OP_CMP)): + with m.If((op.insn_type == MicrOp.OP_ADD) | + (op.insn_type == MicrOp.OP_CMP)): # in bit 0, 1+carry_in creates carry into bit 1 and above comb += add_a.eq(Cat(cry_i[0], a, Const(0, 1))) comb += add_b.eq(Cat(Const(1, 1), b, Const(0, 1))) @@ -58,7 +58,7 @@ class ALUMainStage(PipeModBase): with m.Switch(op.insn_type): #### CMP, CMPL #### - with m.Case(InternalOp.OP_CMP): + with m.Case(MicrOp.OP_CMP): # this is supposed to be inverted (b-a, not a-b) # however we have a trick: instead of adding either 2x 64-bit # MUXes to invert a and b, or messing with a 64-bit output, @@ -67,7 +67,7 @@ class ALUMainStage(PipeModBase): comb += o.ok.eq(0) # use o.data but do *not* actually output #### add #### - with m.Case(InternalOp.OP_ADD): + with m.Case(MicrOp.OP_ADD): # bit 0 is not part of the result, top bit is the carry-out comb += o.data.eq(add_o[1:-1]) comb += o.ok.eq(1) # output register @@ -87,7 +87,7 @@ class ALUMainStage(PipeModBase): comb += ov_o.ok.eq(1) #### exts (sign-extend) #### - with m.Case(InternalOp.OP_EXTS): + with m.Case(MicrOp.OP_EXTS): with m.If(op.data_len == 1): comb += o.data.eq(exts(a, 8, 64)) with m.If(op.data_len == 2): @@ -97,7 +97,7 @@ class ALUMainStage(PipeModBase): comb += o.ok.eq(1) # output register #### cmpeqb #### - with m.Case(InternalOp.OP_CMPEQB): + with m.Case(MicrOp.OP_CMPEQB): eqs = Signal(8, reset_less=True) src1 = Signal(8, reset_less=True) comb += src1.eq(a[0:8]) diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py index 58d9708d..e7d1c673 100644 --- a/src/soc/fu/alu/output_stage.py +++ b/src/soc/fu/alu/output_stage.py @@ -5,7 +5,7 @@ from nmigen import (Module, Signal, Cat, Repl) from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData from soc.fu.common_output_stage import CommonOutputStage from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp class ALUOutputStage(CommonOutputStage): diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index 6b3ae3f3..9201c008 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -6,7 +6,7 @@ import unittest from soc.decoder.isa.caller import ISACaller, special_sprs from soc.decoder.power_decoder import (create_pdecode) from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn) +from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) from soc.decoder.selectable_int import SelectableInt from soc.simulator.program import Program from soc.decoder.isa.all import ISA diff --git a/src/soc/fu/branch/br_input_record.py b/src/soc/fu/branch/br_input_record.py index b3679e38..0bfb1934 100644 --- a/src/soc/fu/branch/br_input_record.py +++ b/src/soc/fu/branch/br_input_record.py @@ -1,6 +1,6 @@ from nmigen.hdl.rec import Record, Layout -from soc.decoder.power_enums import InternalOp, Function, CryIn +from soc.decoder.power_enums import MicrOp, Function, CryIn class CompBROpSubset(Record): @@ -15,7 +15,7 @@ class CompBROpSubset(Record): grab subsets. """ def __init__(self, name=None): - layout = (('insn_type', InternalOp), + layout = (('insn_type', MicrOp), ('fn_unit', Function), ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), ('lk', 1), diff --git a/src/soc/fu/branch/formal/proof_input_stage.py b/src/soc/fu/branch/formal/proof_input_stage.py index 0ce65226..52409c4e 100644 --- a/src/soc/fu/branch/formal/proof_input_stage.py +++ b/src/soc/fu/branch/formal/proof_input_stage.py @@ -9,7 +9,7 @@ from nmigen.cli import rtlil from soc.fu.alu.input_stage import ALUInputStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.branch.br_input_record import CompBROpSubset -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp import unittest @@ -57,7 +57,7 @@ class Driver(Elaboratable): comb += Assert(dut.o.a == a) with m.If(rec.imm_data.imm_ok & - ~(rec.insn_type == InternalOp.OP_RLC)): + ~(rec.insn_type == MicrOp.OP_RLC)): comb += Assert(dut.o.b == rec.imm_data.imm) with m.Else(): comb += Assert(dut.o.b == b) diff --git a/src/soc/fu/branch/formal/proof_main_stage.py b/src/soc/fu/branch/formal/proof_main_stage.py index 394c4346..3e1879ae 100644 --- a/src/soc/fu/branch/formal/proof_main_stage.py +++ b/src/soc/fu/branch/formal/proof_main_stage.py @@ -16,7 +16,7 @@ from nmigen.cli import rtlil from soc.fu.branch.main_stage import BranchMainStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp import unittest @@ -101,7 +101,7 @@ class Driver(Elaboratable): with m.Switch(rec.insn_type): #### b #### - with m.Case(InternalOp.OP_B): + with m.Case(MicrOp.OP_B): # Extract target address LI = i_fields.LI[0:-1] imm = exts(LI, LI.shape().width, 64-2) * 4 @@ -126,7 +126,7 @@ class Driver(Elaboratable): comb += Assert(dut.o.ctr.ok == 0) #### bc #### - with m.Case(InternalOp.OP_BC): + with m.Case(MicrOp.OP_BC): # Assert that branches are conditional comb += Assert(nia_o.ok == (cond_ok & ctr_ok)) @@ -151,7 +151,7 @@ class Driver(Elaboratable): with m.Else(): comb += Assert(dut.o.ctr.ok == 0) #### bctar/bcctr/bclr #### - with m.Case(InternalOp.OP_BCREG): + with m.Case(MicrOp.OP_BCREG): # assert that the condition is good comb += Assert(nia_o.ok == (cond_ok & ctr_ok)) diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py index 9d7c2a54..a46a95c3 100644 --- a/src/soc/fu/branch/main_stage.py +++ b/src/soc/fu/branch/main_stage.py @@ -13,7 +13,7 @@ from nmigen import (Module, Signal, Cat, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase from nmutil.extend import exts from soc.fu.branch.pipe_data import BranchInputData, BranchOutputData -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp from soc.decoder.power_fields import DecodeFields from soc.decoder.power_fieldsn import SignalBitRange @@ -70,7 +70,7 @@ class BranchMainStage(PipeModBase): br_taken = Signal(reset_less=True) # Handle absolute or relative branches - with m.If(AA | (op.insn_type == InternalOp.OP_BCREG)): + with m.If(AA | (op.insn_type == MicrOp.OP_BCREG)): comb += br_addr.eq(br_imm_addr) with m.Else(): comb += br_addr.eq(br_imm_addr + cia) @@ -121,18 +121,18 @@ class BranchMainStage(PipeModBase): ### Main Switch Statement ### with m.Switch(op.insn_type): #### branch #### - with m.Case(InternalOp.OP_B): + with m.Case(MicrOp.OP_B): LI = i_fields.LI[0:-1] comb += br_imm_addr.eq(br_ext(LI)) comb += br_taken.eq(1) #### branch conditional #### - with m.Case(InternalOp.OP_BC): + with m.Case(MicrOp.OP_BC): BD = b_fields.BD[0:-1] comb += br_imm_addr.eq(br_ext(BD)) comb += br_taken.eq(bc_taken) comb += ctr_o.ok.eq(ctr_write) #### branch conditional reg #### - with m.Case(InternalOp.OP_BCREG): + with m.Case(MicrOp.OP_BCREG): xo = self.fields.FormXL.XO[0:-1] with m.If(xo[9] & ~xo[5]): comb += br_imm_addr.eq(Cat(Const(0, 2), fast1[2:])) diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index 947cff28..70796198 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -6,7 +6,7 @@ import unittest from soc.decoder.isa.caller import ISACaller, special_sprs from soc.decoder.power_decoder import (create_pdecode) from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, InternalOp) +from soc.decoder.power_enums import (XER_bits, Function, MicrOp) from soc.decoder.selectable_int import SelectableInt from soc.simulator.program import Program from soc.decoder.isa.all import ISA diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py index d5916a0a..4dbb5c07 100644 --- a/src/soc/fu/common_input_stage.py +++ b/src/soc/fu/common_input_stage.py @@ -3,7 +3,7 @@ # generation for subtraction, should happen here from nmigen import (Module, Signal) from nmutil.pipemodbase import PipeModBase -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp from soc.decoder.power_enums import CryIn diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index 4a9f391d..cc0f00a3 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -3,7 +3,7 @@ from nmigen import (Module, Signal, Cat, Const) from nmutil.pipemodbase import PipeModBase from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp class CommonOutputStage(PipeModBase): @@ -60,8 +60,8 @@ class CommonOutputStage(PipeModBase): # that can be used as a test of whether to invert the +ve/-ve test # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60 - comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP) - comb += is_cmpeqb.eq(op.insn_type == InternalOp.OP_CMPEQB) + comb += is_cmp.eq(op.insn_type == MicrOp.OP_CMP) + comb += is_cmpeqb.eq(op.insn_type == MicrOp.OP_CMPEQB) # nope - if *processor* mode is 32-bit #with m.If(op.is_32bit): # comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB diff --git a/src/soc/fu/compunits/formal/test_compunit.py b/src/soc/fu/compunits/formal/test_compunit.py index 956b5d77..153879ba 100644 --- a/src/soc/fu/compunits/formal/test_compunit.py +++ b/src/soc/fu/compunits/formal/test_compunit.py @@ -6,7 +6,7 @@ from soc.fu.compunits.compunits import FunctionUnitBaseSingle from soc.experiment.alu_hier import DummyALU from soc.experiment.compalu_multi import MultiCompUnit from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp import unittest class MaskGenTestCase(FHDLTestCase): @@ -22,7 +22,7 @@ class MaskGenTestCase(FHDLTestCase): yield dut.src1_i.eq(0x5) yield dut.src2_i.eq(0x5) yield dut.issue_i.eq(1) - yield dut.oper_i.insn_type.eq(InternalOp.OP_ADD) + yield dut.oper_i.insn_type.eq(MicrOp.OP_ADD) yield yield dut.issue_i.eq(0) yield diff --git a/src/soc/fu/cr/cr_input_record.py b/src/soc/fu/cr/cr_input_record.py index 11e85d15..bfe4ab82 100644 --- a/src/soc/fu/cr/cr_input_record.py +++ b/src/soc/fu/cr/cr_input_record.py @@ -1,6 +1,6 @@ from nmigen.hdl.rec import Record, Layout -from soc.decoder.power_enums import (InternalOp, Function) +from soc.decoder.power_enums import (MicrOp, Function) class CompCROpSubset(Record): @@ -11,7 +11,7 @@ class CompCROpSubset(Record): grab subsets. """ def __init__(self, name=None): - layout = (('insn_type', InternalOp), + layout = (('insn_type', MicrOp), ('fn_unit', Function), ('insn', 32), ('read_cr_whole', 1), diff --git a/src/soc/fu/cr/formal/proof_main_stage.py b/src/soc/fu/cr/formal/proof_main_stage.py index 96dbe4bf..c24fb42c 100644 --- a/src/soc/fu/cr/formal/proof_main_stage.py +++ b/src/soc/fu/cr/formal/proof_main_stage.py @@ -14,7 +14,7 @@ from nmigen.cli import rtlil from soc.fu.cr.main_stage import CRMainStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp import unittest @@ -76,7 +76,7 @@ class Driver(Elaboratable): with m.Switch(rec.insn_type): # CR_ISEL takes cr_a - with m.Case(InternalOp.OP_ISEL): + with m.Case(MicrOp.OP_ISEL): # grab the MSBs of the cr bit selector bc = Signal(3, reset_less=True) comb += bc.eq(a_fields.BC[2:5]) @@ -88,7 +88,7 @@ class Driver(Elaboratable): # For OP_CROP, we need to input the corresponding CR # registers for BA, BB, and BT - with m.Case(InternalOp.OP_CROP): + with m.Case(MicrOp.OP_CROP): # grab the MSBs of the 3 bit selectors bt = Signal(3, reset_less=True) ba = Signal(3, reset_less=True) @@ -111,7 +111,7 @@ class Driver(Elaboratable): with m.Else(): comb += cr_output_arr[i].eq(dut.o.cr.data) - with m.Case(InternalOp.OP_MCRF): + with m.Case(MicrOp.OP_MCRF): # This does a similar thing to OP_CROP above, with # less inputs. The CR selection fields are already 3 # bits so there's no need to grab only the MSBs @@ -128,7 +128,7 @@ class Driver(Elaboratable): comb += cr_output_arr[i].eq(dut.o.cr.data) # Set the input similar to OP_MCRF - with m.Case(InternalOp.OP_SETB): + with m.Case(MicrOp.OP_SETB): comb += dut.i.cr_a.eq(cr_input_arr[bfa]) # For the other two, they take the full CR as input, and @@ -159,13 +159,13 @@ class Driver(Elaboratable): FXM = xfx_fields.FXM[0:-1] with m.Switch(rec.insn_type): - with m.Case(InternalOp.OP_MTCRF): + with m.Case(MicrOp.OP_MTCRF): for i in range(8): with m.If(FXM[i]): comb += Assert(cr_o[4*i:4*i+4] == a[4*i:4*i+4]) comb += full_cr_o_ok.eq(1) - with m.Case(InternalOp.OP_MFCR): + with m.Case(MicrOp.OP_MFCR): with m.If(rec.insn[20]): # mfocrf for i in range(8): with m.If(FXM[i]): @@ -176,7 +176,7 @@ class Driver(Elaboratable): comb += Assert(o == cr) comb += o_ok.eq(1) - with m.Case(InternalOp.OP_MCRF): + with m.Case(MicrOp.OP_MCRF): BF = xl_fields.BF[0:-1] BFA = xl_fields.BFA[0:-1] for i in range(4): @@ -186,7 +186,7 @@ class Driver(Elaboratable): comb += Assert(cr_o[i*4:i*4+4] == cr[i*4:i*4+4]) comb += cr_o_ok.eq(1) - with m.Case(InternalOp.OP_CROP): + with m.Case(MicrOp.OP_CROP): bt = Signal(xl_fields.BT[0:-1].shape(), reset_less=True) ba = Signal(xl_fields.BA[0:-1].shape(), reset_less=True) bb = Signal(xl_fields.BB[0:-1].shape(), reset_less=True) @@ -222,7 +222,7 @@ class Driver(Elaboratable): comb += cr_o_ok.eq(1) - with m.Case(InternalOp.OP_ISEL): + with m.Case(MicrOp.OP_ISEL): # Extract the bit selector of the CR bc = Signal(a_fields.BC[0:-1].shape(), reset_less=True) comb += bc.eq(a_fields.BC[0:-1]) @@ -235,7 +235,7 @@ class Driver(Elaboratable): comb += Assert(o == Mux(cr_bit, a, b)) comb += o_ok.eq(1) - with m.Case(InternalOp.OP_SETB): + with m.Case(MicrOp.OP_SETB): with m.If(cr_arr[4*bfa]): comb += Assert(o == ((1<<64)-1)) with m.Elif(cr_arr[4*bfa+1]): diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py index 14828577..27aa6670 100644 --- a/src/soc/fu/cr/main_stage.py +++ b/src/soc/fu/cr/main_stage.py @@ -12,7 +12,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase from soc.fu.cr.pipe_data import CRInputData, CROutputData -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp from soc.decoder.power_fields import DecodeFields from soc.decoder.power_fieldsn import SignalBitRange @@ -54,7 +54,7 @@ class CRMainStage(PipeModBase): with m.Switch(op.insn_type): ##### mcrf ##### - with m.Case(InternalOp.OP_MCRF): + with m.Case(MicrOp.OP_MCRF): # MCRF copies the 4 bits of crA to crB (for instance # copying cr2 to cr1) # Since it takes in a 4 bit cr, and outputs a 4 bit @@ -63,7 +63,7 @@ class CRMainStage(PipeModBase): comb += cr_o.ok.eq(1) # indicate "this CR has changed" # ##### crand, cror, crnor etc. ##### - with m.Case(InternalOp.OP_CROP): + with m.Case(MicrOp.OP_CROP): # crand/cror and friends get decoded to the same opcode, but # one of the fields inside the instruction is a 4 bit lookup # table. This lookup table gets indexed by bits a and b from @@ -109,7 +109,7 @@ class CRMainStage(PipeModBase): comb += cr_o.ok.eq(1) # indicate "this CR has changed" ##### mtcrf ##### - with m.Case(InternalOp.OP_MTCRF): + with m.Case(MicrOp.OP_MTCRF): # mtocrf and mtcrf are essentially identical # put input (RA) - mask-selected - into output CR, leave # rest of CR alone. @@ -117,7 +117,7 @@ class CRMainStage(PipeModBase): comb += full_cr_o.ok.eq(1) # indicate "this CR has changed" # ##### mfcr ##### - with m.Case(InternalOp.OP_MFCR): + with m.Case(MicrOp.OP_MFCR): # Ugh. mtocrf and mtcrf have one random bit differentiating # them. This bit is not in any particular field, so this # extracts that bit from the instruction @@ -135,7 +135,7 @@ class CRMainStage(PipeModBase): comb += rt_o.ok.eq(1) # indicate "INT reg changed" # ##### isel ##### - with m.Case(InternalOp.OP_ISEL): + with m.Case(MicrOp.OP_ISEL): # just like in branch, CR0-7 is incoming into cr_a, we # need to select from the last 2 bits of BC a_fields = self.fields.FormA @@ -150,7 +150,7 @@ class CRMainStage(PipeModBase): comb += rt_o.eq(Mux(cr_bit, a, b)) comb += rt_o.ok.eq(1) # indicate "INT reg changed" - with m.Case(InternalOp.OP_SETB): + with m.Case(MicrOp.OP_SETB): with m.If(cr_a[3]): comb += rt_o.data.eq(-1) with m.Elif(cr_a[2]): diff --git a/src/soc/fu/div/core_stages.py b/src/soc/fu/div/core_stages.py index 32f29e68..aa53845a 100644 --- a/src/soc/fu/div/core_stages.py +++ b/src/soc/fu/div/core_stages.py @@ -4,7 +4,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp from soc.decoder.power_fields import DecodeFields from soc.decoder.power_fieldsn import SignalBitRange diff --git a/src/soc/fu/div/formal/proof_main_stage.py b/src/soc/fu/div/formal/proof_main_stage.py index f3baa1b6..469127dd 100644 --- a/src/soc/fu/div/formal/proof_main_stage.py +++ b/src/soc/fu/div/formal/proof_main_stage.py @@ -16,7 +16,7 @@ from nmigen.cli import rtlil from soc.fu.logical.main_stage import LogicalMainStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp import unittest @@ -78,14 +78,14 @@ class Driver(Elaboratable): # main assertion of arithmetic operations with m.Switch(rec.insn_type): - with m.Case(InternalOp.OP_AND): + with m.Case(MicrOp.OP_AND): comb += Assert(dut.o.o == a & b) - with m.Case(InternalOp.OP_OR): + with m.Case(MicrOp.OP_OR): comb += Assert(dut.o.o == a | b) - with m.Case(InternalOp.OP_XOR): + with m.Case(MicrOp.OP_XOR): comb += Assert(dut.o.o == a ^ b) - with m.Case(InternalOp.OP_POPCNT): + with m.Case(MicrOp.OP_POPCNT): with m.If(rec.data_len == 8): comb += Assert(dut.o.o == self.popcount(a, 64)) with m.If(rec.data_len == 4): @@ -98,7 +98,7 @@ class Driver(Elaboratable): comb += Assert(dut.o.o[i*8:(i+1)*8] == self.popcount(a[i*8:(i+1)*8], 8)) - with m.Case(InternalOp.OP_PRTY): + with m.Case(MicrOp.OP_PRTY): with m.If(rec.data_len == 8): result = 0 for i in range(8): @@ -112,7 +112,7 @@ class Driver(Elaboratable): result_high = result_high ^ a[i*8 + 32] comb += Assert(dut.o.o[0:32] == result_low) comb += Assert(dut.o.o[32:64] == result_high) - with m.Case(InternalOp.OP_CNTZ): + with m.Case(MicrOp.OP_CNTZ): XO = dut.fields.FormX.XO[0:-1] with m.If(rec.is_32bit): m.submodules.pe32 = pe32 = PriorityEncoder(32) diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py index b5b286a6..5da7f6c7 100644 --- a/src/soc/fu/div/output_stage.py +++ b/src/soc/fu/div/output_stage.py @@ -9,7 +9,7 @@ from nmutil.pipemodbase import PipeModBase from soc.fu.logical.pipe_data import LogicalInputData from soc.fu.div.pipe_data import DivMulOutputData from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp from soc.decoder.power_fields import DecodeFields from soc.decoder.power_fieldsn import SignalBitRange @@ -115,7 +115,7 @@ class DivOutputStage(PipeModBase): with m.If(~ov): # result is valid (no overflow) with m.Switch(op.insn_type): - with m.Case(InternalOp.OP_DIVE): + with m.Case(MicrOp.OP_DIVE): with m.If(op.is_32bit): with m.If(op.is_signed): # matches POWER9's divweo behavior @@ -124,7 +124,7 @@ class DivOutputStage(PipeModBase): comb += o.eq(quotient_65[0:32].as_unsigned()) with m.Else(): comb += o.eq(quotient_65) - with m.Case(InternalOp.OP_DIV): + with m.Case(MicrOp.OP_DIV): with m.If(op.is_32bit): with m.If(op.is_signed): # matches POWER9's divwo behavior @@ -133,7 +133,7 @@ class DivOutputStage(PipeModBase): comb += o.eq(quotient_65[0:32].as_unsigned()) with m.Else(): comb += o.eq(quotient_65) - with m.Case(InternalOp.OP_MOD): + with m.Case(MicrOp.OP_MOD): with m.If(op.is_32bit): with m.If(op.is_signed): # matches POWER9's modsw behavior diff --git a/src/soc/fu/div/setup_stage.py b/src/soc/fu/div/setup_stage.py index 25daa201..11619fc7 100644 --- a/src/soc/fu/div/setup_stage.py +++ b/src/soc/fu/div/setup_stage.py @@ -5,7 +5,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase from soc.fu.div.pipe_data import DIVInputData from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp from soc.decoder.power_fields import DecodeFields from soc.decoder.power_fieldsn import SignalBitRange @@ -54,10 +54,10 @@ class DivSetupStage(PipeModBase): # check for absolute overflow condition (32/64) comb += self.o.dive_abs_ov64.eq((abs_dend >= abs_dor) - & (op.insn_type == InternalOp.OP_DIVE)) + & (op.insn_type == MicrOp.OP_DIVE)) comb += self.o.dive_abs_ov32.eq((abs_dend[0:32] >= abs_dor[0:32]) - & (op.insn_type == InternalOp.OP_DIVE)) + & (op.insn_type == MicrOp.OP_DIVE)) # set divisor based on 32/64 bit mode (must be absolute) comb += eq32(op.is_32bit, divisor_o, abs_dor) @@ -70,10 +70,10 @@ class DivSetupStage(PipeModBase): with m.Switch(op.insn_type): # div/mod takes straight (absolute) dividend - with m.Case(InternalOp.OP_DIV, InternalOp.OP_MOD): + with m.Case(MicrOp.OP_DIV, MicrOp.OP_MOD): comb += eq32(op.is_32bit, dividend_o, abs_dend) # extended div shifts dividend up - with m.Case(InternalOp.OP_DIVE): + with m.Case(MicrOp.OP_DIVE): with m.If(op.is_32bit): comb += dividend_o.eq(abs_dend[0:32] << 32) with m.Else(): diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index 65aa0801..204e4315 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -6,7 +6,7 @@ import unittest from soc.decoder.isa.caller import ISACaller, special_sprs from soc.decoder.power_decoder import (create_pdecode) from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn) +from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) from soc.decoder.selectable_int import SelectableInt from soc.simulator.program import Program from soc.decoder.isa.all import ISA diff --git a/src/soc/fu/ldst/ldst_input_record.py b/src/soc/fu/ldst/ldst_input_record.py index 2abf6c22..03851d43 100644 --- a/src/soc/fu/ldst/ldst_input_record.py +++ b/src/soc/fu/ldst/ldst_input_record.py @@ -1,6 +1,6 @@ from nmigen.hdl.rec import Record, Layout -from soc.decoder.power_enums import InternalOp, Function, LDSTMode +from soc.decoder.power_enums import MicrOp, Function, LDSTMode class CompLDSTOpSubset(Record): @@ -13,7 +13,7 @@ class CompLDSTOpSubset(Record): note: rc / oe is needed (later) for st*cx when it comes to setting OV/SO """ def __init__(self, name=None): - layout = (('insn_type', InternalOp), + layout = (('insn_type', MicrOp), ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), ('zero_a', 1), ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # for later diff --git a/src/soc/fu/ldst/test/test_pipe_caller.py b/src/soc/fu/ldst/test/test_pipe_caller.py index 6336f0ae..9e601e3e 100644 --- a/src/soc/fu/ldst/test/test_pipe_caller.py +++ b/src/soc/fu/ldst/test/test_pipe_caller.py @@ -6,7 +6,7 @@ import unittest from soc.decoder.isa.caller import special_sprs from soc.decoder.power_decoder import (create_pdecode) from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn) +from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) from soc.decoder.selectable_int import SelectableInt from soc.simulator.program import Program from soc.decoder.isa.all import ISA diff --git a/src/soc/fu/logical/formal/proof_input_stage.py b/src/soc/fu/logical/formal/proof_input_stage.py index 16f3df04..ab6e392e 100644 --- a/src/soc/fu/logical/formal/proof_input_stage.py +++ b/src/soc/fu/logical/formal/proof_input_stage.py @@ -9,7 +9,7 @@ from nmigen.cli import rtlil from soc.fu.alu.input_stage import ALUInputStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp import unittest @@ -57,7 +57,7 @@ class Driver(Elaboratable): comb += Assert(dut.o.a == a) with m.If(rec.imm_data.imm_ok & - ~(rec.insn_type == InternalOp.OP_RLC)): + ~(rec.insn_type == MicrOp.OP_RLC)): comb += Assert(dut.o.b == rec.imm_data.imm) with m.Else(): comb += Assert(dut.o.b == b) diff --git a/src/soc/fu/logical/formal/proof_main_stage.py b/src/soc/fu/logical/formal/proof_main_stage.py index de1c788d..e7cf254a 100644 --- a/src/soc/fu/logical/formal/proof_main_stage.py +++ b/src/soc/fu/logical/formal/proof_main_stage.py @@ -16,7 +16,7 @@ from nmigen.cli import rtlil from soc.fu.logical.main_stage import LogicalMainStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp import unittest @@ -82,14 +82,14 @@ class Driver(Elaboratable): # main assertion of arithmetic operations with m.Switch(rec.insn_type): - with m.Case(InternalOp.OP_AND): + with m.Case(MicrOp.OP_AND): comb += Assert(o == a & b) - with m.Case(InternalOp.OP_OR): + with m.Case(MicrOp.OP_OR): comb += Assert(o == a | b) - with m.Case(InternalOp.OP_XOR): + with m.Case(MicrOp.OP_XOR): comb += Assert(o == a ^ b) - with m.Case(InternalOp.OP_POPCNT): + with m.Case(MicrOp.OP_POPCNT): with m.If(rec.data_len == 8): comb += Assert(o == simple_popcount(a, 64)) with m.If(rec.data_len == 4): @@ -101,7 +101,7 @@ class Driver(Elaboratable): slc = slice(i*8, (i+1)*8) comb += Assert(o[slc] == simple_popcount(a[slc], 8)) - with m.Case(InternalOp.OP_PRTY): + with m.Case(MicrOp.OP_PRTY): with m.If(rec.data_len == 8): result = 0 for i in range(8): @@ -116,7 +116,7 @@ class Driver(Elaboratable): comb += Assert(o[0:32] == result_low) comb += Assert(o[32:64] == result_high) - with m.Case(InternalOp.OP_CNTZ): + with m.Case(MicrOp.OP_CNTZ): XO = dut.fields.FormX.XO[0:-1] with m.If(rec.is_32bit): m.submodules.pe32 = pe32 = PriorityEncoder(32) @@ -145,7 +145,7 @@ class Driver(Elaboratable): comb += pe64.i.eq(a[0:64][::-1]) comb += Assert(o == peo64) - with m.Case(InternalOp.OP_CMPB): + with m.Case(MicrOp.OP_CMPB): for i in range(8): slc = slice(i*8, (i+1)*8) with m.If(a[slc] == b[slc]): @@ -153,7 +153,7 @@ class Driver(Elaboratable): with m.Else(): comb += Assert(o[slc] == 0) - with m.Case(InternalOp.OP_BPERM): + with m.Case(MicrOp.OP_BPERM): # note that this is a copy of the beautifully-documented # proof_bpermd.py comb += Assert(o[8:] == 0) diff --git a/src/soc/fu/logical/logical_input_record.py b/src/soc/fu/logical/logical_input_record.py index 92de6388..7040f0e5 100644 --- a/src/soc/fu/logical/logical_input_record.py +++ b/src/soc/fu/logical/logical_input_record.py @@ -1,6 +1,6 @@ from nmigen.hdl.rec import Record, Layout -from soc.decoder.power_enums import InternalOp, Function, CryIn +from soc.decoder.power_enums import MicrOp, Function, CryIn class CompLogicalOpSubset(Record): @@ -11,7 +11,7 @@ class CompLogicalOpSubset(Record): grab subsets. """ def __init__(self, name=None): - layout = (('insn_type', InternalOp), + layout = (('insn_type', MicrOp), ('fn_unit', Function), ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), ('rc', Layout((("rc", 1), ("rc_ok", 1)))), diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py index 1815431a..925455b3 100644 --- a/src/soc/fu/logical/main_stage.py +++ b/src/soc/fu/logical/main_stage.py @@ -13,7 +13,7 @@ from soc.fu.logical.bpermd import Bpermd from soc.fu.logical.popcount import Popcount from soc.fu.logical.pipe_data import LogicalOutputData from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp from soc.decoder.power_fields import DecodeFields from soc.decoder.power_fieldsn import SignalBitRange @@ -47,15 +47,15 @@ class LogicalMainStage(PipeModBase): with m.Switch(op.insn_type): ###### AND, OR, XOR ####### - with m.Case(InternalOp.OP_AND): + with m.Case(MicrOp.OP_AND): comb += o.data.eq(a & b) - with m.Case(InternalOp.OP_OR): + with m.Case(MicrOp.OP_OR): comb += o.data.eq(a | b) - with m.Case(InternalOp.OP_XOR): + with m.Case(MicrOp.OP_XOR): comb += o.data.eq(a ^ b) ###### cmpb ####### - with m.Case(InternalOp.OP_CMPB): + with m.Case(MicrOp.OP_CMPB): l = [] for i in range(8): slc = slice(i*8, (i+1)*8) @@ -63,14 +63,14 @@ class LogicalMainStage(PipeModBase): comb += o.data.eq(Cat(*l)) ###### popcount ####### - with m.Case(InternalOp.OP_POPCNT): + with m.Case(MicrOp.OP_POPCNT): comb += popcount.a.eq(a) comb += popcount.b.eq(b) comb += popcount.data_len.eq(op.data_len) comb += o.data.eq(popcount.o) ###### parity ####### - with m.Case(InternalOp.OP_PRTY): + with m.Case(MicrOp.OP_PRTY): # strange instruction which XORs together the LSBs of each byte par0 = Signal(reset_less=True) par1 = Signal(reset_less=True) @@ -83,7 +83,7 @@ class LogicalMainStage(PipeModBase): comb += o[32].eq(par1) ###### cntlz ####### - with m.Case(InternalOp.OP_CNTZ): + with m.Case(MicrOp.OP_CNTZ): XO = self.fields.FormX.XO[0:-1] count_right = Signal(reset_less=True) comb += count_right.eq(XO[-1]) @@ -102,7 +102,7 @@ class LogicalMainStage(PipeModBase): comb += o.data.eq(Mux(op.is_32bit, clz.lz-32, clz.lz)) ###### bpermd ####### - with m.Case(InternalOp.OP_BPERM): + with m.Case(MicrOp.OP_BPERM): comb += bpermd.rs.eq(a) comb += bpermd.rb.eq(b) comb += o.data.eq(bpermd.ra) diff --git a/src/soc/fu/logical/output_stage.py b/src/soc/fu/logical/output_stage.py index 7f833b3e..a985511f 100644 --- a/src/soc/fu/logical/output_stage.py +++ b/src/soc/fu/logical/output_stage.py @@ -6,7 +6,7 @@ from nmutil.pipemodbase import PipeModBase from soc.fu.common_output_stage import CommonOutputStage from soc.fu.logical.pipe_data import LogicalInputData, LogicalOutputData from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp class LogicalOutputStage(CommonOutputStage): diff --git a/src/soc/fu/mul/formal/proof_main_stage.py b/src/soc/fu/mul/formal/proof_main_stage.py index 0e44e5e8..890475a6 100644 --- a/src/soc/fu/mul/formal/proof_main_stage.py +++ b/src/soc/fu/mul/formal/proof_main_stage.py @@ -10,7 +10,7 @@ from nmigen.cli import rtlil from soc.fu.shift_rot.main_stage import ShiftRotMainStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp import unittest @@ -69,14 +69,14 @@ class Driver(Elaboratable): # main assertion of arithmetic operations with m.Switch(rec.insn_type): - with m.Case(InternalOp.OP_SHL): + with m.Case(MicrOp.OP_SHL): comb += Assume(ra == 0) with m.If(rec.is_32bit): comb += Assert(o[0:32] == ((a << b[0:6]) & 0xffffffff)) comb += Assert(o[32:64] == 0) with m.Else(): comb += Assert(o == ((a << b[0:7]) & ((1 << 64)-1))) - with m.Case(InternalOp.OP_SHR): + with m.Case(MicrOp.OP_SHR): comb += Assume(ra == 0) with m.If(~rec.is_signed): with m.If(rec.is_32bit): diff --git a/src/soc/fu/mul/mul_input_record.py b/src/soc/fu/mul/mul_input_record.py index 51e7352e..8d85d913 100644 --- a/src/soc/fu/mul/mul_input_record.py +++ b/src/soc/fu/mul/mul_input_record.py @@ -1,6 +1,6 @@ from nmigen.hdl.rec import Record, Layout -from soc.decoder.power_enums import InternalOp, Function, CryIn +from soc.decoder.power_enums import MicrOp, Function, CryIn class CompMULOpSubset(Record): @@ -11,7 +11,7 @@ class CompMULOpSubset(Record): grab subsets. """ def __init__(self, name=None): - layout = (('insn_type', InternalOp), + layout = (('insn_type', MicrOp), ('fn_unit', Function), ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data diff --git a/src/soc/fu/mul/post_stage.py b/src/soc/fu/mul/post_stage.py index 9f3d6963..0fc71804 100644 --- a/src/soc/fu/mul/post_stage.py +++ b/src/soc/fu/mul/post_stage.py @@ -5,7 +5,7 @@ from nmutil.pipemodbase import PipeModBase from soc.fu.div.pipe_data import DivMulOutputData from soc.fu.mul.pipe_data import MulOutputData from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp class MulMainStage3(PipeModBase): @@ -38,10 +38,10 @@ class MulMainStage3(PipeModBase): # OP_MUL_nnn - select hi32/hi64/lo64 from result with m.Switch(op.insn_type): # hi-32 replicated twice - with m.Case(InternalOp.OP_MUL_H32): + with m.Case(MicrOp.OP_MUL_H32): comb += o.data.eq(Repl(mul_o[32:64], 2)) # hi-64 - with m.Case(InternalOp.OP_MUL_H64): + with m.Case(MicrOp.OP_MUL_H64): comb += o.data.eq(mul_o[64:128]) # lo-64 - overflow with m.Default(): diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py index b85c0e04..56d3fed6 100644 --- a/src/soc/fu/mul/test/test_pipe_caller.py +++ b/src/soc/fu/mul/test/test_pipe_caller.py @@ -6,7 +6,7 @@ import unittest from soc.decoder.isa.caller import ISACaller, special_sprs from soc.decoder.power_decoder import (create_pdecode) from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn) +from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) from soc.decoder.selectable_int import SelectableInt from soc.simulator.program import Program from soc.decoder.isa.all import ISA diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py index 9b083a54..685b221f 100644 --- a/src/soc/fu/shift_rot/formal/proof_main_stage.py +++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py @@ -14,7 +14,7 @@ from nmigen.cli import rtlil from soc.fu.shift_rot.main_stage import ShiftRotMainStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp import unittest @@ -74,7 +74,7 @@ class Driver(Elaboratable): # main assertion of arithmetic operations with m.Switch(rec.insn_type): - with m.Case(InternalOp.OP_SHL): + with m.Case(MicrOp.OP_SHL): comb += Assume(ra == 0) with m.If(rec.is_32bit): comb += Assert(o[0:32] == ((a << b[0:6]) & 0xffffffff)) @@ -82,7 +82,7 @@ class Driver(Elaboratable): with m.Else(): comb += Assert(o == ((a << b[0:7]) & ((1 << 64)-1))) - with m.Case(InternalOp.OP_SHR): + with m.Case(MicrOp.OP_SHR): comb += Assume(ra == 0) with m.If(~rec.is_signed): with m.If(rec.is_32bit): @@ -97,11 +97,11 @@ class Driver(Elaboratable): with m.Else(): comb += Assert(o == (a_signed >> b[0:7])) #TODO - with m.Case(InternalOp.OP_RLC): + with m.Case(MicrOp.OP_RLC): pass - with m.Case(InternalOp.OP_RLCR): + with m.Case(MicrOp.OP_RLCR): pass - with m.Case(InternalOp.OP_RLCL): + with m.Case(MicrOp.OP_RLCL): pass with m.Default(): comb += o_ok.eq(0) diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py index ae9d59fb..f27134c4 100644 --- a/src/soc/fu/shift_rot/main_stage.py +++ b/src/soc/fu/shift_rot/main_stage.py @@ -7,7 +7,7 @@ from nmutil.pipemodbase import PipeModBase from soc.fu.logical.pipe_data import LogicalOutputData from soc.fu.shift_rot.pipe_data import ShiftRotInputData from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp from soc.fu.shift_rot.rotator import Rotator from soc.decoder.power_fields import DecodeFields @@ -62,11 +62,11 @@ class ShiftRotMainStage(PipeModBase): # instruction rotate type mode = Signal(3, reset_less=True) with m.Switch(op.insn_type): - with m.Case(InternalOp.OP_SHL): comb += mode.eq(0b000) - with m.Case(InternalOp.OP_SHR): comb += mode.eq(0b001) # R-shift - with m.Case(InternalOp.OP_RLC): comb += mode.eq(0b110) # clear LR - with m.Case(InternalOp.OP_RLCL): comb += mode.eq(0b010) # clear L - with m.Case(InternalOp.OP_RLCR): comb += mode.eq(0b100) # clear R + with m.Case(MicrOp.OP_SHL): comb += mode.eq(0b000) + with m.Case(MicrOp.OP_SHR): comb += mode.eq(0b001) # R-shift + with m.Case(MicrOp.OP_RLC): comb += mode.eq(0b110) # clear LR + with m.Case(MicrOp.OP_RLCL): comb += mode.eq(0b010) # clear L + with m.Case(MicrOp.OP_RLCR): comb += mode.eq(0b100) # clear R with m.Default(): comb += o.ok.eq(0) # otherwise disable diff --git a/src/soc/fu/shift_rot/sr_input_record.py b/src/soc/fu/shift_rot/sr_input_record.py index da055538..6b0c7eb9 100644 --- a/src/soc/fu/shift_rot/sr_input_record.py +++ b/src/soc/fu/shift_rot/sr_input_record.py @@ -1,6 +1,6 @@ from nmigen.hdl.rec import Record, Layout -from soc.decoder.power_enums import InternalOp, Function, CryIn +from soc.decoder.power_enums import MicrOp, Function, CryIn class CompSROpSubset(Record): @@ -11,7 +11,7 @@ class CompSROpSubset(Record): grab subsets. """ def __init__(self, name=None): - layout = (('insn_type', InternalOp), + layout = (('insn_type', MicrOp), ('fn_unit', Function), ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), ('rc', Layout((("rc", 1), ("rc_ok", 1)))), diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py index e2234e67..f4261b62 100644 --- a/src/soc/fu/spr/main_stage.py +++ b/src/soc/fu/spr/main_stage.py @@ -7,7 +7,7 @@ from nmigen import (Module, Signal, Cat) from nmutil.pipemodbase import PipeModBase from soc.fu.spr.pipe_data import SPRInputData, SPROutputData -from soc.decoder.power_enums import InternalOp, SPR, XER_bits +from soc.decoder.power_enums import MicrOp, SPR, XER_bits from soc.decoder.power_fields import DecodeFields from soc.decoder.power_fieldsn import SignalBitRange @@ -45,7 +45,7 @@ class SPRMainStage(PipeModBase): # TODO: some #defines for the bits n stuff. with m.Switch(op.insn_type): #### MTSPR #### - with m.Case(InternalOp.OP_MTSPR): + with m.Case(MicrOp.OP_MTSPR): with m.Switch(spr): # fast SPRs first with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1): @@ -67,7 +67,7 @@ class SPRMainStage(PipeModBase): # slow SPRs TODO # move from SPRs - with m.Case(InternalOp.OP_MFSPR): + with m.Case(MicrOp.OP_MFSPR): comb += o.ok.eq(1) with m.Switch(spr): # fast SPRs first diff --git a/src/soc/fu/spr/spr_input_record.py b/src/soc/fu/spr/spr_input_record.py index 8dfce155..84599a98 100644 --- a/src/soc/fu/spr/spr_input_record.py +++ b/src/soc/fu/spr/spr_input_record.py @@ -1,6 +1,6 @@ from nmigen.hdl.rec import Record, Layout -from soc.decoder.power_enums import (InternalOp, Function) +from soc.decoder.power_enums import (MicrOp, Function) class CompSPROpSubset(Record): @@ -11,7 +11,7 @@ class CompSPROpSubset(Record): grab subsets. """ def __init__(self, name=None): - layout = (('insn_type', InternalOp), + layout = (('insn_type', MicrOp), ('fn_unit', Function), ('insn', 32), ('is_32bit', 1), diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py index d879d439..c05ea950 100644 --- a/src/soc/fu/spr/test/test_pipe_caller.py +++ b/src/soc/fu/spr/test/test_pipe_caller.py @@ -6,7 +6,7 @@ import unittest from soc.decoder.isa.caller import ISACaller, special_sprs from soc.decoder.power_decoder import (create_pdecode) from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn) +from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) from soc.decoder.selectable_int import SelectableInt from soc.simulator.program import Program from soc.decoder.isa.all import ISA diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 0ddb2823..769ae863 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -14,7 +14,7 @@ from nmutil.pipemodbase import PipeModBase from nmutil.extend import exts from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData from soc.fu.branch.main_stage import br_ext -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp from soc.decoder.power_fields import DecodeFields from soc.decoder.power_fieldsn import SignalBitRange @@ -146,7 +146,7 @@ class TrapMainStage(PipeModBase): # TODO: some #defines for the bits n stuff. with m.Switch(op.insn_type): #### trap #### - with m.Case(InternalOp.OP_TRAP): + with m.Case(MicrOp.OP_TRAP): # trap instructions (tw, twi, td, tdi) with m.If(should_trap): # generate trap-type program interrupt @@ -164,7 +164,7 @@ class TrapMainStage(PipeModBase): comb += srr1_o.data[PI.ILLEG].eq(1) # move to MSR - with m.Case(InternalOp.OP_MTMSRD, InternalOp.OP_MTMSR): + with m.Case(MicrOp.OP_MTMSRD, MicrOp.OP_MTMSR): L = self.fields.FormX.L[0:-1] # X-Form field L # start with copy of msr comb += msr_o.eq(msr_i) @@ -181,12 +181,12 @@ class TrapMainStage(PipeModBase): comb += msr_o.ok.eq(1) # move from MSR - with m.Case(InternalOp.OP_MFMSR): + with m.Case(MicrOp.OP_MFMSR): # TODO: some of the bits need zeroing? apparently not comb += o.data.eq(msr_i) comb += o.ok.eq(1) - with m.Case(InternalOp.OP_RFID): + with m.Case(MicrOp.OP_RFID): # XXX f_out.virt_mode <= b_in(MSR.IR) or b_in(MSR.PR); # XXX f_out.priv_mode <= not b_in(MSR.PR); @@ -210,7 +210,7 @@ class TrapMainStage(PipeModBase): comb += msr_o.ok.eq(1) # OP_SC - with m.Case(InternalOp.OP_SC): + with m.Case(MicrOp.OP_SC): # TODO: scv must generate illegal instruction. this is # the decoder's job, not ours, here. @@ -218,7 +218,7 @@ class TrapMainStage(PipeModBase): self.trap(m, 0xc00, cia_i+4) # TODO (later) - #with m.Case(InternalOp.OP_ADDPCIS): + #with m.Case(MicrOp.OP_ADDPCIS): # pass comb += self.o.ctx.eq(self.i.ctx) diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index 552be8f4..44fbba6a 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -6,7 +6,7 @@ import unittest from soc.decoder.isa.caller import ISACaller, special_sprs from soc.decoder.power_decoder import (create_pdecode) from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn) +from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) from soc.decoder.selectable_int import SelectableInt from soc.simulator.program import Program from soc.decoder.isa.all import ISA diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py index 9c9a53c4..84715f82 100644 --- a/src/soc/fu/trap/trap_input_record.py +++ b/src/soc/fu/trap/trap_input_record.py @@ -1,6 +1,6 @@ from nmigen.hdl.rec import Record, Layout -from soc.decoder.power_enums import (InternalOp, Function) +from soc.decoder.power_enums import (MicrOp, Function) class CompTrapOpSubset(Record): @@ -11,7 +11,7 @@ class CompTrapOpSubset(Record): grab subsets. """ def __init__(self, name=None): - layout = (('insn_type', InternalOp), + layout = (('insn_type', MicrOp), ('fn_unit', Function), ('insn', 32), ('is_32bit', 1), diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index ceac442c..740cc990 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -32,7 +32,7 @@ from soc.decoder.power_decoder2 import PowerDecode2 from soc.decoder.decode2execute1 import Data from soc.experiment.l0_cache import TstL0CacheBuffer # test only from soc.config.test.test_loadstore import TestMemPspec -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp import operator @@ -157,10 +157,10 @@ class NonProductionCore(Elaboratable): with m.If(can_run): with m.Switch(dec2.e.do.insn_type): # check for ATTN: halt if true - with m.Case(InternalOp.OP_ATTN): + with m.Case(MicrOp.OP_ATTN): m.d.sync += core_stopped.eq(1) - with m.Case(InternalOp.OP_NOP): + with m.Case(MicrOp.OP_NOP): sync += counter.eq(2) comb += self.busy_o.eq(1) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 2d7ae5e0..0f90943d 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -24,7 +24,7 @@ from soc.regfile.regfiles import FastRegs from soc.simple.core import NonProductionCore from soc.config.test.test_loadstore import TestMemPspec from soc.config.ifetch import ConfigFetchUnit -from soc.decoder.power_enums import InternalOp +from soc.decoder.power_enums import MicrOp class TestIssuer(Elaboratable): @@ -142,7 +142,7 @@ class TestIssuer(Elaboratable): with m.If(core.core_terminated_o): m.next = "IDLE" # back to idle, immediately (OP_ATTN) with m.Else(): - with m.If(insn_type != InternalOp.OP_NOP): + with m.If(insn_type != MicrOp.OP_NOP): comb += core_ivalid_i.eq(1) # instruction is valid comb += core_opcode_i.eq(ilatch) # actual opcode with m.If(self.fast_nia.wen): diff --git a/src/soc/simulator/test_div_sim.py b/src/soc/simulator/test_div_sim.py index a6f18601..04278c30 100644 --- a/src/soc/simulator/test_div_sim.py +++ b/src/soc/simulator/test_div_sim.py @@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay, Settle from nmigen.test.utils import FHDLTestCase import unittest from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, InternalOp, +from soc.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, single_bit_flags, Form, SPR, diff --git a/src/soc/simulator/test_helloworld_sim.py b/src/soc/simulator/test_helloworld_sim.py index fb5ed768..2ff1e006 100644 --- a/src/soc/simulator/test_helloworld_sim.py +++ b/src/soc/simulator/test_helloworld_sim.py @@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay, Settle from nmigen.test.utils import FHDLTestCase import unittest from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, InternalOp, +from soc.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, single_bit_flags, Form, SPR, diff --git a/src/soc/simulator/test_mul_sim.py b/src/soc/simulator/test_mul_sim.py index 00c51a4e..ef117c3a 100644 --- a/src/soc/simulator/test_mul_sim.py +++ b/src/soc/simulator/test_mul_sim.py @@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay, Settle from nmigen.test.utils import FHDLTestCase import unittest from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, InternalOp, +from soc.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, single_bit_flags, Form, SPR, diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py index d1e65f4f..dae60cea 100644 --- a/src/soc/simulator/test_sim.py +++ b/src/soc/simulator/test_sim.py @@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay, Settle from nmigen.test.utils import FHDLTestCase import unittest from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, InternalOp, +from soc.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, single_bit_flags, Form, SPR, diff --git a/src/soc/simulator/test_trap_sim.py b/src/soc/simulator/test_trap_sim.py index dfb4faa2..d535cf1a 100644 --- a/src/soc/simulator/test_trap_sim.py +++ b/src/soc/simulator/test_trap_sim.py @@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay, Settle from nmigen.test.utils import FHDLTestCase import unittest from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, InternalOp, +from soc.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, single_bit_flags, Form, SPR, -- 2.30.2