From d2c5f22e812cd09383c44cd4acb864e77b4ae5ee Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 25 Jul 2020 21:41:15 +0100 Subject: [PATCH] hilarious. only just caught a bug where overflow was being taken from Rc --- src/soc/decoder/isa/caller.py | 9 ++++++--- src/soc/decoder/power_fields.py | 2 +- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index c7d0784f..9053d268 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -543,14 +543,16 @@ class ISACaller: rc_en = yield self.dec2.e.do.rc.data rc_ok = yield self.dec2.e.do.rc.ok # grrrr have to special-case MUL op (see DecodeOE) - print("ov en rc en", ov_ok, ov_en, rc_ok, rc_en, int_op) + print("ov %d en %d rc %d en %d op %d" % \ + (ov_ok, ov_en, rc_ok, rc_en, int_op)) if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]: print("mul op") if rc_en & rc_ok: asmop += "." else: - if ov_en & ov_ok: - asmop += "." + if not asmop.endswith("."): # don't add "." to "andis." + if rc_en & rc_ok: + asmop += "." lk = yield self.dec2.e.do.lk if lk: asmop += "l" @@ -626,6 +628,7 @@ class ISACaller: illegal = name != asmop if illegal: + print ("illegal", name, asmop) self.TRAP(0x700, PIb.ILLEG) self.namespace['NIA'] = self.trap_nia self.pc.update(self.namespace) diff --git a/src/soc/decoder/power_fields.py b/src/soc/decoder/power_fields.py index f4bdf161..02c2dc70 100644 --- a/src/soc/decoder/power_fields.py +++ b/src/soc/decoder/power_fields.py @@ -147,7 +147,7 @@ class DecodeFields: "LK": self.FormI.LK, "AA": self.FormB.AA, "Rc": self.FormX.Rc, - "OE": self.FormXO.Rc, + "OE": self.FormXO.OE, "BD": self.FormB.BD, "BF": self.FormX.BF, "CR": self.FormXL.XO, -- 2.30.2