From e78f98bb1941092c35b1ffb39c857accb250af13 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Thu, 7 May 2020 14:13:24 -0400 Subject: [PATCH] Fix test_mtcrf. Test has been verified against qemu --- src/soc/decoder/isa/test_caller.py | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index 14beb2a7..1c7cb9a0 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -150,16 +150,19 @@ class DecoderTestCase(FHDLTestCase): def test_mtcrf(self): for i in range(4): - # 0x7654 gives expected (3+4) (2+4) (1+4) (0+4) for i=3,2,1,0 - lst = ["addi %d, 0, 0x7654" % (i+1), - "mtcrf %d, %d" % (1 << i, i+1), + # 0x76540000 gives expected (3+4) (2+4) (1+4) (0+4) for + # i=0, 1, 2, 3 + # The positions of the CR fields have been verified using + # QEMU and 'cmp crx, a, b' instructions + lst = ["addis 1, 0, 0x7654", + "mtcrf %d, 1" % (1 << (7-i)), ] with Program(lst) as program: sim = self.run_tst_program(program) print("cr", sim.cr) - expected = (i+4) + expected = (7-i) # check CR itself - self.assertEqual(sim.cr, SelectableInt(expected << (i*4), 32)) + self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 32)) # check CR[0]/1/2/3 as well print("cr%d", sim.crl[i]) self.assertTrue(SelectableInt(expected, 4) == sim.crl[i]) -- 2.30.2