From e84327af6b5060ca0492a1a5c3817edfba25bbc8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 5 Mar 2019 10:55:18 +0000 Subject: [PATCH] remove whitespace --- TLB/test/test_cam.py | 38 +++++++++---------- TLB/test/test_cam_entry.py | 46 +++++++++++------------ TLB/test/test_walking_priority_encoder.py | 4 +- 3 files changed, 44 insertions(+), 44 deletions(-) diff --git a/TLB/test/test_cam.py b/TLB/test/test_cam.py index 00474feb..c2c3bdaf 100644 --- a/TLB/test/test_cam.py +++ b/TLB/test/test_cam.py @@ -13,26 +13,26 @@ def set_cam(dut, e, we, a, d): yield dut.write_enable.eq(we) yield dut.address_in.eq(a) yield dut.data_in.eq(d) - yield - + yield + def check_single_match(dut, dh, op): out_sm = yield dut.single_match if op == 0: assert_eq("Single Match", out_sm, dh) else: assert_ne("Single Match", out_sm, dh) - + def check_match_address(dut, ma, op): out_ma = yield dut.match_address if op == 0: assert_eq("Match Address", out_ma, ma) else: - assert_ne("Match Address", out_ma, ma) - + assert_ne("Match Address", out_ma, ma) + def check_all(dut, single_match, match_address, sm_op, ma_op): yield from check_single_match(dut, single_match, sm_op) yield from check_match_address(dut, match_address, ma_op) - + def testbench(dut): # NA @@ -43,7 +43,7 @@ def testbench(dut): single_match = 0 yield from set_cam(dut, enable, write_enable, address, data) yield from check_single_match(dut, single_match, 0) - + # Read Miss # Note that the default starting entry data bits are all 0 enable = 1 @@ -53,8 +53,8 @@ def testbench(dut): single_match = 0 yield from set_cam(dut, enable, write_enable, address, data) yield - yield from check_single_match(dut, single_match, 0) - + yield from check_single_match(dut, single_match, 0) + # Write Entry 0 enable = 1 write_enable = 1 @@ -63,8 +63,8 @@ def testbench(dut): single_match = 0 yield from set_cam(dut, enable, write_enable, address, data) yield - yield from check_single_match(dut, single_match, 0) - + yield from check_single_match(dut, single_match, 0) + # Read Hit Entry 0 enable = 1 write_enable = 0 @@ -73,8 +73,8 @@ def testbench(dut): single_match = 1 yield from set_cam(dut, enable, write_enable, address, data) yield - yield from check_all(dut, single_match, address, 0, 0) - + yield from check_all(dut, single_match, address, 0, 0) + # Search Hit enable = 1 write_enable = 0 @@ -84,7 +84,7 @@ def testbench(dut): yield from set_cam(dut, enable, write_enable, address, data) yield yield from check_all(dut, single_match, address, 0, 0) - + # Search Miss enable = 1 write_enable = 0 @@ -93,12 +93,12 @@ def testbench(dut): single_match = 0 yield from set_cam(dut, enable, write_enable, address, data) yield - yield from check_single_match(dut, single_match, 0) - - yield - + yield from check_single_match(dut, single_match, 0) + + yield + if __name__ == "__main__": dut = Cam(4, 4) run_simulation(dut, testbench(dut), vcd_name="Waveforms/cam_test.vcd") - print("Cam Unit Test Success") \ No newline at end of file + print("Cam Unit Test Success") diff --git a/TLB/test/test_cam_entry.py b/TLB/test/test_cam_entry.py index 9fcc6609..1ed48f50 100644 --- a/TLB/test/test_cam_entry.py +++ b/TLB/test/test_cam_entry.py @@ -6,13 +6,13 @@ from nmigen.compat.sim import run_simulation from test_helper import assert_eq, assert_ne from CamEntry import CamEntry - + # This function allows for the easy setting of values to the Cam Entry # unless the key is incorrect # Arguments: # dut: The CamEntry being tested # c (command): NA (0), Read (1), Write (2), Reserve (3) -# d (data): The data to be set +# d (data): The data to be set def set_cam_entry(dut, c, d): # Write desired values yield dut.command.eq(c) @@ -20,9 +20,9 @@ def set_cam_entry(dut, c, d): yield # Reset all lines yield dut.command.eq(0) - yield dut.data_in.eq(0) - yield - + yield dut.data_in.eq(0) + yield + # Checks the data state of the CAM entry # Arguments: # dut: The CamEntry being tested @@ -33,20 +33,20 @@ def check_data(dut, d, op): if op == 0: assert_eq("Data", out_d, d) else: - assert_ne("Data", out_d, d) - + assert_ne("Data", out_d, d) + # Checks the match state of the CAM entry # Arguments: # dut: The CamEntry being tested -# m (Match): The expected match +# m (Match): The expected match # op (Operation): (0 => ==), (1 => !=) def check_match(dut, m, op): out_m = yield dut.match if op == 0: assert_eq("Match", out_m, m) else: - assert_ne("Match", out_m, m) - + assert_ne("Match", out_m, m) + # Checks the state of the CAM entry # Arguments: # dut: The CamEntry being tested @@ -57,7 +57,7 @@ def check_match(dut, m, op): def check_all(dut, d, m, d_op, m_op): yield from check_data(dut, d, d_op) yield from check_match(dut, m, m_op) - + # This testbench goes through the paces of testing the CamEntry module # It is done by writing and then reading various combinations of key/data pairs # and reading the results with varying keys to verify the resulting stored @@ -69,46 +69,46 @@ def testbench(dut): match = 0 yield from set_cam_entry(dut, command, data) yield from check_all(dut, data, match, 0, 0) - + # Check read miss command = 1 data = 2 match = 0 yield from set_cam_entry(dut, command, data) - yield from check_all(dut, data, match, 1, 0) - + yield from check_all(dut, data, match, 1, 0) + # Check read hit command = 1 data = 1 match = 1 yield from set_cam_entry(dut, command, data) - yield from check_all(dut, data, match, 0, 0) - + yield from check_all(dut, data, match, 0, 0) + # Check overwrite command = 2 data = 5 match = 0 yield from set_cam_entry(dut, command, data) yield - yield from check_all(dut, data, match, 0, 0) - + yield from check_all(dut, data, match, 0, 0) + # Check read hit command = 1 data = 5 match = 1 yield from set_cam_entry(dut, command, data) - yield from check_all(dut, data, match, 0, 0) - + yield from check_all(dut, data, match, 0, 0) + # Check reset command = 3 data = 0 match = 0 yield from set_cam_entry(dut, command, data) - yield from check_all(dut, data, match, 0, 0) - + yield from check_all(dut, data, match, 0, 0) + # Extra clock cycle for waveform yield - + if __name__ == "__main__": dut = CamEntry(4) run_simulation(dut, testbench(dut), vcd_name="Waveforms/cam_entry_test.vcd") diff --git a/TLB/test/test_walking_priority_encoder.py b/TLB/test/test_walking_priority_encoder.py index 6f1faa04..370545b7 100644 --- a/TLB/test/test_walking_priority_encoder.py +++ b/TLB/test/test_walking_priority_encoder.py @@ -24,9 +24,9 @@ def testbench(dut): yield yield output = yield dut.output - #assert_eq("Output", output, 1) + #assert_eq("Output", output, 1) if __name__ == "__main__": dut = WalkingPriorityEncoder(4) run_simulation(dut, testbench(dut), vcd_name="Waveforms/cam_walking_priority_encoder.vcd") - print("WalkingPriorityEncoder Unit Test Success") \ No newline at end of file + print("WalkingPriorityEncoder Unit Test Success") -- 2.30.2