From ec705aafce1ceefe398f06cae7564b9e4b4620e6 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Fri, 15 May 2020 10:21:52 -0400 Subject: [PATCH] Add test for prtyw pseudocode --- src/soc/decoder/isa/test_caller.py | 10 ++++++++++ src/soc/decoder/selectable_int.py | 5 +++++ 2 files changed, 15 insertions(+) diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index 4050fab3..10db874c 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -230,6 +230,16 @@ class DecoderTestCase(FHDLTestCase): sim = self.run_tst_program(program, initial_regs) self.assertEqual(sim.gpr(3), SelectableInt(0xdf95fd81bc0, 64)) + def test_prty(self): + lst = ["prtyw 2, 1"] + initial_regs = [0] * 32 + initial_regs[1] = 0xdeadbeeecaffc0de + with Program(lst) as program: + sim = self.run_tst_program(program, initial_regs) + self.assertEqual(sim.gpr(2), SelectableInt(0x100000001, 64)) + + + def test_mtcrf(self): for i in range(4): # 0x76540000 gives expected (3+4) (2+4) (1+4) (0+4) for diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py index a275de07..ce7c2ebb 100644 --- a/src/soc/decoder/selectable_int.py +++ b/src/soc/decoder/selectable_int.py @@ -216,6 +216,11 @@ class SelectableInt: assert b.bits == self.bits return SelectableInt(self.value ^ b.value, self.bits) + def __rxor__(self, b): + b = check_extsign(self, b) + assert b.bits == self.bits + return SelectableInt(self.value ^ b.value, self.bits) + def __invert__(self): return SelectableInt(~self.value, self.bits) -- 2.30.2