From edd44e1f7a25f4b2060bcfd5cec0e186ebd89cd3 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Wed, 11 Nov 2020 19:51:41 +0100 Subject: [PATCH] dcbz and tlbie first test, still incomplete --- src/soc/fu/mmu/test/test_pipe_caller.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py index 2290597f..373cd658 100644 --- a/src/soc/fu/mmu/test/test_pipe_caller.py +++ b/src/soc/fu/mmu/test/test_pipe_caller.py @@ -85,8 +85,8 @@ class MMUTestCase(TestAccumulatorBase): #"mfspr 27, 4", # SRR1 #next two need to be added to the simulator - #"dcbz 5,6" # Data Cache Block set to Zero - RA,RB - #"tlbie 1,1,1,1,1" + #"dcbz 5,6" # Data Cache Block set to Zero - RA,RB (hangs) + "tlbie 1,1,1,1,1" #does not hang -- not verified yet ] initial_regs = [0] * 32 -- 2.30.2