From fdf3fe5479f77e28c524b2f811e18ff7a6697477 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 29 Jan 2021 22:46:43 +0000 Subject: [PATCH] add SVP64 RM (Remap) Record --- src/soc/sv/svp64.py | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 src/soc/sv/svp64.py diff --git a/src/soc/sv/svp64.py b/src/soc/sv/svp64.py new file mode 100644 index 00000000..c0aa7bb7 --- /dev/null +++ b/src/soc/sv/svp64.py @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: LGPLv3+ +# Copyright (C) 2021 Luke Kenneth Casson Leighton +# Funded by NLnet http://nlnet.nl +"""SVP64 RM (Remap) Record. + +https://libre-soc.org/openpower/sv/svp64/ + +| Field Name | Field bits | Description | +|------------|------------|----------------------------------------| +| MASKMODE | `0` | Execution (predication) Mask Kind | +| MASK | `1:3` | Execution Mask | +| ELWIDTH | `4:5` | Element Width | +| ELWIDTH_SRC | `6:7` | Element Width for Source | +| SUBVL | `8:9` | Sub-vector length | +| EXTRA | `10:18` | context-dependent extra | +| MODE | `19:23` | changes Vector behaviour | +""" + +from nmigen import Record + +class SVP64Rec(Record): + def __init__(self, name=None): + Record.__init__([("mmode" : 1), + ("mask" : 3), + ("elwidth" : 2), + ("ewsrc" : 2), + ("extra" : 9), + ("mode" : 5), name=name) + -- 2.30.2