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convert CR to PowerDecodeSubset format
2020-09-07 Luke Kenneth Casson... convert CR to PowerDecodeSubset format
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2020-09-07 Luke Kenneth Casson... bit of a big reorg of data structures
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2020-09-07 Luke Kenneth Casson... split out PowerDecode2 into PowerDecodeSubset
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2020-09-07 Luke Kenneth Casson... large stack of moving stuff around in dcache
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2020-09-07 Luke Kenneth Casson... adjust indentation of dcache_slow
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2020-09-07 Luke Kenneth Casson... more dcache translation
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2020-09-07 Luke Kenneth Casson... add start on cache_ram.vhdl to nmigen conversion
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2020-09-07 Luke Kenneth Casson... more dcache translation
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2020-09-07 Luke Kenneth Casson... allow Decode2ToExecute1Type to take an opkls argument
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2020-09-07 Luke Kenneth Casson... whoops truncated the mb and me fields
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2020-09-07 Luke Kenneth Casson... minor reorg on PowerDecoder
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2020-09-06 Luke Kenneth Casson... comment, nothing unusual when Trap Type is DEC
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2020-09-06 Luke Kenneth Casson... decoder immediate b split out to DecodeBImm
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2020-09-06 Luke Kenneth Casson... decoder immediate a split out to DecodeAImm
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2020-09-06 Luke Kenneth Casson... add row subset selector for PowerDecode.
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2020-09-06 Luke Kenneth Casson... add row_subset (doesnt do anything yet)
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2020-09-06 Luke Kenneth Casson... pass col_subset throughout PowerDecoder
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2020-09-06 Luke Kenneth Casson... reorganise PowerOp to be dynamic
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2020-09-06 Luke Kenneth Casson... reorg of PowerOp to be able to dynamically subset it
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2020-09-06 Luke Kenneth Casson... grr, autopep8 messing up
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2020-09-06 Luke Kenneth Casson... copy dec SPR into decoder cur_state
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2020-09-06 Luke Kenneth Casson... add reset option to Register
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2020-09-06 Luke Kenneth Casson... wark-wark, fast regs is binary-addressed
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2020-09-06 Luke Kenneth Casson... add unit test for slow SPRs (SPRG0/1)
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2020-09-06 Luke Kenneth Casson... minor code-munge on SPR-to-FAST mapping
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2020-09-06 Luke Kenneth Casson... use with subTest in spr unit test
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2020-09-06 Luke Kenneth Casson... redo generation of microwatt.v from litex
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2020-09-06 Luke Kenneth Casson... add comments for DEC / TB
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2020-09-06 Luke Kenneth Casson... add a DEC/TB FSM to TestIssuer
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2020-09-06 Luke Kenneth Casson... move DEC and TB from StateRegs to FastRegs for several...
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2020-09-06 Luke Kenneth Casson... add DEC SPR to CoreState and PowerDecoder, activate...
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2020-09-06 Luke Kenneth Casson... add DEC and TB to State regfile
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2020-09-06 Luke Kenneth Casson... add DEC/TB SPRs to spr pipeline
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2020-09-05 Luke Kenneth Casson... add comments on MSR read
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2020-09-05 Luke Kenneth Casson... move GPIO IRQ to 15 to match microwatt modifications
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2020-09-05 Luke Kenneth Casson... hmmm XICS data being asserted on wb bus for too long
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2020-09-05 Luke Kenneth Casson... argh missed a VHDL "&" translating to Cat
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2020-09-05 Luke Kenneth Casson... reduce XICS address lookup by 2 bits
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2020-09-05 Luke Kenneth Casson... MSR read in INSN_READ only occurs for 1 cycle
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2020-09-05 Luke Kenneth Casson... sync on ICP eint
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2020-09-05 Luke Kenneth Casson... connect XICS core irq to Decode2 eint
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2020-09-05 Luke Kenneth Casson... whoops, combinatorial loop on pending_priority
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2020-09-05 Luke Kenneth Casson... use stbcix in test
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2020-09-05 Luke Kenneth Casson... XICS addresses in words: divide by 4
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2020-09-05 Luke Kenneth Casson... whoops, ICS in litex sim needs to be 0x1000 size region
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2020-09-05 Luke Kenneth Casson... add lwzcix unit test
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2020-09-05 Luke Kenneth Casson... increase wishbone address width to 29 for xics and...
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2020-09-05 Luke Kenneth Casson... submodule update
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2020-09-05 Luke Kenneth Casson... add simple GPIO wishbone bus to litex sim.py
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2020-09-05 Luke Kenneth Casson... add stbcix and lwzcix to power_enum list
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2020-09-05 Luke Kenneth Casson... add simple GPIO peripheral to verilog TestIssuer
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2020-09-05 Luke Kenneth Casson... move wb read/write to separate util test library and...
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2020-09-05 Luke Kenneth Casson... add simple wishbone GPIO peripheral
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2020-09-04 Luke Kenneth Casson... add sld test with RB=64 to see what happens
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2020-09-04 Luke Kenneth Casson... reduce CSR data width to 8 as an experiment
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2020-09-04 Luke Kenneth Casson... add UART reserved IRQ @ 0
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2020-09-04 Luke Kenneth Casson... add XICS memory regions, shrink litex CSR memmap size...
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2020-09-04 Luke Kenneth Casson... adding XICS wb slave devices to litex sim
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2020-09-04 Luke Kenneth Casson... bring out XICS ICS interrupt levels so that they can...
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2020-09-04 Luke Kenneth Casson... adding option to include XICS external interrupts.
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2020-09-04 Luke Kenneth Casson... add means to run hello_world.bin under simulation
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2020-09-03 Luke Kenneth Casson... do more on dcache conversion
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2020-09-03 Luke Kenneth Casson... testing microwatt 3.bin (2.bin ok)
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2020-09-02 Luke Kenneth Casson... when mtocrf FXM is 0, the CR has to be set to CR7
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2020-09-02 Luke Kenneth Casson... fix bug in cmpli (and cmplw)
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2020-09-02 Luke Kenneth Casson... sign-extend lhax needs 16-64, separate from lwax which...
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2020-09-02 Luke Kenneth Casson... add bc ctr regression test when CTR=0 and CTR=1
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2020-09-02 Luke Kenneth Casson... update submodule
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2020-09-02 Luke Kenneth Casson... bug in carry32 handling in OP_CMP
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2020-09-02 Luke Kenneth Casson... add cmpl regression test (one binary, one assembly)
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2020-09-02 Luke Kenneth Casson... add cmpl microwatt 1.bin test, cmpl
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2020-09-02 Luke Kenneth Casson... series of extensive modifications to fix long-standing...
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2020-08-31 Luke Kenneth Casson... add XER to fastregs and "construct" it in mfspr/mtspr
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2020-08-30 Luke Kenneth Casson... redo OP_CMP based on microwatt. L=1 had been ignored
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2020-08-30 Luke Kenneth Casson... reversal of FXM mask for one-hot selection in OP_MTCR...
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2020-08-30 Luke Kenneth Casson... working on dcache.py
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2020-08-30 Luke Kenneth Casson... tidyup on mul proof
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2020-08-30 Luke Kenneth Casson... set mul post_stage o.ok only when needed, and fix xer_so...
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2020-08-29 Luke Kenneth Casson... minor code-shuffle, comments
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2020-08-29 Luke Kenneth Casson... slowly morphing towards using an XER bit-field selector...
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2020-08-29 Luke Kenneth Casson... break down XER into flags
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2020-08-29 Luke Kenneth Casson... add XER read via DMI interface to sim.py
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2020-08-29 Luke Kenneth Casson... add hack to get at XER through DMI interface
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2020-08-29 Luke Kenneth Casson... submodule update
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2020-08-29 Luke Kenneth Casson... yep disable OE for MULH64/32 and EXTS and CNTZ
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2020-08-29 Luke Kenneth Casson... investigating CR mtocrf / mfocrf
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2020-08-29 Luke Kenneth Casson... add additional CR regression tests
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2020-08-29 Luke Kenneth Casson... allow pseudocode numbering to decrement in for-loops
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2020-08-29 Luke Kenneth Casson... add wat to write out raw binary assembled programs
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2020-08-29 Luke Kenneth Casson... CR FXM becomes a full mask.
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2020-08-27 Luke Kenneth Casson... https://bugs.libre-soc.org/show_bug.cgi?id=476
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2020-08-27 Luke Kenneth Casson... xer so is not being passed through to CR0
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2020-08-27 Luke Kenneth Casson... really bad hack to fix simulator bug in carry handling
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2020-08-27 Luke Kenneth Casson... augment addme test case to show bug #476
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2020-08-27 Luke Kenneth Casson... add addze and addme uni tests
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2020-08-27 Luke Kenneth Casson... incompatibility with POWER9 on mulhw/u due to lack...
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2020-08-27 Luke Kenneth Casson... overflow-enable does not occur on shift operations
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2020-08-27 Luke Kenneth Casson... oink, write_cr shiftrot record width was zero (??)
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2020-08-27 Luke Kenneth Casson... sorting out shift_rot to use new output stage data...
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2020-08-27 Luke Kenneth Casson... need to read SO if Rc=1
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