git.libre-soc.org Git - soc.git/search

2020-12-06	Luke Kenneth Casson...	attempt to split into two separate GPIO banks due to...	commit \| commitdiff \| tree
2020-12-03	Luke Kenneth Casson...	put ls180 litex bus width back to 32 bit temporarily	commit \| commitdiff \| tree
2020-12-03	Luke Kenneth Casson...	argh issue with yosys ABC	commit \| commitdiff \| tree
2020-12-03	Luke Kenneth Casson...	add 3 more 4k SRAMs, change WB bus width to 64 in ls180...	commit \| commitdiff \| tree
2020-11-22	Luke Kenneth Casson...	simplify litex-core wishbone interfaces	commit \| commitdiff \| tree
2020-11-14	Luke Kenneth Casson...	sigh, direction wrong in IOtypes litex core	commit \| commitdiff \| tree
2020-11-13	Luke Kenneth Casson...	reduce number of nc in ls180 to 24	commit \| commitdiff \| tree
2020-11-13	Luke Kenneth Casson...	reduce clkcsel ls180 width (2 pins), rename pll_18...	commit \| commitdiff \| tree
2020-11-13	Luke Kenneth Casson...	rename and add pll lock signal to ls180	commit \| commitdiff \| tree
2020-11-13	Luke Kenneth Casson...	rename ls180 litex pll_48 output to pll_18	commit \| commitdiff \| tree
2020-11-13	Luke Kenneth Casson...	add enable/disable arguments (not ideal but it works...	commit \| commitdiff \| tree
2020-11-13	Luke Kenneth Casson...	remove io_in/out now it is not needed for niolib	commit \| commitdiff \| tree
2020-11-10	Luke Kenneth Casson...	add build commands to Makefile for versa ecp5	commit \| commitdiff \| tree
2020-11-10	Luke Kenneth Casson...	submodule update	commit \| commitdiff \| tree
2020-11-10	Luke Kenneth Casson...	remove ClockSelect module, use DummyPLL	commit \| commitdiff \| tree
2020-11-10	Luke Kenneth Casson...	add separate DummyPLL module, according to API discussed at	commit \| commitdiff \| tree
2020-11-07	Luke Kenneth Casson...	update submodule	commit \| commitdiff \| tree
2020-11-06	Luke Kenneth Casson...	sigh sorting out litex pin-connections to sdram	commit \| commitdiff \| tree
2020-11-04	Luke Kenneth Casson...	move back to 3.3v on X3 VERSA ECP5 connector	commit \| commitdiff \| tree
2020-11-03	Luke Kenneth Casson...	swap jtag pinorder to match ulx3s	commit \| commitdiff \| tree
2020-11-03	Luke Kenneth Casson...	change LVCMOS level on versa ecp5 jtag to 2.5v	commit \| commitdiff \| tree
2020-10-30	Luke Kenneth Casson...	add JTAG extension to versa_ecp5 then we can use it	commit \| commitdiff \| tree
2020-10-24	Luke Kenneth Casson...	submodule update	commit \| commitdiff \| tree
2020-10-22	Luke Kenneth Casson...	add query about cross-domain on the JTAG enable of WB	commit \| commitdiff \| tree
2020-10-22	Luke Kenneth Casson...	add detection and disable of Instruction Wishbone based...	commit \| commitdiff \| tree
2020-10-22	Luke Kenneth Casson...	add detection and disable of LoadStore Wishbone based...	commit \| commitdiff \| tree
2020-10-22	Luke Kenneth Casson...	add JTAG enable/disable of wishbone to TestIssuer	commit \| commitdiff \| tree
2020-10-22	Luke Kenneth Casson...	add means to JTAG interface to enable/disable "stuff...	commit \| commitdiff \| tree
2020-10-21	Luke Kenneth Casson...	fix up asserts (check correct pads/cores)	commit \| commitdiff \| tree
2020-10-16	Luke Kenneth Casson...	experiment swapping dummy trap stage over to input	commit \| commitdiff \| tree
2020-10-16	Luke Kenneth Casson...	re-enable tests	commit \| commitdiff \| tree
2020-10-16	Luke Kenneth Casson...	manually run coresync clock for test issuer	commit \| commitdiff \| tree
2020-10-16	Luke Kenneth Casson...	set defaults in pspec	commit \| commitdiff \| tree
2020-10-16	Luke Kenneth Casson...	update submodule	commit \| commitdiff \| tree
2020-10-16	Luke Kenneth Casson...	add extra (test dummy stage in trap to see if combinatorial...	commit \| commitdiff \| tree
2020-10-16	Luke Kenneth Casson...	add LGPLv3+ notice and add copyright holders	commit \| commitdiff \| tree
2020-10-15	Luke Kenneth Casson...	add commented-out connection to JTAG in ECP5 litex	commit \| commitdiff \| tree
2020-10-15	Luke Kenneth Casson...	wrong pspec variable in selecting pll clock	commit \| commitdiff \| tree
2020-10-15	Luke Kenneth Casson...	sorting out missing clock somewhere	commit \| commitdiff \| tree
2020-10-15	Luke Kenneth Casson...	use "enable" and set default actions in getopt	commit \| commitdiff \| tree
2020-10-15	Luke Kenneth Casson...	add extra variant to litex core	commit \| commitdiff \| tree
2020-10-15	Luke Kenneth Casson...	syntax error	commit \| commitdiff \| tree
2020-10-15	Luke Kenneth Casson...	disable gpio in litex core	commit \| commitdiff \| tree
2020-10-15	Luke Kenneth Casson...	enable/disable litex irqs based on variant name	commit \| commitdiff \| tree
2020-10-11	Luke Kenneth Casson...	add way to bypass PLL for ECP5 and sim	commit \| commitdiff \| tree
2020-10-11	Luke Kenneth Casson...	comment out XICS/GPIO interrupt test, causes ECP5 litex...	commit \| commitdiff \| tree
2020-10-11	Luke Kenneth Casson...	record commands for building ECP5	commit \| commitdiff \| tree
2020-10-11	Luke Kenneth Casson...	litex sim.py operational	commit \| commitdiff \| tree
2020-10-10	Luke Kenneth Casson...	add debug start/stop to firmware_upload script	commit \| commitdiff \| tree
2020-10-10	Luke Kenneth Casson...	add DMI status / reset to firmware upload script	commit \| commitdiff \| tree
2020-10-10	Luke Kenneth Casson...	add first version of firmware uploader	commit \| commitdiff \| tree
2020-10-09	Luke Kenneth Casson...	use libresoc version of c4m-jtag repo	commit \| commitdiff \| tree
2020-10-09	Luke Kenneth Casson...	submodule update	commit \| commitdiff \| tree
2020-10-09	Luke Kenneth Casson...	drop in "undefined" function into ISAcaller namespace	commit \| commitdiff \| tree
2020-10-09	Luke Kenneth Casson...	rename undef to undefined (preserving the fact that...	commit \| commitdiff \| tree
2020-10-09	Luke Kenneth Casson...	missing yields in JTAG pads test to allow settling	commit \| commitdiff \| tree
2020-10-08	Luke Kenneth Casson...	missing yields in JTAG pads test to allow settling	commit \| commitdiff \| tree
2020-10-08	Luke Kenneth Casson...	minor icache cleanup	commit \| commitdiff \| tree
2020-10-08	Luke Kenneth Casson...	add incoming PortInterface to be connected to LoadStoreCompUnit	commit \| commitdiff \| tree
2020-10-08	Luke Kenneth Casson...	JTAG boundary scan test 1st attempt	commit \| commitdiff \| tree
2020-10-08	Luke Kenneth Casson...	rework jtag test to use JTAG class not DMITAP	commit \| commitdiff \| tree
2020-10-08	Luke Kenneth Casson...	split out jtag util functions to separate module	commit \| commitdiff \| tree
2020-10-07	Luke Kenneth Casson...	missing invert_in field from shiftrot input record	commit \| commitdiff \| tree
2020-10-07	Luke Kenneth Casson...	git submodule update	commit \| commitdiff \| tree
2020-10-07	Luke Kenneth Casson...	reorder / reorganise reset signals slightly	commit \| commitdiff \| tree
2020-10-06	Luke Kenneth Casson...	update comments on pimem.py	commit \| commitdiff \| tree
2020-10-06	Luke Kenneth Casson...	comments	commit \| commitdiff \| tree
2020-10-06	Luke Kenneth Casson...	add ports function to DummyPLL	commit \| commitdiff \| tree
2020-10-06	Luke Kenneth Casson...	use pdecode2.do not pdecode2.e in test_pipe_caller...	commit \| commitdiff \| tree
2020-10-06	Luke Kenneth Casson...	skip Decode2ToOperand from PowerDecodeSubset	commit \| commitdiff \| tree
2020-10-06	Luke Kenneth Casson...	comment SRR1 mem.exception	commit \| commitdiff \| tree
2020-10-06	Luke Kenneth Casson...	add SRR1 setting for LDST memory exception trap	commit \| commitdiff \| tree
2020-10-06	Luke Kenneth Casson...	passing LDSTException over to Trap Pipeline	commit \| commitdiff \| tree
2020-10-06	Luke Kenneth Casson...	add LDSTException decode/handling in PowerDecoder2	commit \| commitdiff \| tree
2020-10-06	Luke Kenneth Casson...	make LDSTException fields added from list of fieldnames	commit \| commitdiff \| tree
2020-10-06	Luke Kenneth Casson...	move LDSTException to mem_types	commit \| commitdiff \| tree
2020-10-06	Luke Kenneth Casson...	submodule update	commit \| commitdiff \| tree
2020-10-06	Luke Kenneth Casson...	add LDSTException to PortInterface	commit \| commitdiff \| tree
2020-10-06	Luke Kenneth Casson...	add sdr bypass routing via JTAG boundary scan	commit \| commitdiff \| tree
2020-10-05	Luke Kenneth Casson...	add debug / investigation print statements	commit \| commitdiff \| tree
2020-10-05	Luke Kenneth Casson...	whoops fix syntax error	commit \| commitdiff \| tree
2020-10-05	Luke Kenneth Casson...	whoops fix syntax error	commit \| commitdiff \| tree
2020-10-05	Luke Kenneth Casson...	return test rather than "if test return True else False"	commit \| commitdiff \| tree
2020-10-05	Luke Kenneth Casson...	whitespace	commit \| commitdiff \| tree
2020-10-05	Luke Kenneth Casson...	whitespace	commit \| commitdiff \| tree
2020-10-04	Luke Kenneth Casson...	significant reorg of the litex pinspecs to use pinmux...	commit \| commitdiff \| tree
2020-10-04	Luke Kenneth Casson...	submodule update	commit \| commitdiff \| tree
2020-10-04	Luke Kenneth Casson...	remove ls180io import	commit \| commitdiff \| tree
2020-10-04	Luke Kenneth Casson...	move ls180io.py back into ls180.py	commit \| commitdiff \| tree
2020-10-03	Luke Kenneth Casson...	allow i2c to be routed via JTAG	commit \| commitdiff \| tree
2020-10-03	Luke Kenneth Casson...	nope. put it back and connect to platform pads in...	commit \| commitdiff \| tree
2020-10-03	Luke Kenneth Casson...	move iopad litex creation to ls180soc.py	commit \| commitdiff \| tree
2020-10-03	Luke Kenneth Casson...	minor reorg on JTAG, allow alternative pinset dict...	commit \| commitdiff \| tree
2020-10-02	Luke Kenneth Casson...	add pinmux generator to create litex pinmap	commit \| commitdiff \| tree
2020-10-02	Luke Kenneth Casson...	add pinmux as submodule	commit \| commitdiff \| tree
2020-10-01	Luke Kenneth Casson...	arg CacheRam read output needs delay by 1 cycle	commit \| commitdiff \| tree
2020-10-01	Luke Kenneth Casson...	do not pass cache row array around, just the current row	commit \| commitdiff \| tree
2020-10-01	Luke Kenneth Casson...	revert bug in icache wishbone ack	commit \| commitdiff \| tree
2020-10-01	Luke Kenneth Casson...	add clksel, pll to ls180	commit \| commitdiff \| tree
2020-10-01	Luke Kenneth Casson...	create dummy PLL block, connect up to core and clock...	commit \| commitdiff \| tree
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